49th week of 2012 patent applcation highlights part 69 |
Patent application number | Title | Published |
20120311164 | METHOD OF CONTROLLING CONNECTION ESTABLISHMENT IN A WIRELESS NETWORK - A method of controlling connection establishment to transmit or receive A/V data in a wireless network is provided. The method of controlling connection establishment to transmit or receive A/V data in a first device of a wireless network that includes a coordinator and at least one device comprises transmitting connection request information required to request connection establishment with a second device and a connection request message which includes capability information of the first device to the second device and receiving a connection response message from the second device in response to the connection request message. | 2012-12-06 |
20120311165 | SELECTIVE ADMISSION INTO A NETWORK SHARING SESSION - A system and method provide for the selective authorization and admission of a client into a data sharing session with a host. A host may select one or more clients into the sharing session based on the proximity of the clients. When a client is selected, an identifier is provided from the client device to the host device, for example, utilizing an optical identifier such as a bar code or an audible identifier such as an encoded sound. The identifier is then utilized to establish a link between the client and the host. In this fashion any number of client devices may be selectively admitted into the sharing session in a quick and easy process enabling security for the host and anonymity for the client. | 2012-12-06 |
20120311166 | Pipe Selection Heuristics - A method and apparatus of a device that manages connection pairs between a pair of devices is described. The device receives a metric from an application that indicates a preference to be used in suggesting a connection pair between a pair of devices. The device further receives characteristics of the connection pairs and selects one of the connection pairs based on these characteristics and the application metric. The device suggests the selected connection pair to the application. | 2012-12-06 |
20120311167 | NON-INTRUSIVE SINGLE SIGN-ON MECHANISM IN CLOUD SERVICES - A method and apparatus for Single Sign-on, wherein the user accesses a platform server and at least one service provider on the platform server. The method includes intercepting a request sent by the user via a client browser and extracting a domain name included in the request. If the domain name is an original domain name of the platform server, a global session ID is generated for uniquely identifying a session between the user and the platform server. A new domain name of the platform server associated with the global session ID is generated and the URL in the request is redirected to a new URL including the new domain name of the platform server. The request, including the new URL of the platform server, is forwarded to the platform server. | 2012-12-06 |
20120311168 | METHOD FOR IMPROVING ACCURACY IN COMPUTATION OF ONE-WAY TRANSFER TIME FOR NETWORK TIME SYNCHRONIZATION - A method for improving accuracy in the computation of a one-way transfer time between two networked devices. In one aspect, variability in time transfer latency that is caused by cache loading, data structure setup time, and scheduling variability in software is reduced by initiating a first sequence of loading data structures into cache and priming scheduling, and then initiating a second sequence of calibrating the timing of a subsequent synchronization message so that the completion of the first sequence occurs just in time for the reception of the synchronization message. The method is applicable for any network time synchronization protocol, including Network Time Protocol (NTP) and Precision Time Protocol (PTP). | 2012-12-06 |
20120311169 | NETWORK RELAY APPARATUS - A network relay apparatus which conducts data transfer by using a plurality of network LSIs includes a transfer engine unit having at least two network LSIs and a central control unit which controls the operation state of the network relay apparatus. The transfer engine unit includes the network LSIs capable of changing over at least one of a clock and an operation which differ every function block, a load judgment unit for judging a load laid upon each of function blocks in the network LSI, and a frequency voltage control unit for individually changing over at least one of the clock and operation voltage supplied to each function block on the basis of the load judged by the load judgment unit. | 2012-12-06 |
20120311170 | METHOD AND APPARATUS FOR INEXPENSIVELY MONITORING AND CONTROLLING REMOTELY DISTRIBUTED APPLIANCES - A method and associated apparatus are described that enables unattended, remotely distributed appliances, such as vending machines, utility meters, thermostats and kitchen appliances (ovens, washing machines, refrigerators, etc.) to be connected inexpensively to each other and to a centrally located server. The apparatus 1) uses relatively simple “personality” modules to adapt the apparatus to the application in combination with a sophisticated core module that provides the intelligence needed to process data locally, to format that data and to transfer it to a remote server and 2) uses existing Internet-based communication links, thereby avoiding the costly proprietary links used with current state-of-the-art solutions. | 2012-12-06 |
20120311171 | APPARATUS, SYSTEMS AND METHODS FOR MONITORING THE TRANSMISSION OF MEDIA CONTENT EVENTS - Systems and methods are operable for monitoring the transmission of media content events. An exemplary embodiment receives a media content stream at a media device from a media content transmission device at a first transmission rate, wherein the media content stream comprises at least one media content event selected for presentation on a media presentation device; stores at least a portion of the media content stream in a media device buffer; calculates a buffer metric; transmitting the buffer metric to the media content transmission device; and receives the media content stream from the media content transmission device at a second transmission rate based on the transmitted buffer metric. | 2012-12-06 |
20120311172 | OVERLOADING PROCESSING UNITS IN A DISTRIBUTED ENVIRONMENT - Techniques are disclosed for overloading, at one or more nodes, an output of data streams containing data tuples. A first plurality of tuples is received via a first data stream and a second plurality of tuples is received via a second data stream. A first value associated with the first data stream and a second value associated with the second data stream are established based on a specified metric. A third plurality of tuples is output based on the first value and the second value, wherein the third plurality of tuples is a subset of the first plurality of tuples and the second plurality of tuples. | 2012-12-06 |
20120311173 | Dynamic Wireless Channel Selection And Protocol Control For Streaming Media - Dynamic wireless channel selection and protocol control for streaming video utilizing transmission delay/packet loss information and channel utilization statistics. A transmission delay and packet loss monitor generates transmission delay information during the transmission of a video stream to remote wireless device(s) over a first wireless channel by timestamping and monitoring video packet(s) and associated transmission acknowledgement(s). The transmission delay information is compared to a predetermined threshold (e.g., a maximum tolerated delay threshold and/or total packet loss threshold) and, if the threshold is exceeded, a second wireless channel is selected for continued transmission of the video stream. In one mode, channel utilization statistics are likewise examined prior to a channel relocation event. Selection of the second wireless channel may be accomplished through a random or semi-random channel selection process, or through active scanning to collect clear channel assessment statistics for candidate channels. In another mode, at least one transmission protocol parameter is altered in response to a violation of one or more of the predetermined thresholds. | 2012-12-06 |
20120311174 | MULTIPATH DELIVERY FOR ADAPTIVE STREAMING - A method for delivering content via adaptive streaming technique over multiple communication paths and a device implementing the method are disclosed. | 2012-12-06 |
20120311175 | GUARANTEED BANDWIDTH MEMORY APPARATUS AND METHOD - Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests. | 2012-12-06 |
20120311176 | METHOD FOR OPTIMIZING TRANSPORT CHANNELS OF DEVICES - A first device and a second device communicate with each other using a first communications protocol over a first communications media. The first device detects a need to modify a communications bandwidth with the second device based on an operating condition of the first device at a point in time. The first device negotiates with the second device to identify a second communications protocol that is suitable for the operating condition based on a set of one or more rules associated with the first device. Both the first and second devices switch, without user intervention, from the first communications protocol to the second communications protocol to communicate with the second device using the second communications protocol over a second communications media. | 2012-12-06 |
20120311177 | DYNAMIC VARIABLE RATE MEDIA DELIVERY SYSTEM - A method and apparatus for dynamically transcoding and delivering variable bit rate media files delivers media files to client systems. The media server dynamically transcodes a content file to a bit rate requested by a client using an original content file or other transcoded content files. The media server can dynamically select a segment of a content file to transcode. The file format required by the client is determined and the transcoded segment is formatted to the file format. The formatted segment is delivered to the client. | 2012-12-06 |
20120311178 | SELF-DISRUPTING NETWORK ELEMENT - A method, apparatus, and machine readable storage medium is disclosed for establishing a test protocol processor which identifies and removes messages from a network element port buffer. Subsequent to removal the test protocol processor may perform one of several actions including allowing the message to drop, replacing the message after a delay, replacing the message after altering the payload of the message, and replacing the message after altering the message type. The disclosed self disrupting network element is particularly useful for providing a means to perform in situ field testing of network performance indicators. | 2012-12-06 |
20120311179 | METHOD FOR PROCESSING TCP RE-TRANSMISSION BASED ON FIXED ADDRESS - The present invention relates to a technology where, in the state that start pointers for n transmit buffers each having Ethernet frame size are fixedly declared and thus fixed addresses are assigned to the transmit buffers, packets can be stably retransmitted utilizing the fixed addresses of the transmit buffers, without executing dynamic pointer operations in re-transmission. | 2012-12-06 |
20120311180 | FACILITATING ROUTING BY SELECTIVELY AGGREGATING CONTIGUOUS DATA UNITS - Aggregation of contiguous data packets, such as contiguous I/O adapter stores, is disclosed. Commensurate with receiving data packets to be written to a memory, multiple contiguous data units of the data packets are aggregated into an aggregated data block. The aggregated data block is validated for writing to memory responsive to either the aggregated data block reaching a size which with inclusion of a next contiguous data unit in the aggregated data block would result in the aggregated data block exceeding a configurable size limit, or a next data unit of the plurality of data units to be written to memory being non-contiguous with the multiple contiguous data units. | 2012-12-06 |
20120311181 | SYSTEMS AND METHODS FOR FACILITATING COMMUNICATION WITH FOUNDATION FIELDBUS LINKING DEVICES - Systems and methods for facilitating communication with Foundation Fieldbus linking devices are described. A first Foundation Fieldbus linking device associated with a first Ethernet network and a second Foundation Fieldbus linking device associated with a second Ethernet network may be identified by a gateway device that includes one or more computers. At least one virtual address representative of the first linking device and the second linking device may be determined by the gateway device. Communications between the first and second linking devices and an external system may be facilitated by the gateway device, and the at least one virtual address may be utilized to represent the linking devices to the external system. | 2012-12-06 |
20120311182 | SYSTEM AND METHOD FOR SUPPORTING CONTROLLED RE-ROUTING IN AN INFINIBAND (IB) NETWORK - A system and method can support controlled re-routing in an InfiniBand (IB) fabric. The fabric is associated with a subnet manager that can detect a connectivity change in the fabric, and re-rout the fabric accordingly. The subnet manager can ensure that only accredited components and connectivity are utilized in the re-routing, and represent the connectivity that is not accredited within a local subnet or sub-subnet. The subnet manager can further maintain a node record or fabric configuration for evaluating the detected connectivity change in the fabric. | 2012-12-06 |
20120311183 | CIRCUITRY TO MAINTAIN CORRELATION BETWEEN SETS OF ADDRESSES - An embodiment may include circuitry in a controller that may be included in a host that has at least one processor. The circuitry may maintain a correlation between a set of network addresses and a set of medium access control (MAC) addresses. The correlation may be generated, at least in part, by at least one process to be executed, at least in part, by the at least one processor. The circuitry may determine, based at least in part upon the set of network addresses, whether to generate at least one response to at least one request. If the circuitry determines to generate the at least one response, the circuitry may generate the at least one response based at least in part upon the correlation and at least one network address associated with the at least one request. Many alternatives, variations, and modifications are possible. | 2012-12-06 |
20120311184 | IP Address Assignment System, Dynamic Host Configuration Protocol Server, And Method Of Assigning An IP Address - A DHCP server assigning an IP address to a client. The DHCP server stores an exclusive address range corresponding to a range of IP addresses assignable to the client, assigns an IP address to the client with a lease period when a request for assignment of new IP address is received from the client, and sends a permission for extension to the client, irrespective of whether an assigned IP address is included in the exclusive address range, as long as the assigned IP address is included in the entire network address range, when a request for extension of the lease period with regard to the assigned IP address is received from the client. | 2012-12-06 |
20120311185 | DATA TRANSMISSION BASED ON ADDRESS TRANSLATION - Data transmission based on address translation, comprising: sending to a Dynamic Host Configuration Protocol (DHCP) server a request message requesting a public network address by an Network Address Translation (NAT) device; receiving a response message carrying the public network address returned by the DHCP server by the NAT device, performing address translation to said data through said public network address, and sending the translated data to an external network device. | 2012-12-06 |
20120311186 | METHOD, FRAMEWORK, AND PROGRAM PRODUCT FOR FORMATTING AND SERVING WEB CONTENT - The present invention provides an approach and corresponding framework that separates data from its formatting/view by generating the dynamic JavaScript (data) as a set (e.g., at least one) of JavaScript (data) objects, without any HTML formatting. Then, a set of JavaScript functions can be created that takes the set of JavaScript objects as a parameter, and outputs all or a subset of this data object in a format determined by this JavaScript function. In general, these formatting functions can be static, rather than dynamic, JavaScript. This approach has the advantage of providing a much greater degree of formatting flexibility, without the need for each new format to establish a connection with the back-end system providing the data. | 2012-12-06 |
20120311187 | Media Server and Method for Audio/Video Transmission - The present invention discloses a media server, which is connected with content networks, and linked with an information terminal via Wireless Fidelity (WiFi). The media server comprises an information receiving and transmitting controller as well as a Web server; wherein, the information receiving and transmitting controller is used to receive contents sent by the content networks, and to convert audio and video data of the contents into a format of the Real-Time Transport Protocol/Real-Time Transport Control Protocol (RTP/RTCP) encapsulation, then to transmit the converted data to the information terminal, additionally, to form a content directory in a HTML format according to the contents; the Web server is used to publish the content directory in the HTML format, which is formed by the information receiving and transmitting controller, so as to be accessed by the information terminal. The present invention also discloses a method for transmitting audio and video. | 2012-12-06 |
20120311188 | Method and Device for Data Segmentation in Data Compression - A method and device for data segmentation in data compression are disclosed. The method includes: acquiring a segmentation rule corresponding to the length of a current unsegmented data stream according to the length of the current unsegmented data stream in a data stream to be compressed, whereas the length of the unsegmented data stream increases, the probability that the corresponding segmentation rule is satisfied increases monotonically, and when the segmentation rule corresponding to a first length is satisfied, the segmentation rule corresponding to a second length is definitely satisfied too; where the first length and the second length are the length of the unsegmented data stream, and the first length is smaller than the second length; and segmenting, by using the segmentation rule, the data stream to be compressed. | 2012-12-06 |
20120311189 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND RECORDING MEDIUM - A disclosed information processing apparatus is connected to an information management apparatus via a network. The information processing apparatus includes a data storage unit configured to store data that specifies the information management apparatus as an access destination, and a synchronization controller unit configured to periodically compare a list of data stored in the data storage unit and a list of data stored in the information management apparatus, transmit data stored only in the data storage unit to the information management apparatus, and acquire data stored only in the information management apparatus from the information management apparatus and store the acquired data in the data storage unit. | 2012-12-06 |
20120311190 | COMMUNICATION NETWORK SYSTEM, GATEWAY, DATA COMMUNICATION METHOD AND PROGRAM PROVIDING MEDIUM - This invention relates to provide a communication network system, a gateway, and a data communication method, in which the gateway has an advanced functionality. A person who issues an access request can retrieve a desired access destination easily by the following configuration: functions of routing information providing and authentication processing are added to a gateway that performs protocol conversion between two different communication networks; when an access request is issued from a public communication network such as Internet to a terminal in a local (private) communication network connected to the gateway, a request terminal is authenticated to enable prevention of unauthorized data writing and reading; and an access request user who succeeded in the authentication is provided with an active terminal list comprising accessible terminal information, or with a user condition table. | 2012-12-06 |
20120311191 | WIRELESS MODEM DEVICE USABLE ON COMPUTER DEVICE WITHOUT DRIVER INSTALLATION - A method and apparatus is provided for connecting a computer device to a communication network, the computer device being provided with an operating system using a kernel protocol stack to connect to a pool of first communication networks known to an administrator of the computer device. The method includes introducing a second protocol stack, aside from the kernel protocol stack, for connecting the computer device to a second communication network not belonging to the known pool of first communication networks. | 2012-12-06 |
20120311192 | FIBRE CHANNEL INPUT/OUTPUT DATA ROUTING SYSTEM AND METHOD - A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW. | 2012-12-06 |
20120311193 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device. | 2012-12-06 |
20120311194 | PARTIAL SORT ON A HOST - A host devices transfers client data from a client device to the host device. The host device generates sort keys for host data that includes the client data. The host device sorts the host data using the sort keys and transfers the sorted host data to the client device. The client data and host data may include music, video, or other content. | 2012-12-06 |
20120311195 | METHOD, SYSTEM AND COMPUTER-READABLE MEDIUM FOR SWITCHING ACCESS MODE OF HARD DRIVE - A method for switching access mode of a hard drive is provided. The method includes the following steps: detecting and writing digitally current access mode as a current registry code of a system registration information by a processing unit, then overwriting the current registry code with a new registry code that corresponds to a new access mode other than the current access mode by the processing unit, and then reloading the system registration information by the processing unit, and then changing the current access mode to the new access mode correspondingly by a Basic Input/Output System (BIOS). In addition, a system executing the method and a computer-readable medium encoded with processing instructions for implementing the method are also provided. | 2012-12-06 |
20120311196 | Information Processing Apparatus and Tangible Computer-Readable Recording Medium - Disclosed is an information processing apparatus including: a display unit; a connection I/F unit to receive a connection to a withdrawable electronic device; and a control unit to detect an insertion operation or a withdrawal operation; wherein when the control unit detects the insertion operation, the control unit instructs the display unit to display contents corresponding to the electronic device connected to the connection I/F unit by the insertion operation so as to move the contents in a direction which is same as a direction of the detected insertion operation, and when the control unit detects the withdrawal operation, the control unit instructs the display unit to display the contents corresponding to the electronic device withdrawn from the connection I/F unit by the withdrawal operation so as to move the contents in a direction which is same as a direction of the detected withdrawal operation. | 2012-12-06 |
20120311197 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer. | 2012-12-06 |
20120311198 | FIBRE CHANNEL INPUT/OUTPUT DATA ROUTING SYSTEM AND METHOD - A computer program product is provided for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating at least one address control word (ACW) in the local channel memory specifying one or more host memory locations for transfer of data between the host and a control unit and including at least one ACW error checking field; generating an address control structure specifying a location in the local channel memory of a corresponding ACW and including at least one address control structure error checking field; receiving a data transfer request from the network interface that includes the addressing information; comparing the at least one ACW error checking field to the at least one address control structure error checking field; and, responsive to the fields matching, routing the data transfer request to the host memory location specified in the corresponding ACW. | 2012-12-06 |
20120311199 | FIBRE CHANNEL INPUT/OUTPUT DATA ROUTING INCLUDING DISCARDING OF DATA TRANSFER REQUESTS IN RESPONSE TO ERROR DETECTION - A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW. | 2012-12-06 |
20120311200 | FIBRE CHANNEL INPUT/OUTPUT DATA ROUTING SYSTEM AND METHOD - A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order. | 2012-12-06 |
20120311201 | PARTITIONING OF A VARIABLE LENGTH SCATTER GATHER LIST - Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel. | 2012-12-06 |
20120311202 | FAST CANCELLATION OF INPUT-OUTPUT REQUESTS - A method, system, and computer program product for fast cancellation of an I/O request in a data processing system are provided in the illustrative embodiments. A first component in a stack comprising a plurality of components determines whether a memory buffer associated with the I/O request is valid, the memory buffer being an addressable area in a memory in the data processing system. The first component, responsive to the memory buffer being valid, creates a first request data structure corresponding to the I/O request, wherein the first request data structure includes a reference to the memory buffer. The first component passes the first request data structure to a second component in the stack. | 2012-12-06 |
20120311203 | USB SWITCH WHICH ALLOWS PRIMARY USB CONNECTION IN RESPONSE TO USB SIGNALING - System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device. | 2012-12-06 |
20120311204 | STORAGE SYSTEM COMPRISING MICROPROCESSOR LOAD DISTRIBUTION FUNCTION - Among a plurality of microprocessors | 2012-12-06 |
20120311205 | MESSAGE FLOW REROUTING FOR SELF-DISRUPTING NETWORK ELEMENT - A method, apparatus, and machine readable storage medium is disclosed for establishing a test protocol processor which intercepts success path protocol messages at a network element port buffer and substitutes a failure path message to simulate the introduction of unexpected protocol messages into the protocol message flow from an external source to the network element under test. The disclosed self disrupting network element is particularly useful for providing a means to perform in situ field testing of a network element. | 2012-12-06 |
20120311206 | FACILITATING PROCESSING IN A COMMUNICATIONS ENVIRONMENT USING STOP SIGNALING - Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result. | 2012-12-06 |
20120311207 | MEDIATING COMMUNCIATION OF A UNIVERAL SERIAL BUS DEVICE - An apparatus for mediating communication between a universal serial bus (USB) device and a host computing device is described. In an example, the apparatus includes a USB host interface configured to be connected to a downstream USB device, and a USB device interface configured to be connected to an upstream host computing device. The apparatus also includes a mediation module positioned between the USB host interface and the USB device interface and configured to determine whether the USB device is authorized to communicate with the host computing device. | 2012-12-06 |
20120311208 | METHOD AND SYSTEM FOR PROCESSING COMMANDS ON AN INFINIBAND HOST CHANNEL ADAPTOR - A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network. | 2012-12-06 |
20120311209 | SYSTEM, CIRCUIT AND METHOD FOR IMPROVING SYSTEM-ON-CHIP BANDWIDTH PERFORMANCE FOR HIGH LATENCY PERIPHERAL READ ACCESSES - A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request. | 2012-12-06 |
20120311210 | SYSTEM AND METHOD FOR OPTIMIZING SLAVE TRANSACTION ID WIDTH BASED ON SPARSE CONNECTION IN MULTILAYER MULTILEVEL INTERCONNECT SYSTEM-ON-CHIP ARCHITECTURE - A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information. | 2012-12-06 |
20120311211 | METHOD AND SYSTEM FOR CONTROLLING INTER-INTEGRATED CIRCUIT (I2C) BUS - The present invention discloses a method and a system for controlling an Inter-Integrated Circuit (I2C) bus. The method comprises: dividing a Serial Clock Line (SCL) signal collected from an I2C bus of a master device into a plurality of paths of signals and extending the signals to I2C buses of slave devices, by a Complex Programmable Logic Device (CPLD); judging a current state of data and determining a direction of a current Serial Data Line (SDA) signal, between the SDA signal collected from the I2C bus of the master device and the SDA signal collected from the I2C bus of the slave device. The system can reduce cost and design complexity of a single-board. | 2012-12-06 |
20120311212 | AVOIDING NON-POSTED REQUEST DEADLOCKS IN DEVICES - Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations. | 2012-12-06 |
20120311213 | AVOIDING NON-POSTED REQUEST DEADLOCKS IN DEVICES - Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations. | 2012-12-06 |
20120311214 | ARBITRATION CIRCUIT AND ARBITRATION METHOD THEREOF - An arbitration circuit and an arbitration method thereof are provided to arbitrate requests from a plurality of data processing devices for access to a shared resource. The arbitration method has steps of generating a first data stream for respectively identifying whether the data processing devices are currently serviced, generating a second data stream for identifying whether the data processing devices issue any request for access the shared resource, and performing AND operations on the first and second data streams in parallel to generate a third data stream that is used for determining which of the requests may be granted. Because the requests are processed in parallel, the arbitration time can be reduced. | 2012-12-06 |
20120311215 | PERIPHERAL COMPONENT INTERCONNECT EXPRESS EXPANSION SYSTEM AND METHOD - A peripheral component interconnect express (PCIe) expansion system used to set a motherboard PCIe slot arranged on a motherboard to work in a transmission mode with different transmission lanes includes a basic input/output system (BIOS) set on the motherboard and an expansion card. The expansion card includes a circuit board, three expansion PCIe slots arranged on the circuit board, a converting chip used to detect whether there is a device plugged into any one of the expansion PCIe slots, and an edge connector set on a side of the circuit board to be engaged in the motherboard PCIe slot. The BIOS chip used to set the transmission mode of the motherboard PCIe slot according to a detection result obtained by the converting chip. | 2012-12-06 |
20120311216 | Multifunction Computer Dock - A multifunction dock station for portable computer is disclosed. The dock includes a connection port, a switch, a controller, a network-attached storage (NAS) and an I/O bus for connecting input/output or storage devices. The connection port is used for connecting a computer and electrically connects to the controller and switch. The switch is controlled by the controller and has a group of common pins connecting the connection port and two groups of switching pins separately connecting the NAS and I/O bus. The switch connects the NAS and connection port when the connection port is not connected by a computer. The switch connects the I/O bus and connection port when the connection port is connected by a computer. | 2012-12-06 |
20120311217 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 2012-12-06 |
20120311218 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 2012-12-06 |
20120311219 | Patient Monitoring Platform Interface - Physical monitoring systems are disclosed which may include a platform interface between a platform device and a monitoring module. The platform interface may allow physiological information from a patient such as sensor signal data, physiological trend data, other suitable data, or combinations thereof to be communicated from the monitoring module to the platform device. The platform interface may include a connector with pins configured to receive UART communications, transmit UART communications, communicate diagnostic information, be coupled to a ground, be coupled to a serial clock, receive serial data, transmit serial data, be coupled to a regulated power supply, be coupled to an unregulated power supply, communicate using USB standard, communicate using any other suitable standards, perform any other suitable functions, or any combinations thereof. The monitoring module may connect directly to the platform device, or a wired cable with suitable connectors may be used to electrically couple the monitoring module to the platform device. | 2012-12-06 |
20120311220 | COMPUTER BUS WITH ENHANCED FUNCTIONALITY - A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability. | 2012-12-06 |
20120311221 | USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH - The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy. | 2012-12-06 |
20120311222 | IMPLEMENTING DEVICE PHYSICAL LOCATION IDENTIFICATION IN SERIAL ATTACHED SCSI (SAS) FABRIC USING RESOURCE PATH GROUPS - A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device. | 2012-12-06 |
20120311223 | INFORMATION SYSTEM - An information system includes a configuration controller board having a capability to set, to each I/O bus bridge device in the alternative I/O board, the logical bus number set in corresponding I/O bus bridge device in the failed I/O board | 2012-12-06 |
20120311224 | EXPOSING EXPANDERS IN A DATA STORAGE FABRIC - A method of selectively exposing expanders in a data storage fabric is disclosed. The method includes generating a phy permission table in a switch expander. The phy permission table is configured for access by an initiator and includes data as to which enclosure expanders are discoverable by the initiator. A zone group of phys from the enclosure expanders assigned to the initiator is created. The phy permission table is updated to identify each phy coupled to the enclosure expanders in the zone group. | 2012-12-06 |
20120311225 | DEVICE DRIVER-LEVEL APPROACH FOR UTILIZING A SINGLE SET OF INTERFACE INPUT DEVICES FOR MULTIPLE COMPUTING DEVICES - A method for switching interface device input between computing devices can begin with connecting a primary computing device to a secondary computing device using a physical connector cable using the appropriate communications port of each computing device. An interface input control program can be configured to establish a unique interface trigger that defines a user-selected series of inputs that switches the primary computing device between a first input state and a second input state. Input from the interface input devices of the primary computing device can be interpreted by a device driver. In the first input state, the input can be directed to the operating system of the primary computing device. In the second input state, the input can be redirected to the secondary computing device via the physical connector cable, which can be recognized as having originated from local interface input devices. | 2012-12-06 |
20120311226 | COMPUTER APPARATUS, COMPUTER SYSTEM AND ADAPTER CARRY-OVER METHOD - To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers. | 2012-12-06 |
20120311227 | INFORMATION STORAGE SYSTEM, SNAPSHOT ACQUISITION METHOD, AND DATA STORAGE MEDIUM - The information storage system of an aspect of the present invention includes a first differential data storage area which stores differential data of a higher volume from a first point of time to a second point of time, a lower snapshot manager which provides a lower snapshot at the second point of time of the higher volume, and a second differential data storage area which stores differential data of the higher volume after the second point of time. The higher snapshot manager acquires a plurality of generations of higher snapshots from the lower snapshot and the data in the first differential data storage area and acquires a plurality of generations of higher snapshots from the data of the higher volume and the data in the second differential data storage area. | 2012-12-06 |
20120311228 | METHOD AND APPARATUS FOR PERFORMING MEMORY WEAR-LEVELING USING PASSIVE VARIABLE RESISTIVE MEMORY WRITE COUNTERS - Method and apparatus for performing wear-leveling using passive variable resistive memory (PVRM) based write counters are provided. In one example, a method for performing wear-leveling using passive PVRM based write counters is disclosed. The method includes associating a logical address of a memory array with a physical address of the memory array via at least one mapping table. Additionally, the method includes, in response to writing to the physical address of the memory array, incrementally updating at least one PVRM based write counter associated with the physical address of the memory array. The at least one PVRM based write counter may be incrementally updated by varying an amount of resistance stored in the at least one PVRM based write counter. | 2012-12-06 |
20120311229 | SYSTEM AND METHOD FOR RECORDING NUMBER OF POWER ON TIMES OF MOTHERBOARD - A powering on times recording system records powering on times of a motherboard, and includes a Basic Input/Output System (BIOS) Read Only Memory (ROM) chip installed on the motherboard. The BIOS ROM chip includes a first storage area storing a recording module and a second storage area storing a first variable data. When the motherboard is powered on, the recording module acquires the first variable data from the second storage area and increments the first variable data by one. The changed first variable data is recorded in the second storage area. | 2012-12-06 |
20120311230 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units. | 2012-12-06 |
20120311231 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs. | 2012-12-06 |
20120311232 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria. | 2012-12-06 |
20120311233 | SYSTEM AND METHOD FOR MANAGING A NON-VOLATILE MEMORY - A method, computer readable medium storing instructions and system for managing flash memory. Data sector are received and each is written into a data block of a buffer of a non-volatile memory device. Pointers in a data management structure are created for each data sector corresponding to an associated logical block and a storage location of the data sector in the buffer. When a predefined criterion is fulfilled before the buffer becomes full, a number of logical blocks to be merged is determined and data sectors corresponding to the number of logical blocks to be merged are written from the buffer to a primary non-volatile data storage memory of the non-volatile memory device. | 2012-12-06 |
20120311234 | INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD - According to one embodiment, an information processing apparatus includes a storage device, a volatile memory, and a processor. The storage device includes a controller, a first nonvolatile storage module, and a second nonvolatile storage module whose access speed is higher than an access speed of the first nonvolatile storage module. The processor is configured to execute an operating system and a cache driver that are loaded into the volatile memory. The cache driver uses at least part of an area in the second nonvolatile storage module as a cache for the first nonvolatile storage module. | 2012-12-06 |
20120311235 | MEMORY SYSTEM HAVING MULTIPLE CHANNELS AND METHOD OF GENERATING READ COMMANDS FOR COMPACTION IN MEMORY SYSTEM - According to one embodiment, a valid-cluster search module searches valid clusters included in first blocks, in each of channels, for compaction. A read command generator generates read commands used to read, in parallel, valid clusters to be migrated to a second block. The valid clusters searched in each of the channels comprise the valid clusters to be migrated. The valid clusters to be migrated correspond to a number of clusters simultaneously written to the second block and to a second number of channels in a first number of channels. A determination module determines the second number of channels corresponding to read commands to be generated next based on a situation of issuance of the read commands. | 2012-12-06 |
20120311236 | MEMORY SYSTEM, DATA CONTROL METHOD, AND DATA CONTROLLER - According to one embodiment, a memory system includes: a non-volatile memory; a storage configured to store therein data temporarily; a notifying module configured to notify a host of data transfer permission with a specified amount of data to be written in the storage; a transfer module configured to transfer data transferred from the host according to the data transfer permission to the storage, and to transfer the data stored in the storage to be written to the non-volatile memory; and a controller configured to inhibit notification of the data transfer permission by the notifying module until transfer of the data to the non-volatile memory by the transfer module is completed after an amount of data necessary to be written in the non-volatile memory is stored in the storage. | 2012-12-06 |
20120311237 | STORAGE DEVICE, STORAGE SYSTEM AND METHOD OF VIRTUALIZING A STORAGE DEVICE - A storage device includes a storage media including a one or more nonvolatile memories and a controller. The controller controls the nonvolatile memories, provides a virtual storage to an external host via at least one of the nonvolatile memories and erases a memory block of corresponding nonvolatile memory including data at physical addresses corresponding to data in the virtual storage. | 2012-12-06 |
20120311238 | MEMORY APPARATUS - A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table. | 2012-12-06 |
20120311239 | DATA INTERLEAVING SCHEME FOR AN EXTERNAL MEMORY OF A SECURE MICROCONTROLLER - The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words and are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively. | 2012-12-06 |
20120311240 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - The hibernation start-up by the kernel function takes a long time due to a processing time required for a normal boot sequence. When starting an operating system, the information processing apparatus according to the present invention determines whether to perform the hibernation start-up processing before initialization of a memory management mechanism. When the hibernation start-up processing is performed, a size of the memory management mechanism is reduced to a minimum size necessary for initializing the kernel and a hibernation image is read in parallel with initialization of hardware. The limited memory management area can be restored to a state free from a limitation by reading the hibernation image. | 2012-12-06 |
20120311241 | SCHEDULER FOR MEMORY - A scheduler controls execution in a memory of operation requests received in an input request set (IRS) by providing a corresponding output request set (ORS). The scheduler includes zone standby units having a one-to-one relationship with corresponding zones such that each zone standby unit stores an operation request. The scheduler also includes an output processing unit that determines a processing sequence for the operation requests stored in the zone standby units to provide the ORS. | 2012-12-06 |
20120311242 | DATA PROCESSING SYSTEM - A data processing system is provided, which can realize speeding up and facilitation of data processing using a program and a parameter of a scale larger than the maximum storage capacity of an available on-chip nonvolatile memory. A program and a parameter of a scale larger than the maximum storage capacity of the on-chip nonvolatile memory are stored in a nonvolatile semiconductor memory device coupled to the exterior of a semiconductor data processing device, and responding to the determination result of the information supplied from the exterior, the semiconductor data processing device downloads an internally required program and parameter from the nonvolatile semiconductor memory device, and rewrites the on-chip nonvolatile memory. When the program is rewritten, software reset processing is performed to execute the program from a starting address. | 2012-12-06 |
20120311243 | METHOD FOR INCREASING RELIABILITY OF DATA ACCESSING FOR A MULTI-LEVEL CELL TYPE NON-VOLATILE MEMORY - The primary object of the present invention is to provide a data accessing method for a multi level cell type non-volatile memory, including a plurality of storage cells, each storage cell has 0 | 2012-12-06 |
20120311244 | Balanced Performance for On-Chip Folding of Non-Volatile Memories - A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands. | 2012-12-06 |
20120311245 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 2012-12-06 |
20120311246 | System Including a Fine-Grained Memory and a Less-Fine-Grained Memory - A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations. | 2012-12-06 |
20120311247 | DATA READ METHOD FOR A PLURALITY OF HOST READ COMMANDS, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened. | 2012-12-06 |
20120311248 | CACHE LINE LOCK FOR PROVIDING DYNAMIC SPARING - A system that includes a memory, a cache, a purge mechanism, and a memory interface mechanism. The memory includes a failing memory element at a failing memory location. The cache is configured for storing corrected contents of the failing memory element in a locked state, with the corrected contents stored in a first cache line. The purge mechanism is configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations. The memory interface mechanism is configured for receiving a request to access the failing memory location, determining that corrected contents of the failing memory location are stored in first cache line in the cache, and accessing the first cache line in the cache. | 2012-12-06 |
20120311249 | MEMORY SYSTEM, MEMORY CONTROL METHOD, AND RECORDING MEDIUM STORING MEMORY CONTROL PROGRAM - A memory system includes a dual inline memory module (DIMM) connector to which a DIMM is connected, which is selected from a Joint Electron Device Engineering Council (JEDEC) standard DIMM in compliance with JEDEC standards and a customized DIMM not in compliance with JEDEC standard, and a memory controller to determine whether the DIMM being connected is the JEDEC standard DIMM or the customized DIMM to generate a determination result, and to control access to the DIMM based on the determination result and SPD information obtained from a SPD of the DIMM being connected. | 2012-12-06 |
20120311250 | ARCHITECTURE AND ACCESS METHOD OF HETEROGENEOUS MEMORIES - A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer. | 2012-12-06 |
20120311251 | Coordinating Memory Operations Using Memory-Device Generated Reference Signals - A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal. | 2012-12-06 |
20120311252 | DATA REPLICATION AMONG STORAGE SYSTEMS - A first storage system stores information relating to the updating of data stored in that system as a journal. More specifically, the journal is composed of a copy of data that was used for updating and update information such as a write command used during updating. Furthermore, the second storage system acquires the journal via a communication line between the first storage system and the second storage system. The second storage system holds a duplicate of the data held by the first storage system and updates the data corresponding to the data of the first storage system in the data update order of the first storage system by using the journal. | 2012-12-06 |
20120311253 | Reallocation of Tape Drive Resources Associated With a Secure Data Erase Process - A method according to one embodiment includes determining whether to reallocate one or more of a plurality of tape drives that are presently allocated for a secure data erase process in response to an evaluation of a quantity of physical volumes to be secure data erased and a minimum queued threshold; and in response to said determination that one or more of said plurality of tape drives is to be reallocated, reallocating the one or more of said plurality of tape drives from the secure data erase process to another function. | 2012-12-06 |
20120311254 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - An extended command is defined in compliance with the ATA standard. A selection number for selecting one of HDDs, one or more designated ATA commands, and an accessible time period including an available count are added to the extended command. As a result, designated normal ATA commands can access a certain one of the HDDs for a certain time period. | 2012-12-06 |
20120311255 | FULL-STRIPE-WRITE PROTOCOL FOR MAINTAINING PARITY COHERENCY IN A WRITE-BACK DISTRIBUTED REDUNDANCY DATA STORAGE SYSTEM - Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node. | 2012-12-06 |
20120311256 | COMPUTER SYSTEM FOR CONTROLLING ALLOCATION OF PHYSICAL LINKS AND METHOD THEREOF - The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device. | 2012-12-06 |
20120311257 | DISTRIBUTION WITH DYNAMIC PARTITIONS - A method and system for specifying at least one read-only partition and at least one read/write partition in a storage device to provide a convenient user experience. Upon initial connection to a computing system, a read-only partition is specified to execute an autorun file. After completion of the autorun file and upon subsequent connections to the computing system, a read/write partition is specified and the read-only partition is invisible to the user. | 2012-12-06 |
20120311258 | METHODS FOR IMPLEMENTATION OF WORM MODE ON A REMOVABLE DISK DRIVE STORAGE SYSTEM - Embodiments provide systems and methods for maintaining immutable data in an archiving system using random access memory. To ensure data is immutable, novel pointers are maintained in the hardware/firmware of the drive ports and on the removable disk drives. For example, a hardware/firmware in a modular drive bay maintains a pointer to a memory address in the removable disk drive memory that cannot write to a memory block that precedes the pointer. Data may only be stored after the pointer in the removable disk drive. As such, once data is written to the removable disk drive, the data cannot be overwritten although the removable disk drive employs random access memory. | 2012-12-06 |
20120311259 | METHODS FOR CONTROLLING REMOTE ARCHIVING SYSTEMS - Embodiments of the present disclosure provide a unique and novel archiving system that includes two or more network storage systems, each network storage system including removable hard disk drives embedded in removable disk cartridges, referred to simply as removable disk drives. The removable disk drives allow for expandability and replacement such that the archiving system need not be duplicated to add new or more storage capacity. In embodiments, the archiving system accesses, writes, reads, or performs functions on data from one network storage system to another remote network storage system. | 2012-12-06 |
20120311260 | STORAGE MANAGING SYSTEM, COMPUTER SYSTEM, AND STORAGE MANAGING METHOD - The present invention provides a configuration which can realize both two objects of prevention of performance deterioration and a reduction in storage management cost and shift a volume to a storage device which supports a hierarchical pool. To provide the configuration, a storage managing system acquires access information indicating an access load to a logical volume in a storage subsystem from a device file in a host server as access information in a page unit. The storage managing system acquires, from a storage subsystem having a hierarchical pool function, information concerning the configuration and a capacity of hierarchies of the storage subsystem. A capacity of the logical volume is calculated from the number of pages and a page unit capacity indicated by the access information. The storage managing system calculates, on the basis of information concerning the capacity of the logical volume and information concerning the configuration and the capacity of the hierarchies, a configuration candidate of a hierarchical pool for allocating a storage region for storing data included in the logical volume via the hierarchical pool to a virtual logical pool and outputs the configuration candidate of the hierarchical pool. | 2012-12-06 |
20120311261 | STORAGE SYSTEM AND STORAGE CONTROL METHOD - A storage system is provided with a memory region, a cache memory region, and a processor. The memory region stores the time relation information that indicates a time relationship of a data element that has been stored into the cache memory region and that is to be written to the logical region and a snapshot acquisition point of time to the primary volume. The processor judges whether or not the data element that has been stored into the cache memory region is a snapshot configuration element based on the time relation information for the data element that is to be written to a logical region of a write destination that conforms to the write request that specifies the primary volume and that has been stored into the cache memory region. In the case in which the result of the judgment is positive, the processor saves the data element to the secondary volume for holding a snapshot image in which the snapshot configuration element is a configuration element, and a data element of a write target is then stored into the cache memory region. | 2012-12-06 |
20120311262 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. | 2012-12-06 |
20120311263 | SECTOR-BASED WRITE FILTERING WITH SELECTIVE FILE AND REGISTRY EXCLUSIONS - A method includes mounting a persistent volume of a data storage device of an electronic device. The persistent volume is based on a protected volume stored at the data storage device. The method also includes accessing the persistent volume to enable servicing access to the data storage device of the electronic device. | 2012-12-06 |