50th week of 2009 patent applcation highlights part 17 |
Patent application number | Title | Published |
20090302412 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 2009-12-10 |
20090302413 | SEMICONDUCTOR DEVICE AND STI FORMING METHOD THEREFOR - A semiconductor device includes: a semiconductor substrate having a low voltage (LV) region and a high voltage (HV) region; a pad oxide film pattern and a pad nitride film pattern which are formed over the semiconductor substrate. Further, the semiconductor device includes a shallow trench isolation (STI) formed in the LV region and a STI in the HV region, with a step generated therebetween by ions with which the HV region on the semiconductor substrate is doped when an etching process is carried out using the pad oxide film pattern and pad nitride film pattern as a mask. | 2009-12-10 |
20090302414 | TRENCH ISOLATION FOR REDUCED CROSS TALK - A starting substrate in the form of a semiconductor wafer ( | 2009-12-10 |
20090302415 | Micro-Electromechanical System Devices - Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer. | 2009-12-10 |
20090302416 | Programmable Electrical Fuse - The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device. | 2009-12-10 |
20090302417 | STRUCTURE AND METHOD TO FORM DUAL SILICIDE E-FUSE - An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link. | 2009-12-10 |
20090302418 | FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE - Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse. | 2009-12-10 |
20090302419 | METHOD OF MODIFYING SURFACE AREA AND ELECTRONIC DEVICE - In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench. | 2009-12-10 |
20090302420 | Semiconductor device - A multilayer wiring layer | 2009-12-10 |
20090302421 | Method and apparatus for creating a deep trench capacitor to improve device performance - A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide. | 2009-12-10 |
20090302422 | Capacitor-cell, integrated circuit, and designing and manufacturing methods - A capacitor-cell is in an integrated circuit that is configured by disposing a plurality of cells on a site that is on a chip and that is provided between a power line and a grounding line in a direction of the power line and grounding line. The capacitor cell is disposed in a remaining region on the site, after the plurality of cells are disposed on the site. The capacitor-cell includes a gate poly for accumulating capacitance extending up to at least one of positions of the power line and the grounding line in a planar quadrangular cell-frame that is set for disposing the plurality of cells on the site. | 2009-12-10 |
20090302423 | ESD protection circuit and semiconductor device - An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer. | 2009-12-10 |
20090302424 | METHOD OF FORMING A BI-DIRECTIONAL DIODE AND STRUCTURE THEREFOR - In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic. | 2009-12-10 |
20090302425 | CARBON RIBBON TO BE COVERED WITH A THIN LAYER MADE OF SEMICONDUCTOR MATERIAL AND METHOD FOR DEPOSITING A LAYER OF THIS TYPE - The present invention relates to a carbon ribbon for covering in a thin layer of semiconductor material, and to a method of deposited such a layer on a substrate constituted by a carbon ribbon. At least one of the two faces of the carbon ribbon is for covering in a layer of semiconductor material by causing the ribbon to pass substantially vertically upwards through a bath of molten semiconductor material. According to the invention, the two edges of at least one of the two faces of the carbon ribbon project so as to form respective rims. | 2009-12-10 |
20090302426 | Method for the Selective Deposition of Germanium Nanofilm on a Silicon Substrate and Semiconductor Devices Made Therefrom - A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like. | 2009-12-10 |
20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 2009-12-10 |
20090302428 | LASER BEAM MACHINING METHOD AND SEMICONDUCTOR CHIP - An object to be processed | 2009-12-10 |
20090302429 | Electrically Conducting Connection with Insulating Connection Medium - A device comprising a first component ( | 2009-12-10 |
20090302430 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r | 2009-12-10 |
20090302431 | METHOD OF ACCESSING SEMICONDUCTOR CIRCUITS FROM THE BACKSIDE USING ION-BEAM AND GAS-ETCH - The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket. | 2009-12-10 |
20090302432 | SILICON EPITAXIAL WAFER AND THE PRODUCTION METHOD THEREOF - A silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon wafer having a diameter of at least 300 mm produced by slicing a silicon single crystal ingot doped with boron and germanium grown by the Czochralski method, wherein boron is doped to be at a concentration of 8.5×10 | 2009-12-10 |
20090302433 | METHOD FOR MODIFYING HIGH-K DIELECTRIC THIN FILM AND SEMICONDUCTOR DEVICE - There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties. | 2009-12-10 |
20090302434 | Preparation of Lanthanide-Containing Precursors and Deposition of Lanthanide-Containing Films - Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand. | 2009-12-10 |
20090302435 | Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die. | 2009-12-10 |
20090302436 | Semiconductor Device and Method of Forming Shielding Layer Grounded Through Metal Pillars Formed in Peripheral Region of the Semiconductor - A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate. | 2009-12-10 |
20090302437 | Semiconductor Device and Method of Connecting a Shielding Layer to Ground Through Conductive Vias - A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV. The substrate is singulated to separate the semiconductor die. | 2009-12-10 |
20090302438 | IC HAVING VOLTAGE REGULATED INTEGRATED FARADAY SHIELD - An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit. | 2009-12-10 |
20090302439 | Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference - A semiconductor device is made by forming an integrated passive device (IPD) structure on a substrate, mounting first and second electrical devices to a first surface of the IPD structure, depositing encapsulant over the first and second electrical devices and IPD structure, forming a shielding layer over the encapsulant, and electrically connecting the shielding layer to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant. | 2009-12-10 |
20090302440 | NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP - An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation. | 2009-12-10 |
20090302441 | COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE - A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting. | 2009-12-10 |
20090302442 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated. | 2009-12-10 |
20090302443 | LEADFRAME-BASED SEMICONDUCTOR PACKAGE HAVING ARCHED BEND IN A SUPPORTING BAR AND LEADFRAME FOR THE PACKAGE - A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented. | 2009-12-10 |
20090302444 | RESIN SEALED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A resin sealed semiconductor device includes a first semiconductor switching device having a first emitter terminal and a first collector terminal bonded to its top and bottom surfaces respectively, a second semiconductor switching device having a second emitter terminal and a second collector terminal bonded to its top and bottom surfaces respectively, a first heat sink directly or indirectly bonded to the first collector terminal, a second heat sink directly or indirectly bonded to the second collector terminal, and a molding resin integrally covering the first and second semiconductor switching devices. The first and second heat sinks are exposed from the molding resin. The first emitter terminal faces and is spaced apart from the second emitter terminal. | 2009-12-10 |
20090302445 | Method and Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die. Encapsulant is flowed around a portion of the semiconductor die. The encapsulant is etched and a conductive material is deposited into the etched portion of the encapsulant to form a thermally conductive structure. In one embodiment, a trench is etched into the encapsulant and a thermally conductive material is deposited into the trench to form a thermal channel. In alternative embodiments, thermally conductive through hole vias (THVs) are formed in the encapsulant. A thermally conductive pad may be formed over the semiconductor die to facilitate removal of heat energy from the hot spots of the semiconductor die. A thermally conductive trace is formed to interconnect the thermal channel and the thermally conductive pad. A heat sink may be deposited over the semiconductor package. The packages are singulated by cutting through the encapsulant or the thermal channel. | 2009-12-10 |
20090302446 | SEMICONDUCTOR PACKAGE FABRICATED BY CUTTING AND MOLDING IN SMALL WINDOWS - A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulant on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units. | 2009-12-10 |
20090302447 | SEMICONDUCTOR ARRANGEMENT HAVING SPECIALLY FASHIONED BOND WIRES AND METHOD FOR FABRICATING SUCH AN ARRANGEMENT - A semiconductor arrangement includes first and second integrated circuits (dies), an electrically conductive intermediate element, and one or more bond conductors. The first and the second integrated circuits are arranged in a package. The first integrated circuit has a first contact pad. The second integrated circuit has a second contact pad. The intermediate element is disposed on the second contact pad. The conductors electrically connect the first and the second integrated circuits. At least one of the bond conductors has a first end electrically connected to the first contact pad, and a second wedge shaped end electrically connected to the intermediate element. The bond conductor is made of a first material and the intermediate element is made of a second material which is softer than the first material. | 2009-12-10 |
20090302448 | Chip Stacked Structure and the Forming Method - A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patterned UBM layer and electrically connect to the metal layer. | 2009-12-10 |
20090302449 | PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME - An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant. | 2009-12-10 |
20090302450 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided in which the heat dissipation characteristic of a flip-chip mounted semiconductor chip is improved. A semiconductor device is provided with a substrate, a semiconductor flip-chip mounted on the substrate, a sealing resin layer for sealing around the semiconductor flip-chip. A sealing resin layer for sealing the semiconductor chip is formed around the semiconductor chip. In this semiconductor device, the back surface of the semiconductor chip is exposed and is convex with respect to the upper surface of the sealing resin layer. | 2009-12-10 |
20090302451 | Semiconductor device having function circuits selectively connected to bonding wire - A semiconductor device includes a semiconductor chip, a wiring substrate, and wires. The semiconductor chip includes a first circuit, a second circuit having a function differing from that of the first circuit, a plurality of first pads disposed in a row along one side of the semiconductor chip and connected to the first circuit, and a plurality of second pads disposed between both of the first and second circuits and the first pads, and connected to the second circuit. The wiring substrate includes a plurality of terminals and the plurality of wires is connected between a plurality of terminals provided outside of the semiconductor chip, and ones of the first pads and the second pads. The wires are free from the other of the first pads and the second pads, and the plurality of the wires being not intersected to each other. | 2009-12-10 |
20090302452 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM - A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed. | 2009-12-10 |
20090302453 | CONTACT PADS FOR SILICON CHIP PACKAGES - A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads. | 2009-12-10 |
20090302454 | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer - The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length. | 2009-12-10 |
20090302455 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to increase resistance against an electrostatic breakdown and to increase resistance to an external stress. Another object is to reduce cost by simplifying the manufacturing process. In a step in which an element formation layer is provided between a first organic resin layer provided with a first conductive film on its surface and a second organic resin layer provided with a second conductive film on its surface to electrically connect the first conductive film and the second conductive film with a contact conductor formed in each of the organic resin layers, the contact conductor provided in each of the first organic resin layer and the second organic resin layer is manufactured by making paste penetrate before an organic resin is cured and then curing the organic resin layer. | 2009-12-10 |
20090302456 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a simple method for manufacturing a semiconductor device in which deterioration in characteristics due to electrostatic discharge is reduced, a plurality of element layers each having a semiconductor integrated circuit and an antenna are sealed between a first insulator and a second insulator; a layered structure having a first conductive layer formed on a surface of the first insulator, the first insulator, the element layers, the second insulator, and a second conductive layer formed on a surface of the second insulator is formed; and the first insulator and the second insulator are melted, whereby the layered structure is divided so as to include at least one of the semiconductor integrated circuits and one of the antennas. | 2009-12-10 |
20090302457 | WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resin layer. The through wiring is formed using a conductive material, the conductive material is exposed on both surfaces of the insulating resin layer, the sheet-like fibrous body is positioned in the conductive material, and the sheet-like fibrous body is impregnated with the conductive material. A manufacturing method of the wiring substrate is also provided. | 2009-12-10 |
20090302458 | Heat Sink For Power Module - A heat sink ( | 2009-12-10 |
20090302459 | Heat Sink with Thermally Compliant Beams - A heat dissipating structure includes: a heat spreader; and a plurality of compliant beams attached to the heat spreader. The beams are formed of a high-conductive material such that a maximum stress of each beam is less than a fatigue stress of the high-conductive material; said beams are placed at an angle relative to a chip surface such that the beams are able to exert bending compliance in response to x, y, and z forces exerted upon them. The structure also includes a thermal material interface for bonding said structure to the chip surface. Both the heat spreader and the compliant beams can be machined from a copper block. An alternative heat dissipating structure includes compliant beams soldered to the chip surface. | 2009-12-10 |
20090302460 | SELF-ASSEMBLED MONOLAYER RELEASE FILMS - A release film for soft composite materials is provided. The release film contains a film with a closely packed self-assembled monolayer. A method of applying soft composite materials to a substrate without loss of the soft composite material to the release film is also provided. The method is useful in applications such as applying thermal pastes to semiconductor packaging. | 2009-12-10 |
20090302461 | SYSTEMS, DEVICES, AND METHODS FOR SEMICONDUCTOR DEVICE TEMPERATURE MANAGEMENT - Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein. | 2009-12-10 |
20090302462 | Prepreg, Method for Manufacturing Prepreg, Substrate, and Semiconductor Device - A prepreg which can meet a demand for thickness reduction is provided. The prepreg has first and second resin layers having different applications, functions, capabilities, or properties, and allows an amount of a resin composition in each of the first and second resin layers to be set appropriately depending on a circuit wiring portion to be embedded into the second resin layer. Further, a method for manufacturing the above prepreg, and a substrate and a semiconductor device having the prepreg are also provided. The prepreg according to the present invention includes a core layer including a sheet-shaped base member and having one surface and the other surface which is opposite to the one surface, the first resin layer provided on the one surface of the core layer and formed of a first resin composition, and the second resin layer provided on the other surface of the core layer and formed of a second resin composition, wherein at least one of a requirement that a thickness of the first resin layer is different from that of the second resin layer and a requirement that a constitution of the first resin composition is different from that of the second resin composition is satisfied. | 2009-12-10 |
20090302463 | SEMICONDUCTOR DEVICE HAVING SUBSTRATE WITH DIFFERENTIALLY PLATED COPPER AND SELECTIVE SOLDER - A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip | 2009-12-10 |
20090302464 | SEMICONDUCTOR DEVICE - A semiconductor device allowing for chip size reduction and thereby cost reduction without being restricted by a layout of bumps comprises a film substrate, an interposer substrate ( | 2009-12-10 |
20090302465 | DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF - A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer. | 2009-12-10 |
20090302466 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first metal post that has a first face, a second metal post that has a second face, a first plated layer that is provided on the first face, the first plated layer being discontiguous with an outer edge of the first face, a second plated layer that is provided on the second face, the second plated layer being discontiguous with an outer edge of the second face, an integrated circuit element that is fixed on the first face; a conductor that electrically connects the integrated circuit element with the second metal post, and a resin that seals the integrated circuit element and the conductor. | 2009-12-10 |
20090302467 | ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, CIRCUIT BOARD MOUNTED WITH THE SAME, AND ELECTRONIC APPLIANCE COMPRISING THE CIRCUIT BOARD - An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device. | 2009-12-10 |
20090302468 | Printed circuit board comprising semiconductor chip and method of manufacturing the same - Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip. | 2009-12-10 |
20090302469 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip | 2009-12-10 |
20090302470 | Electrode for semiconductor chip and semiconductor chip with the electrode - In an n-type semiconductor layer that contains gallium (Ga), contact resistance is to be suppressed at a low level. An n-side electrode is provided on a surface of the n-type semiconductor layer containing Ga. The electrode includes a metal layer having a Ga content of equal to or more than 1 at % and equal to or less than 25 at %. The metal layer is disposed in contact with the n-type semiconductor layer. | 2009-12-10 |
20090302471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a semiconductor device including a semiconductor substrate on which a plurality of semiconductor chips having electrode pads is formed, an internal connection terminal provided on each of the electrode pads, an insulating layer provided to cover the plurality of semiconductor chips and the internal connection terminals, and a wiring pattern connected to the internal connection terminals across the insulating layer. This semiconductor device is characterized in that the insulating layer is configured to contain an alpha ray blocking material including polyimide and/or a polyimide-based compound. | 2009-12-10 |
20090302472 | Non-volatile memory devices including shared bit lines and methods of fabricating the same - Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts. | 2009-12-10 |
20090302473 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first interlayer insulating film formed over a semiconductor substrate; a plurality of interconnects formed in the first interlayer insulating film; and a via and a dummy via, which are formed in the first interlayer insulating film so as to connect to at least one of the plurality of interconnects. A void is selectively formed between adjacent ones of the interconnects in the first interlayer insulating film. The dummy via is formed under an interconnect which is in contact with the void, so as to connect to the interconnect. The via and the dummy via are surrounded by the first interlayer insulating film with no void interposed therebetween. | 2009-12-10 |
20090302474 | Atomic laminates for diffucion barrier applications - The present invention relates to a very thin multilayer diffusion barrier for a semiconductor device and fabrication method thereof. The multilayer diffusion barrier according to the present invention is fabricated by forming a very thin, multilayer diffusion barrier composed of even thinner sub-layers, where the sub-layers are only a few atoms thick. The present invention provides a diffusion barrier layer for a semiconductor device which is in a substantially amorphous state and thermodynamically stable, even at high temperatures. | 2009-12-10 |
20090302475 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between adjacent ones of the plurality of first interconnects in the first interlayer insulating film, and a cap insulating film is formed in a region located over the void and between the interconnects. Respective widths of a lower end and an upper end of the void are substantially the same as a gap between the interconnects located adjacent to the void, and the lower end of the void is located lower than lower ends of the first interconnects located adjacent to the void. | 2009-12-10 |
20090302476 | Structures and Methods to Enhance CU Interconnect Electromigration (EM) Performance - The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect. | 2009-12-10 |
20090302477 | Integrated circuit with embedded contacts - In some embodiments, disclosed is an interconnect structure with embedded plugs. | 2009-12-10 |
20090302478 | Semiconductor device and method of forming recessed conductive vias in saw streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 2009-12-10 |
20090302479 | SEMICONDUCTOR STRUCTURES HAVING VIAS - A semiconductor structure comprises a substrate having a front surface and a back surface and a via extending from the first surface, the via comprising. The via comprises: a first side; a second side parallel to the first side; a first end extending between the first side and the second side; a second end opposite to the first end and extending between the first side and the second side. The first and second ends form oblique angles with the first and second sides. A method of fabricating the vias is also described. | 2009-12-10 |
20090302480 | Through Substrate Via Semiconductor Components - A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening. | 2009-12-10 |
20090302481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has a first conductive layer over a first insulating layer; a second insulating layer over the first conductive layer, which includes an opening extending to the first conductive layer; and a signal wiring layer for electrically connecting an integrated circuit portion to an antenna and a second conductive layer adjacent to the signal wiring layer, which are formed over the second insulating layer. The second conductive layer is in contact with the first conductive layer through the opening, and the first conductive layer overlaps the signal wiring layer with the second insulating layer interposed therebetween. | 2009-12-10 |
20090302482 | Structure and Method for Forming Hybrid Substrate - A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate. | 2009-12-10 |
20090302483 | STACKED DIE PACKAGE - The invention provides a stacked die package. The package includes a lead frame having a plurality of the leads and a stack of dice disposed thereon, in which the upper die may be electrically connected to the leads via at least one transit area on the lower die to transfer a power signal or a ground signal. | 2009-12-10 |
20090302484 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die. | 2009-12-10 |
20090302485 | LAMINATE SUBSTRATE AND SEMICONDUCTOR PACKAGE UTILIZING THE SUBSTRATE - A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching. | 2009-12-10 |
20090302486 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark | 2009-12-10 |
20090302487 | WASTEWATER TREATMENT SYSTEM AND METHOD OF USING SAME - A wastewater treatment system, comprising a tank and an elongate draft tube. The tank comprises a bottom and at least one partition wall extending short of a tank curved turning wall to form at least a pair of channels for movement of a volume of a liquid. The elongate draft tube is at least partially submerged beneath the liquid and is rotated about its longitudinal axis for orbitally moving the liquid through the at least a pair of channels of the tank in a fixed direction. A process for treating wastewater is also provided. | 2009-12-10 |
20090302488 | METHOD AND APPARATUS FOR THE DRY RELEASE OF A COMPLIANT OPHTHALMIC ARTICLE FROM MOLD SURFACE - An apparatus for releasing a molded lens from a deformable mold includes a shear ring for temporarily retaining an annular portion of the deformable mold outside a periphery of the lens and a plunger for deforming an annular section of the deformable mold within the periphery of the lens. The apparatus can be employed to release a non-hydrated hydrogel lens from a deformable mold section. | 2009-12-10 |
20090302489 | METHOD AND DEVICE FOR PRODUCING POLYESTER GRANULES AND/OR SHAPED PARTS WITH A LOW ACETALDEHYDE CONTENT - In the case of the method for the production of polyester granulate or moulded articles from a melt which is discharged from a polycondensation ( | 2009-12-10 |
20090302490 | INJECTION MOLDING SYSTEM AND INJECTION MOLDING METHOD - An injection molding system includes an injection mold set to form injection molded products through repeated injection molding, and a printing device to press a film coated with colors onto an intermediate injection molded product to print the colors onto the intermediate injection molded product. The intermediate injection molded product is printed with the colors coated onto the film to shorten a printing time and semipermanently conserve a printed figure. Further, even if the film is deviated slightly from a predetermined correct position, printing a desired figure correctly on the intermediate injection molded product is possible. | 2009-12-10 |
20090302491 | EXTRUSION DIE WITH EXTRUSION PORT HAVING A SHAPED EXTRUSION OUTLET - A cutter assembly for an extruder includes an elongated extrusion member having an open feed end. The open feed end is attachable in fluid communication with the extruder for supplying a mash thereto. An extrusion die is supported on the elongated extrusion member. The extrusion die includes at least one extrusion outlet formed therein. A cutter member cuts extrudate to a desired length as the extrudate exits the die. The at least one extrusion outlet is shaped to have at least six straight sides, the shape of the at least one extrusion outlet ensuring that the mash exits the extrusion die in a straight orientation in order to form a straight food product. | 2009-12-10 |
20090302492 | In-mold reprint manufacturing system for thin film texture and a method thereof - An in-mold reprint manufacturing system for thin film texture includes a texture reprint device having a first mold and a second mold and an injection molding machine having a foil feeder, a foil feeder rewinder, a cavity moving plate, and a core fastening plate. The first mold and the second mold of the texture reprint device are pressed onto a thin film to generate a texture on the thin film. The foil feeder and the foil feeder rewinder continuously make the thin film with the texture pass through the core fastening plate. The cavity moving plate has a repeated movement to the core fastening plate to produce a product with the texture by the injection molding way. An in-mold reprint manufacturing method for thin film texture is also disclosed. | 2009-12-10 |
20090302493 | PROCESS FOR PRODUCING A SOLID DISPERSION OF AN ACTIVE INGREDIENT - A process for producing a solid dispersion of an active ingredient which comprises feeding the active ingredient and a matrix-forming agent to an extruder and forming a uniform extrudate, wherein the extruder comprises at least two rotating shafts ( | 2009-12-10 |
20090302494 | METHOD MANUFACTURE OF WEATHERSTRIPS USING ULTRA HIGH MOLECULAR WEIGHT POLYETHYLENE ONTO SCF EXTRUSION SYSTEM - There is provided a process of preparing an automotive weatherstrip by co-extrusion of UHMWPE and TPV materials with an SCF. The automotive weatherstrip according to the present invention can be easily recycled, shows excellent properties with respect to lightweight and fire-resistance, and also contributes to improve the product quality by preventing exterior damage. | 2009-12-10 |
20090302495 | SOLUTION CASTING METHOD AND SOLUTION CASTING APPARATUS FOR FILM MANUFACTURE | 2009-12-10 |
20090302496 | CNC Instructions For Solidification Fixturing Of Parts - A customer transmits their 3D CAD file for a part to be total profile machined. Computer analysis of the transmitted CAD file produces CNC machining instructions, which are transmitted back to an address defined by the customer. The customer can then use the transmitted CNC machining instructions to total profile machine their own part using their own CNC mill at the location where the part is likely needed. The transmitted instructions include not only the tool paths for CNC machining of the total profile of the part, but also for additional features formed into the encircling portion of a material block from which the part is to be total profile machined. For instance, the CNC machining instructions transmitted back to the customer can define a registration recess and/or channels or undercuts for fluid support material on an A-side of a material block. After the A-side of the block is machined, the customer adds and solidifies fluid support material into the machined recess. The CNC mill is then used to machine a support surface into a portion of the solidified support material surface. A registration fixture is applied into contact with the support surface CNC machining on the B-side of the material block is then performed while the part is supported by the solidified support material, substantially separating the part from the encircling block of material. The support material is then removed, such as by dissolving, freeing the part from the encircling block of material. | 2009-12-10 |
20090302497 | FLOW RESTRICTOR FOR INJECTION MOULDING MACHINE FOR THE INJECTION MOULDING OF RUBBER MATERIALS OR OF ELASTOMER MATERIALS - The present invention relates to a throttle for an injection molding machine for injection molding rubber or elastomeric material and comprises a throttle block, an inlet channel and an outlet channel provided therein as well as a throttle means. The inlet channel can be provided at an angle relative to the outlet channel. The throttle means comprises a throttle piston, which serves both to reduce the material flow and inject the rubber or elastomeric materials into the injection mold. A system and method for tempering rubber or elastomeric material in injection molding can be realised with the throttle of the invention, wherein in particular shorter cycle times can be achieved. | 2009-12-10 |
20090302498 | SENSING DEVICE - A sensing device including a magnetoelastic film and a polymeric support for the magnetoelastic film, the magnetoelastic film being mounted in the support. The polymeric support includes a mixture of polymeric material and magnetically-susceptible material, the magnetically-susceptible material being in particulate form. A method for the production of the sensing device, and an absorbent article including the sensing device. | 2009-12-10 |
20090302499 | METHOD FOR MAKING A RADIOPHARMACEUTICAL PIG - A pharmaceutical pig is used to transport a syringe containing a liquid radiopharmaceutical from a radiopharmacy to a medical facility for administration to a patient. The pharmaceutical pig includes an elongate polymer cap that is removably attached to an elongate polymer base. The elongate polymer cap includes a cap shell that completely encloses a cap shielding element and the elongate polymer base includes a base shell that completely encloses a base shielding element. Preferably the polymer utilized for the cap shell and the base shell is polycarbonate resin, e.g., LEXAN®. An inner liner is not utilized and the cap shielding element and the base shielding element, which are preferably, but not necessarily, made of lead, are completely sealed and unexposed. | 2009-12-10 |
20090302500 | Forming Apparatus - The present invention relates to method of forming a material, including the steps of, presenting a formable material to a space from where the material can be carried by and/or between opposing surfaces of the space, as the opposing surfaces advance in an advancing direction. Also pressurising, as the opposing surfaces advance, the material between the opposing surfaces in a reduced space between the opposing surfaces defining at least in part a pressure forming zone. The reduced space between the opposing surfaces being maintained at least substantially constant until such time as the form of at least one of the opposing surfaces is profiled into the material and is retainable thereon. Thereafter releasing the now profiled material from between the opposing surfaces, as the space increases between the opposing surfaces as the surfaces advance. The relative movement between adjacent tools of at least one set of forming tools over the zone before the pressure forming zone is only towards the forming tools of the other opposing surface. | 2009-12-10 |
20090302501 | Formable Sealant Barrier - In one embodiment of the present invention, an assembly for HPHT processing comprises a can with an opening. A powder mixture is disposed within the opening. A substrate is disposed within the opening adjacent the powder mixture. Paint is coated on a surface within the opening and opposite the powder mixture with respect to the substrate. A meltable sealant is disposed within the opening and opposite the substrate with respect to the surface and a cap is covering the opening. | 2009-12-10 |
20090302502 | PROCESS OF PRODUCING LIQUID DISCHARGE HEAD - Provided is a process of producing a liquid discharge head having a substrate, a passage-forming member, and a patterned layer. The process includes providing a resin layer on a substrate; providing a resist pattern on the resin layer for patterning the resin layer; forming a patterned layer by patterning the resin layer using the resist pattern as a mask; providing a layer for forming a passage pattern having a shape of passage on the resist pattern lying on the patterned layer; forming a passage pattern by patterning the layer for forming a passage pattern; removing the resist pattern; providing a passage-forming member so as to cover the passage pattern and the patterned layer; and removing the passage pattern to give the passage. | 2009-12-10 |
20090302503 | Coating Method - The subject of the invention is a coating method based on laser ablation where the distance between the substrate and the target being ablated is exceptionally small. The short distance allows coating the substrate even in industrial scale preferably also under a low-vacuum or even non-vacuum atmosphere. The invention is preferable in conjunction with the optimal coating of all large-size objects or objects with varying shapes. | 2009-12-10 |
20090302504 | MACHINE UTILIZED FOR PRODUCING AND MANUFACTURING A RESILIENT FILM SOFT AT TOUCH, SUITABLE TO DRAINING USE - A machine utilized for producing and manufacturing a film, soft at touch, resilient and suitable at draining use. A film produced by such a machine, presents, at least, on one surface an essentially continuous pattern of micro-funnels three-dimensional (3D) directed in an essentially perpendicular way to the surface from which the micro-openings have origin. It presents also on the opposite surface a continuous pattern, composed by 3D macro-funnels directed in an essentially perpendicular way to the surface from which the macro-funnels have origin. The “micro-funnels” term, intend to describe a multitude of funnels non distinguishable by the human eye at a distance equal or higher than 450 mm. while the “macro funnels” term, intend to describe funnels clearly visible by the human eye at a distance higher than 450 mm. | 2009-12-10 |
20090302505 | INJECTABLE CORING COMPOSITION FOR CLOSED MOLDING PROCESSES - An injectable coring composition. The injectable coring composition comprises: about 70 to about 90 wt % polyester resin, about 0.1 to about 5 wt % monomer, about 0.1 to about 5 wt % solvent, about 1 to about 25 wt % spheres or microspheres, the spheres or microspheres made of glass, plastic, ceramic, or combinations thereof, and 0 to about 25 wt % filler. A method of making a core is also disclosed. | 2009-12-10 |
20090302506 | Ultra Water Repellent Film Manufacturing Equipment and Method - Provided are ultra water repellent film manufacturing equipment capable of continuous manufacturing of an ultra water repellent film through casting and separating a hydrophilic or hydrophobic polymer on an outer surface of a rotating belt, and an ultra water repellent film manufacturing method using the equipment. The equipment includes the rotating belt wound around rollers to continuously rotate, a polymer supplying member ( | 2009-12-10 |
20090302507 | MOLD, PROCESS FOR ITS PRODUCTION, AND PROCESS FOR PRODUCING BASE MATERIAL HAVING TRANSFERRED MICROPATTERN - To provide a mold having optical transparency, release properties, mechanical strength, dimension stability and a highly precise micropattern, and having less deformation of the micropattern; and a process for producing a base material with a transferred micropattern having less deformation of the transferred micropattern, capable of transferring highly precise micropattern of the mold. | 2009-12-10 |
20090302508 | METHOD OF CONSTRUCTION - A method of producing a one-piece support structure which incorporates a supporting platform and at least one integral support leg using a blow moulding technique, including the steps of: a) defining the optimum thickness of material required for the support leg(s) for strength purposes, b) defining the optimum height for the support legs, c) determining the volume of the parison, to be introduced across the leg part of the mould, d) designing the mould leg interior to ensure that for the given parison volume the thickness of material subsequently blow moulded around the surface area of the support leg is sufficient to provide the required strength, and e) blow moulding material into the mould as designed by steps a) to d). | 2009-12-10 |
20090302509 | Method Of Forming A Composite Article In A Mold - A method of forming a composite article having a decal occurs in a mold. The mold includes a surface that defines a mold cavity. A decal is introduced to the surface of the mold. A polyurethane elastomer composition is applied into the mold cavity to form an elastomeric layer over the decal. The composite article including the elastomeric layer and the decal may then be demolded from the mold. Alternatively, a paint composition is applied into the mold cavity to form a paint layer over the decal. The polyurethane elastomer composition is applied into the mold cavity to form an elastomeric backing layer over the paint layer. The composite article including the paint layer, the decal, and the elastomeric backing layer may then be demolded from the mold. The composite article may be a seat for an all-terrain vehicle. | 2009-12-10 |
20090302510 | METHOD AND EQUIPMENT FOR DECREASING THE CYCLE TIMES OF MACHINES FOR PRODUCING ARTICLES IN THERMOPLASTIC MATERIAL - The method comprises the following sequence of stages of operation: feeding the blowing air into the parison enclosed in the mould ( | 2009-12-10 |
20090302511 | Method for Shaping Sheet Thermoplastic and the Like - Processes and apparati for shaping sheet glass or thermoplastic materials use force from a layer of a flowing fluid, such as air, between the sheet and a mandrel at close to the softening temperature of the thermoplastic. The shape is preserved by colling. The shape of the air bearing mandrel and the pressure distribution of the fluid contribute to the final shape. A process can be conducted on one or two surfaces such that the force from the air layer is on one or two surfaces of the sheet. The gap size between the sheet and mandrel determines the pressure profile in the gap, which also determines the final sheet shape. In general, smaller gaps lead to larger viscous forces. The pressure profile depends on the shape of the mandrel, the size of the fluid gap and the sheet and the fluid supply pressure. | 2009-12-10 |