50th week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150357421 | WAFER STRENGTH BY CONTROL OF UNIFORMITY OF EDGE BULK MICRO DEFECTS - Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile. | 2015-12-10 |
20150357422 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness. | 2015-12-10 |
20150357423 | FLEXIBLE ACTIVE MATRIX CIRCUITS FOR INTERFACING WITH BIOLOGICAL TISSUE - High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors. | 2015-12-10 |
20150357424 | SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING THE SAME - A silicon substrate is restrained from being warped. A substrate is formed by use of a silicon substrate. The substrate has a first surface and a second surface opposite to each other. A metal film is formed over the first surface. An interconnection layer is formed over the second surface. The metal film has a face centered cubic lattice structure. When the metal film is measured by XRD (X-ray diffraction), the [111] orientation intensity A(111), the [220] orientation intensity A(220) and the [311] orientation intensity A(311) of the metal film satisfy the following: A(111)/{A(220)+A(311)}≧10. | 2015-12-10 |
20150357425 | BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions. | 2015-12-10 |
20150357426 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively. | 2015-12-10 |
20150357427 | Integrated Circuit Device with Metal Gates Including Diffusion Barrier Layers and Fabricating Methods Thereof - An integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof are provided. The device may include a gate insulating film, a first conductivity type work function regulating film on the gate insulating film and a metal gate pattern on the first conductivity type work function regulating film. The device may include a cobalt film between the gate insulating film and the metal gate pattern to reduce diffusion from the metal gate pattern into the gate insulating film. | 2015-12-10 |
20150357428 | SURROUNDING GATE TRANSISTOR (SGT) STRUCTURE - The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film. | 2015-12-10 |
20150357429 | SEMICONDUCTOR DEVICES CONTAINING AN EPITAXIAL PEROVSKITE/DOPED STRONTIUM TITANATE STRUCTURE - Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide. | 2015-12-10 |
20150357430 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer. | 2015-12-10 |
20150357431 | MANUFACTURING METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate. | 2015-12-10 |
20150357432 | SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND DEVICES - Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region. | 2015-12-10 |
20150357433 | INTEGRATED CIRCUITS WITH VERTICAL JUNCTIONS BETWEEN nFETS AND pFETS, AND METHODS OF MANUFACTURING THE SAME - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an implant mask overlying a dummy gate, where the implant mask produces a masked dummy gate and an exposed dummy gate. Ions are implanted into the exposed dummy gate, and the implant mask is removed. The masked dummy gate is etched with an etchant selective to the masked dummy gate over the exposed dummy gate to form a trench, and the trench is filled with a conductive material. | 2015-12-10 |
20150357434 | REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions. | 2015-12-10 |
20150357435 | METHOD OF MAKING A GATE STRUCTURE - A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. | 2015-12-10 |
20150357436 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; and performing a second dry etching process to expand the recess. | 2015-12-10 |
20150357437 | MOS-Transistor with Separated Electrodes Arranged in a Trench - A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer. | 2015-12-10 |
20150357438 | METHOD FOR MANURACTURING PILLAR-SHAPED SEMICONDUCTOR DEVICE | 2015-12-10 |
20150357439 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS - A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins. | 2015-12-10 |
20150357440 | METHOD AND STRUCTURE FOR ROBUST FINFET REPLACEMENT METAL GATE INTEGRATION - A robust gate spacer that can resist a long overetch that is required to form gate spacers in fin field effect transistors (FinFETs) and a method of forming the same are provided. The gate spacer includes a first gate spacer adjacent sidewalls of at least one hard mask and a top portion of sacrificial gate material of a sacrificial gate structure and a second gate spacer located beneath the first gate spacer and adjacent remaining portions of sidewalls of the sacrificial gate material. The first gate spacers is composed of a material having a high etch resistance that is not prone to material loss during subsequent exposure to dry or wet etch chemicals employed to form the second gate spacer and to remove the hard mask. | 2015-12-10 |
20150357441 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WHILE AVOIDING NODULES ON A GATE - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins. | 2015-12-10 |
20150357442 | TILT IMPLANTATION FOR FORMING FINFETS - One embodiment of the instant disclosure provides a method for fabrication of fin devices for an integrated circuit, which comprises: forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking; performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, the fin structures being maintained at an elevated temperature during the channel implantation to prevent amorphization thereof during channel implantation; and forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation. | 2015-12-10 |
20150357443 | Semiconductor Liner of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant. | 2015-12-10 |
20150357444 | Semiconductor Device - An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided. In addition, the oxide semiconductor film used for an active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by heat treatment in which impurities such as hydrogen, moisture, a hydroxyl group, or a hydride are removed from the oxide semiconductor and oxygen which is a major constituent of the oxide semiconductor and is reduced concurrently with a step of removing impurities is supplied. | 2015-12-10 |
20150357445 | STRUCTURE AND METHOD FOR VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH LEVELED SOURCE AND DRAIN - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 2015-12-10 |
20150357446 | BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE - According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. | 2015-12-10 |
20150357447 | BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION - The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer. | 2015-12-10 |
20150357448 | BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region. | 2015-12-10 |
20150357449 | Power Semiconductor Device - A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode. | 2015-12-10 |
20150357450 | CHARGE RESERVOIR IGBT TOP STRUCTURE - An IGBT device may be formed from a substrate including a bottom semiconductor layer of a first conductivity and an upper semiconductor layer of a second conductivity type located above the bottom semiconductor layer. Trenches for trench gates are formed in the substrate. Each trench extends vertically into the upper semiconductor layer and is provided with a gate insulator on each side of the trench and is filled with polysilicon. A first conductivity type floating body region is formed between two neighboring trenches and over the substrate. A bottom of the floating body region is close in depth to but above a bottom of the polysilicon in the trench. A heavily doped second conductivity type top region is formed over the floating body region. A first conductivity type body region is formed over the top region. The floating body region has a lower doping concentration than the body region. | 2015-12-10 |
20150357451 | SEMICONDUCTOR DEVICE FOR HIGH-POWER APPLICATIONS - Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer. | 2015-12-10 |
20150357452 | Semiconductor Device with Selectively Etched Surface Passivation - A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer. | 2015-12-10 |
20150357453 | CIRCUIT STRUCTURE, TRANSISTOR AND SEMICONDUCTOR DEVICE - A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a Al | 2015-12-10 |
20150357454 | LAYER STRUCTURE FOR A GROUP-III-NITRIDE NORMALLY-OFF TRANSISTOR - A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer. | 2015-12-10 |
20150357455 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer. The device further includes a third semiconductor layer of the first conductivity type or an intrinsic type provided on the second semiconductor layer, and a fourth semiconductor layer provided on the first semiconductor layer. The device further includes a fifth semiconductor layer of the second conductivity type provided on the fourth semiconductor layer, and a control electrode provided on the second semiconductor layer through an insulating layer and electrically connected to the fifth semiconductor layer. | 2015-12-10 |
20150357456 | SEMICONDUCTOR HETEROJUNCTION DEVICE - In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them. | 2015-12-10 |
20150357457 | SCHOTTKY GATED TRANSISTOR WITH INTERFACIAL LAYER - A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (Å) and 40 Å. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO | 2015-12-10 |
20150357458 | III-Nitride Device with Improved Transconductance - A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench is also disposed in a trench and under and in close proximity to the drift region between the gate and drain electrodes of the device. The back-gate is connected to the main gate and the field plate is connected to the source electrode. The back-gate can consist of a highly conductive silicon substrate. | 2015-12-10 |
20150357459 | INTEGRATED CHANNEL DIODE - A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor. | 2015-12-10 |
20150357460 | SEMICONDUCTOR DEVICE WITH BIASED FEATURE - A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions. | 2015-12-10 |
20150357461 | INTEGRATED TERMINATION FOR MULTIPLE TRENCH FIELD PLATE - A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain drift region. The vertical MOS transistor has chamfered corners; each chamfered corner extends across at least five of the drain trenches. A RESURF termination trench surrounds the drain trenches, separated from sides and ends of the drain trenches by distances which are functions of the drain trench spacing. At the chamfered corners, the termination trench includes external corners which extend around an end of a drain trench which extends past an adjacent drain trench, and includes internal corners which extend past an end of a drain trench which is recessed from an adjacent drain trench. The termination trench is separated from the drain trenches at the chamfered corners by distances which are also functions of the drain trench spacing. | 2015-12-10 |
20150357462 | LDMOS DEVICE AND STRUCTURE FOR BULK FINFET TECHNOLOGY - A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation. | 2015-12-10 |
20150357463 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a channel-forming region of a first conductivity type; a first main electrode region of a second conductivity type disposed in a portion of an upper part of the channel-forming region; a drift region of the second conductivity type that is disposed in an upper part of the channel-forming region apart from the first main electrode region; a second main electrode region of the second conductivity type that is disposed in a part of an upper part of the drift region; and a stopper region of the second conductivity type that is disposed at an end region of the drift region apart from the first main electrode region and has a higher concentration than the drift region. The stopper region restricts extension of a depletion layer developing at the boundary of the pn junction between the channel-forming region and the drift region. | 2015-12-10 |
20150357464 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region. | 2015-12-10 |
20150357465 | THRESHOLD VOLTAGE ADJUSTMENT OF A TRANSISTOR - A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed. | 2015-12-10 |
20150357466 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region. | 2015-12-10 |
20150357467 | TUNABLE BREAKDOWN VOLTAGE RF FET DEVICES - A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions. | 2015-12-10 |
20150357468 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; and a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper is formed in only a region directly under a portion of the fin where the fin intersects the gate stack. | 2015-12-10 |
20150357469 | Source/Drain Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface. | 2015-12-10 |
20150357470 | FINFET WITH OXIDATION-INDUCED STRESS - A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided. | 2015-12-10 |
20150357471 | STRESS INDUCING CONTACT METAL IN FINFET CMOS - A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer. | 2015-12-10 |
20150357472 | QUANTUM WELL FIN-LIKE FIELD EFFECT TRANSISTOR (QWFINFET) HAVING A TWO-SECTION COMBO QW STRUCTURE - The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure. | 2015-12-10 |
20150357473 | SEMICONDUCTOR MEMORY DEVICE - To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided. | 2015-12-10 |
20150357474 | OXIDE FOR SEMICONDUCTOR LAYER OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE - With respect to this oxide for a semiconductor layer of a thin film transistor, metal elements that constitute the oxide comprise In, Ga, and Zn, the oxygen partial pressure when forming the oxide film as the semiconductor layer of the thin film transistor is 15 volume % or lower (not including 0 volume %), the defect density of the oxide satisfies 2×10 | 2015-12-10 |
20150357475 | METAL OXIDE THIN FILM TRANSISTOR - A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode. | 2015-12-10 |
20150357476 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion. | 2015-12-10 |
20150357477 | BACKSIDE SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type. | 2015-12-10 |
20150357478 | THIN FILM TRANSISTOR DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer. | 2015-12-10 |
20150357479 | SEMICONDUCTOR DEVICE - A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions. | 2015-12-10 |
20150357480 | STABLE METAL-OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING - A thin film semiconductor device has a semiconductor layer including a composite/blend/mixture of an amorphous/nanocrystalline semiconductor ionic metal oxide and an amorphous/nanocrystalline non-semiconducting covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a semiconductive channel, and agate terminal is positioned in communication with the semiconductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer. | 2015-12-10 |
20150357481 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor is disclosed. The junction field effect transistor includes a first doped region and a second doped region. The first doped region includes a source and a drain. The second doped region includes a gate. The first doped region and the second doped region have a U-shape PN junction there between. The U-shape PN junction is between the source and the drain. | 2015-12-10 |
20150357482 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a first electrode, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a second electrode. The first electrode forms a Schottky junction with the first region. The second region is provided between the first region and the first electrode. The third region is provided between the first region and the first electrode and forms an ohmic junction with the first electrode. The fourth region is provided between the first region and the third region. The fourth region has a higher impurity concentration than the first region. The fifth region is provided between the third region and the first electrode. The fifth region has a higher impurity concentration than the third region. The second electrode is provided on opposite side of the first region from the first electrode. | 2015-12-10 |
20150357483 | Light Sensing Device and Method of Arranging Light Sensing Element Thereof - A light sensing device includes a substrate, a plurality of light sensing elements and a cover. The plurality of light sensing elements are disposed on the substrate for sensing light. The cover is utilized for sheltering the plurality of light sensing elements, wherein the cover includes a hole for passing the light. A set of the plurality of light sensing elements is selected to be enabled according to a location of the hole relative to the plurality of light sensing elements. | 2015-12-10 |
20150357484 | ELECTRONIC DEVICE COMPRISING AN OPTICAL SENSOR CHIP - An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements. | 2015-12-10 |
20150357485 | PHOTODETECTOR - Provided is a photodetector including a graphene p-n homogeneous vertical-junction diode by evaluating photodetection characteristics of the manufactured graphene p-n vertical junction according to the amount of doping. The photodetector comprises a substrate and graphene having a p-n homogeneous vertical junction as a photodetection layer formed on the substrate, wherein the photodetection layer has a detectability of 10E11 (Jones) or higher within the range of 350 nm to 1100 nm, and first and second electrodes are formed on the photodetection layer. | 2015-12-10 |
20150357486 | SOLAR CELL INCLUDING MULTIPLE BUFFER LAYER FORMED BY ATOMIC LAYER DEPOSITION AND METHOD OF FABRICATING THE SAME - Provided are a solar cell and a method for fabricating the same. The solar cell includes: a substrate; a back electrode layer formed on the substrate; a light absorbing layer formed on the back electrode layer; a buffer layer including an O-free first buffer layer formed on the light absorbing layer by atomic layer deposition (ALD) and a second buffer layer formed on the first buffer layer by the atomic layer deposition (ALD); and a front electrode layer formed on the buffer layer. | 2015-12-10 |
20150357487 | HIGH-EFFICIENCY SOLAR CELL STRUCTURES AND METHODS OF MANUFACTURE - Solar cells of varying composition are disclosed, generally including a central substrate, conductive layer(s), antireflection layers(s), passivation layer(s) and/or electrode(s). Multifunctional layers provide combined functions of passivation, transparency, sufficient conductivity for vertical carrier flow, the junction, and/or varying degrees of anti-reflectivity. Improved manufacturing methods including single-side CVD deposition processes and thermal treatment for layer formation and/or conversion are also disclosed. | 2015-12-10 |
20150357488 | ELECTRO-CONDUCTIVE PASTE COMPRISING A VANADIUM CONTAINING COMPOUND IN THE PREPARATION OF ELECTRODES IN MWT SOLAR CELLS - The invention relates to an electro-conductive paste comprising a vanadium containing compound in the preparation of electrodes in solar cells, particularly in the preparation of electrodes in MWT solar cells, particularly in the preparation of the metal wrap through, or plug, electrode in such solar cells. In particular, the invention relates to a solar cell precursor, a process for preparing a solar cell, a solar cell and a module comprising solar cells. | 2015-12-10 |
20150357489 | BINARY GLASS FRITS USED IN N-TYPE SOLAR CELL PRODUCTION - In general, the invention relates to electro-conductive pastes containing binary glass frits and photovoltaic solar cells, preferably n-type photovoltaic solar cells. More specifically, the invention relates to solar cell precursors, processes for preparation of solar cells, solar cells and solar modules. | 2015-12-10 |
20150357490 | COMPOSITION FOR FORMING ELECTRODE OF SOLAR CELL, AND ELECTRODE MANUFACTURED USING SAME - A composition for solar cell electrodes and electrodes fabricated using the same. The composition includes a silver (Ag) powder; a glass frit containing about 0.1 mole % to about 50 mole % of elemental silver; and an organic vehicle, wherein the elemental silver derives from a silver halide (Ag—X). The composition introduces a glass frit including a silver halide to enhance contact efficiency between electrodes and a silicon wafer, and solar cell electrodes prepared from the composition have minimized contact resistance (Rc), specific contact resistivity, and serial resistance (Rs), thereby exhibiting excellent conversion efficiency. | 2015-12-10 |
20150357491 | PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element includes a first lower electrode in contact with a first-conductivity-type layer and a first upper electrode disposed on the first lower electrode. A part of the first-conductivity-type layer and a part of a second-conductivity-type layer are located above a region where an intrinsic layer contacts an insulating layer. | 2015-12-10 |
20150357492 | CIGS FILM PRODUCTION METHOD, AND CIGS SOLAR CELL PRODUCTION METHOD USING THE CIGS FILM PRODUCTION METHOD - A CIGS film production method capable of suppressing oxidation of a front surface of a CIGS film, and a CIGS solar cell production method using the CIGS film production method includes the steps of: forming a first region having a Ga/(In+Ga) ratio progressively reduced as the thickness of the first region increases to a predetermined first thickness position from a back surface of the CIGS film; forming a second region having a Ga/(In+Ga) ratio progressively increased as the thickness of the second region increases to a predetermined second thickness position from the first region; and forming a third region on the second region by vapor-depositing Se and In, the third region having a Ga/(In+Ga) ratio progressively reduced toward a front surface of the CIGS film. | 2015-12-10 |
20150357493 | SOLAR CELL AND PRODUCING METHOD THEREOF - In a solar cell in a sheet form, a first cured resin layer, a substrate containing a resin, a photoelectric conversion layer, and a second cured resin layer are stacked in this order. The linear expansion coefficient of the first cured resin layer is not less than that of the second cured resin layer, and the linear expansion coefficient of the second cured resin layer is larger than that of the substrate. When the cure degree of a first surface of the first cured resin layer facing the substrate is C | 2015-12-10 |
20150357494 | GAS PERMEATION BARRIER MATERIAL AND ELECTRONIC DEVICES CONSTRUCTED THEREWITH - A gas permeation barrier structure comprises a rigid or flexible substrate, an oxide or nitride layer deposited thereon by atomic layer deposition (ALD), and a polymeric clear coat. The presence of the polymeric clear coat permits the barrier structure to maintain resistance to permeation of gases including oxygen and water vapor longer than would a structure in which the ALD layer is directly exposed to atmosphere. | 2015-12-10 |
20150357495 | TILED FRAMELESS PV-MODULE - A photovoltaic module employing an array of photovoltaic cells disposed between two optically transparent substrates such as to define a closed-loop peripheral area of the module that does not contain a photovoltaic cell. The module is sealed with a peripheral seal along the perimeter; and is devoid of a structural element affixed to an optically transparent substrate and adapted to mount the module to a supporting structure. The two substrates may be bonded together with adhesive material and, optionally, the peripheral seal can include the adhesive material. The module optionally includes diffraction grating element(s) adjoining respectively corresponding PV-cell(s). | 2015-12-10 |
20150357496 | CORE-SHELL PARTICLE, UPCONVERSION LAYER, AND PHOTOELECTRIC CONVERSION DEVICE - A core-shell particle including a semiconductor core and a first semiconductor shell on a surface of the semiconductor core, wherein the semiconductor core contains a semiconductor and an impurity that forms an intermediate band in a band gap of the semiconductor. An upconversion layer and a photoelectric conversion device each containing the core-shell particle. | 2015-12-10 |
20150357497 | ELECTRICALLY CONDUCTIVE ADHESIVES COMPRISING BLEND ELASTOMERS - Disclosed herein is an electrically conductive adhesive composition and its use in solar cell modules, wherein the electrically conductive adhesive comprises a polymer matrix and dispersed in the polymer matrix about 40-90 wt % of conductive particles, with the wt % of all components comprised in the compositions totaling to 100 wt %, and wherein the polymer matrix comprises or is formed of a blend of at least one ethylene/alkyl (meth)acrylate copolymer elastomer and at least one ethylene vinyl acetate copolymer at a weight ratio ranging from about 10:90 to about 70:30. | 2015-12-10 |
20150357498 | VOLTAGE SOURCE GENERATOR AND VOLTAGE SOURCE MODULE - A voltage source generator includes a light-transmissive component and a plurality of vertical multi junction (VMJ) cells. The light-transmissive component includes an inner space. The VMJ cells are disposed within the inner space of the light-transmissive component to receive light and perform light-to-electricity conversion. The VMJ cells are connected in series. The voltage source generator can generate a kV-level voltage and meet small-sized and low-cost demands. A voltage source module includes at least two voltage source generators connected to at least one electrical connector. | 2015-12-10 |
20150357499 | METHOD OF PROVIDING A BORON DOPED REGION IN A SUBSTRATE AND A SOLAR CELL USING SUCH A SUBSTRATE - Method of providing a boron doped region ( | 2015-12-10 |
20150357500 | PHOTOELECTRODE MATERIAL AND PHOTOCELL MATERIAL - A method of generating electricity utilizing silicon oxide is provided. The method includes irradiating a light to a photocell comprising a photovoltaic material which consists essentially of silicon oxide in a manner that causes the silicon oxide to generate the electricity in response to the irradiation of light, and correcting the electricity from the photovoltaic material. | 2015-12-10 |
20150357501 | FOUR JUNCTION INVERTED METAMORPHIC SOLAR CELL - A multijunction solar cell which includes: an upper first solar subcell having a first band gap; a second solar subcell adjacent to said upper first solar subcell and having a second band gap smaller than said first band gap; a third solar subcell adjacent to said second solar subcell and having a third band gap smaller than said second band gap; a graded interlayer adjacent to said third solar subcell, said graded interlayer having a fourth band gap greater than said third band gap; and a lower fourth solar subcell adjacent to said graded interlayer, said lower fourth solar subcell having a fifth band gap smaller than said third band gap such that said lower fourth solar subcell is lattice mismatched with respect to said third solar subcell. | 2015-12-10 |
20150357502 | GROUP IIB-VIA COMPOUND SOLAR CELLS WITH MINIMUM LATTICE MISMATCH AND REDUCED TELLURIUM CONTENT - A thin film solar cell structure is disclosed, the solar cell structure comprising a CdSe | 2015-12-10 |
20150357503 | Method and Apparatus for High Resolution Photon Detection based on Extraordinary Optoconductance (EOC) Effects - The inventors disclose a new high performance optical sensor, preferably of nanoscale dimensions, that functions at room temperature based on an extraordinary optoconductance (EOC) phenomenon, and preferably an inverse EOC (I-EOC) phenomenon, in a metal-semiconductor hybrid (MSH) structure having a semiconductor/metal interface. Such a design shows efficient photon sensing not exhibited by bare semiconductors. In experimentation with an exemplary embodiment, ultrahigh spatial resolution 4-point optoconductance measurements using Helium-Neon laser radiation reveal a strikingly large optoconductance property, an observed maximum measurement of 9460% EOC, for a 250 nm device. Such an exemplary EOC device also demonstrates specific detectivity higher than 5.06×10 | 2015-12-10 |
20150357504 | GRAPHENE TRANSISTOR OPTICAL DETECTOR BASED ON METAMATERIAL STRUCTURE AND APPLICATION THEREOF - A graphene transistor optical detector based on a metamaterial structure and an application thereof. The optical detector includes a substrate, a gate metal layer, a gate medium layer, a graphene layer, a source and drain metal layer successively arranged from bottom to top, wherein a local region of at least the source and drain metal layer has a periodic micro/nanostructure, the periodic micro/nanostructure being matched with the gate metal layer and the gate medium layer to form a metamaterial structure having a complete absorption characteristic. By changing the refractive index, thickness or the like of material for the periodic micro/nanostructure and the gate medium layer, a light absorption frequency band of the metamaterial structure can be regulated. The optical detector provided by the present invention has higher flexibility and narrow-band response, and can work under visible light to infrared even longer wavebands by selecting different metamaterial structures. | 2015-12-10 |
20150357505 | OPTICAL PROXIMITY SENSOR AND MANUFACTURING METHOD THEREOF - The present invention is an optical proximity sensor and manufacturing method thereof. The optical proximity sensor has an optical sensing unit, an illuminating unit, multiple transparent gels and a package. The package encapsulates the optical sensing unit and the illuminating unit. The transparent gels are respectively formed on top surfaces of the optical sensing unit and the illuminating unit. The transparent gels respectively have a convex part and a recess formed in the convex part. The package has through holes communicating with the recesses of the transparent gels to form openings. In a step of injecting encapsulant gel, because the transparent gels are still plastic, the protrusions can closely attach to the transparent gels. The encapsulant gel is prevented from forming above the sensing part and the illuminating part. | 2015-12-10 |
20150357506 | EMITTER DIFFUSION CONDITIONS FOR BLACK SILICON - In some cases, it is desirable to perform doping when manufacturing a solar cell to improve efficiency. Dopant diffusion may include the steps of: (a) an initial temperature ramp, (b) dopant vapor flow, (c) drive-in, and (d) cool down. However, doping may result in excessive doping, such as in regions where the solar cell has been nanoscale textured to provide black silicon, thereby creating a dead zone with excessive recombination of charge carriers. In the systems and method discussed herein, dopant vapor flow and drive-in steps may be performed at two different temperature set points to minimize or eliminate the formation of dead zones. In some embodiments, the dopant vapor flow may be performed at a lower temperature set point than the drive-in. | 2015-12-10 |
20150357507 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - Discussed is a method for manufacturing a solar cell. The method includes forming a tunneling layer on a semiconductor substrate; forming a semiconductor layer on the tunneling layer, wherein the forming of the semiconductor layer including depositing a semiconductor material; and forming an electrode connected to the semiconductor layer. The tunneling layer is formed under a temperature higher than room temperature and a pressure lower than atmospheric pressure. | 2015-12-10 |
20150357508 | OXIDE MEDIA FOR GETTERING IMPURITIES FROM SILICON WAFERS - The present invention relates to a novel process for the preparation of printable, low- to high-viscosity oxide media, and to the use thereof in the production of solar cells. | 2015-12-10 |
20150357509 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a solar cell includes forming a first dielectric layer on a second surface opposite a first surface of a substrate; forming second dielectric layers respectively on an emitter region and the first dielectric layer; forming a third dielectric layer on the second dielectric layer that is positioned on the emitter region; forming a hydrogenated silicon oxide layer on the third dielectric layer; forming a first electrode on the emitter region and connected to the emitter region; and forming a second electrode on the second surface of the substrate and connected to the substrate, wherein the first surface of the substrate has first and second textured surfaces, and wherein the first textured surface includes a plurality of first protrusions and a plurality of first depressions and the second textured surface includes a plurality of second protrusions and a plurality of second depressions. | 2015-12-10 |
20150357510 | METHOD FOR MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell is discussed. The method of manufacturing the solar cell includes: forming a conductive region on a semiconductor substrate; forming an electrode connected to the conductive region; and post-processing the semiconductor substrate to passivate the semiconductor substrate. The post-processing of the semiconductor substrate comprises a main processing process for heat-treating the semiconductor substrate while providing light to the semiconductor substrate. A temperature of the main processing process is about 100° C. to about 800° C., and the temperature and light intensity of the main processing process satisfy Equation of 1750−31.8·T+(0.16)·T | 2015-12-10 |
20150357511 | TRANSPARENT CONDUCTIVE COATINGS FOR OPTOELECTRONIC AND ELECTRONIC DEVICES - The invention provides processes for the manufacture of conductive transparent films and electronic or optoelectronic devices comprising same. | 2015-12-10 |
20150357512 | STRUCTURE WITH A METAL SILICIDE TRASPARENT CONDUCTIVE ELECTRODE AND A METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure. | 2015-12-10 |
20150357513 | CONTACTS FOR AN N-TYPE GALLIUM AND NITROGEN SUBSTRATE FOR OPTICAL DEVICES - A method for fabricating LED devices. The method includes providing a gallium and nitrogen containing substrate member (e.g., GaN) comprising a backside surface and a front side surface. The method includes subjecting the backside surface to a polishing process, causing a backside surface to be characterized by a surface roughness, subjecting the backside surface to an anisotropic etching process exposing various crystal planes to form a plurality of pyramid-like structures distributed spatially in a non-periodic manner on the backside surface, treating the backside surface comprising the plurality of pyramid-like structures, to a plasma species, and subjecting the backside surface to a surface treatment. The method further includes forming a contact material comprising an aluminum bearing species or a titanium bearing species overlying the surface-treated backside to form a plurality of LED devices with the contact material. | 2015-12-10 |
20150357514 | METHOD FOR MANUFACTURING LIGHT EMITTING ELEMENT - A method for manufacturing a light emitting element includes: preparing a wafer that has a substrate in which a first main face is provided with a plurality of convex components; and dividing the wafer along first dividing lines and second dividing lines. The convex components are in the form of circular cones or truncated circular cones, each of which having a circular bottom face and a side face that is connected to the bottom face, and disposed regularly so that a plurality of bounded regions are present around the convex components, and a shortest distance between the convex components and the centers of the bounded regions is less than a radius of the bottom faces of the convex components. The first and second dividing lines extend in a direction that intersects straight lines that link the centers of the plurality of bounded regions around a single convex component. | 2015-12-10 |
20150357515 | THIN LIGHT EMITTING DIODE AND FABRICATION METHOD - A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure. | 2015-12-10 |
20150357516 | Light-Emitting Diode Chip with Current Spreading Layer - A light-emitting diode chip includes a semiconductor layer sequence having a phosphide compound semiconductor material. The semiconductor layer sequence contains a p-type semiconductor region, an n-type semiconductor region, and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active region serves to emit electromagnetic radiation. The n-type semiconductor region faces a radiation exit area of the light-emitting diode chip, and the p-type semiconductor region faces a carrier of the light-emitting diode chip. A current spreading layer having a thickness of less than 500 nm is arranged between the carrier and the p-type semiconductor region. The current spreading layer has one or a plurality of p-doped Al | 2015-12-10 |
20150357517 | LIGHT EMITTING DIODE CHIP, LIGHT EMITTING DEVICE, AND WAFER-LEVEL STRUCTURE OF LIGHT EMITTING DIODE - A light emitting device is provided with a growing base having specific geometry to prevent delamination between the encapsulant and the growing base, and thereby enhance structural reliability of the light emitting device. Furthermore, the light emitting efficiency as well as uniformity of light output of the light emitting device can be improved by forming the side surface of the growing base with at least a curved portion or slanted portion, and uneven structures can be formed on the curved portion or slanted portion to further improve the uniformity of light output. Furthermore, the light emitting diode chips can be fabricated by taking batch processing on the growing substrate, as provided in the wafer-level structure, with the advantages of saving cost, improving yield, etc. | 2015-12-10 |
20150357518 | LIGHT EMITTING MODULE - A light emitting module includes: a substrate having a recess part formed thereon; a body surrounding some of side surfaces and an upper surface of the substrate; a light emitting diode chip positioned on the recess part of the substrate; and a lens positioned on the body, wherein the substrate includes a first step part positioned along an edge of the recess part and a second step part positioned along an edge of a lower surface thereof, and the lower surface of the substrate is exposed to the outside. | 2015-12-10 |
20150357519 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode (LED) chip including a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on said active layer; at least one indentation comprising a bottom part extending downward to reach the first semiconductor layer and exposing the first semiconductor layer; a first metal layer disposed on the second semiconductor layer, connecting to the first semiconductor layer at the bottom part of the indention; | 2015-12-10 |
20150357520 | NANOWIRE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices. | 2015-12-10 |