50th week of 2008 patent applcation highlights part 54 |
Patent application number | Title | Published |
20080307156 | System For Interfacing A Host Operating Through A Logical Address Space With A Direct File Storage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system. | 2008-12-11 |
20080307157 | Method and system for updating firmware of microcontroller - A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I | 2008-12-11 |
20080307158 | METHOD AND APPARATUS FOR PROVIDING DATA TYPE AND HOST FILE INFORMATION TO A MASS STORAGE SYSTEM - A method and system for providing advance data type information to a mass storage system is disclosed. The method may include a host system providing host file information, such as a host file identifier and/or a data type, to a memory system in addition to LBA format data. The system may include a processor, a memory system interface and a host file system operative on the processor to identify and provide host file information and/or data type information to the memory system along with LBA format data. | 2008-12-11 |
20080307159 | Method and control device for operating a non-volatile memory, in particular for use in motor vehicles - A method for the consecutive writing of performance quantity data to a non-volatile memory, in particular in a control device in a motor vehicle. The method encompasses the operations of determining a write address, which defines an address space for the writing of a performance quantity datum to be written, the address space being directly contiguous with a memory area occupied by a previously written performance quantity datum, and of writing the performance quantity datum to be written, to the address space of the non-volatile memory defined by the write address. In the determination operation, the write address corresponds directly to an address datum assigned to the most recently written performance quantity data, which is stored in a referencing datum in the non-volatile memory, or it is determined therefrom with the aid of an address offset that is independent of the size of the previously written performance quantity data. | 2008-12-11 |
20080307160 | METHODS AND STRUCTURE FOR IMPROVED STORAGE SYSTEM PERFORMANCE WITH WRITE-BACK CACHING FOR DISK DRIVES - Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In one aspect hereof, a state machine model of managing cache blocks in a storage controller cache memory maintains blocks in the storage controller's cache memory in a new state until verification is sensed that the blocks have been successfully stored on the persistent storage media of the affected disk drives. Responsive to failure or other reset of the disk drive, the written cache blocks may be re-written from the copy maintained in the cache memory of the storage controller. In another aspect, an alternate controller's cache memory may also be used to mirror the cache blocks from the primary storage controller's cache memory as additional data integrity assurance. | 2008-12-11 |
20080307161 | Method For Accessing Target Disk, System For Expanding Disk Capacity and Disk Array - The present invention discloses a method for accessing a target disk and a system for expanding disk capacity. A processing unit of a master disk array sends a command or data to a PCIe switching unit of the master disk array upon receipt of the command or data; the PCIe of the master disk array sends the received command or data to a control unit in a corresponding disk array according to an address of a target disk indicated in the command or data; the control unit in the corresponding disk array sends the received command or data to the target disk that is directly connected to the control unit. The present invention also discloses a master disk array and a slave disk array. | 2008-12-11 |
20080307162 | PRELOAD CONTROLLER, PRELOAD CONTROL METHOD FOR CONTROLLING PRELOAD OF DATA BY PROCESSOR TO TEMPORARY MEMORY, AND PROGRAM - A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data. | 2008-12-11 |
20080307163 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 2008-12-11 |
20080307164 | Method And System For Memory Block Flushing - A method and system for flushing physical memory blocks in a memory device is disclosed. The method includes detecting a quantity of available memory, background flushing partially obsolete memory blocks if the quantity decreases to a background activation threshold, disabling the background flushing if the quantity increases to a background deactivation threshold, foreground flushing the partially obsolete memory blocks if the quantity decreases to a foreground activation threshold, and disabling the foreground flushing if the quantity increases to a foreground deactivation threshold. The thresholds may be adaptively defined. The background flushing may occur when the host interface is idle. The foreground flushing may interleave writing operations with flushing operations while a write command is unfinished. The system includes a memory for receiving data with a host write command, and a controller for detecting a quantity of available memory and enabling and disabling background and foreground flushing depending on adaptive thresholds. | 2008-12-11 |
20080307165 | INFORMATION PROCESSOR, METHOD FOR CONTROLLING CACHE FLASH, AND INFORMATION PROCESSING CONTROLLER - An information processor, a method for controlling cache flush, and an information processing controller that increases the data processing speed by efficiently performing cache flushing on a cache memory. A CPU includes a load/store unit and a flush control unit. The CPU controls data stored in a cache through a cache controller. When detecting an “.f” signal, the flush control unit waits until a single cache line is accessed. When determining that a single cache line has been accessed, the flush control unit issues a cache flush instruction to a cache controller. | 2008-12-11 |
20080307166 | Store Handling in a Processor - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 2008-12-11 |
20080307167 | Converting Victim Writeback to a Fill - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 2008-12-11 |
20080307168 | Latency Reduction for Cache Coherent Bus-Based Cache - In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response. | 2008-12-11 |
20080307169 | Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory - A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is accessed in the memory directory array. In response to the access, the coherence directory returns, as a result of the first directory lookup request, contents of a first sector that is identified by the target address as a requested sector. The coherence directory also caches contents of a second sector of the multiple sectors that is a non-requested sector for the first directory lookup request in a prefetch sector cache. In response to receiving a subsequent second directory lookup request specifying a second target address that identifies the second sector as a requested sector, the coherence directory accesses the contents of the second sector in the sector prefetch cache and returns the contents of the second sector as a result of the second directory lookup request. | 2008-12-11 |
20080307170 | MEMORY MODULE AND MEMORY SYSTEM - A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group. | 2008-12-11 |
20080307171 | SYSTEM AND METHOD FOR INTRUSION PROTECTION OF NETWORK STORAGE - Protection mechanism is provided for data stored in logical volumes, especially during the time the corresponding host computer is off line. Additionally, integrity check mechanism is provided for logical volume when the host computer is started, so that host computer can detect unauthorized access to its assigned logical volume during off-line period, and execute security check. | 2008-12-11 |
20080307172 | SYSTEM AND METHOD FOR REPRODUCING MEMORY ERROR - An information processing apparatus includes a nonvolatile memory area having a storage area, and a main controller configured to store an access pattern to a main memory in the nonvolatile memory area, to end the storage of the access pattern when an error is detected in the main memory, and to access the main memory based on the access pattern stored in the nonvolatile memory area. The main controller includes a main memory control unit configured to access the main memory based on the access pattern; a nonvolatile memory control unit configured to store a data of the access pattern in the nonvolatile memory area; and a main control unit configured to transfer the access pattern for the main memory to the main memory control unit and the nonvolatile memory control unit. | 2008-12-11 |
20080307173 | Efficient Encoding for Detecting Load Dependency on Store with Misalignment - In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation. | 2008-12-11 |
20080307174 | Dual Use Memory Management Library - A dual-use library that is able to handle calls from programs requiring either reference count or garbage collected memory management is described. This capability may be provided by introducing a new assignment routine, assign( ), and instrumenting the reference count routines responsible for updating an object's reference count—e.g., addReference( ) and removeReference( ) routines. The assign( ), addReferenc( ) and removeReference( ) routines determine, at runtime, which memory management scheme is appropriate and execute the appropriate instructions (i.e., reference count or garbage collection specific instructions). The described dual-use library provides equivalent functionality as prior art two library implementations, but with a significantly lower memory footprint. | 2008-12-11 |
20080307175 | System Setup for Electronic Backup - Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes detecting a remote storage device, prompting the user to use the detected remote storage device for backup operations, receiving a user input to use the detected remote storage device for backup operations, and automatically configuring backup operations using the remote storage device. Other embodiments of this aspect include corresponding systems, apparatus, computer program products, and computer readable media. | 2008-12-11 |
20080307176 | Storage System and Setting Method for Storage Configuration Information - Pairs are formed from a plurality of dispersed volumes and copying between the volumes is conducted by a series of remote operations from a management server. A management server | 2008-12-11 |
20080307177 | PROGRAM CONVERSION DEVICE - An analysis section analyzes the live range of a first variable shared among subroutines and the live range of a second variable used only in a subroutine. The allocation section allocates the second variable in an allocation memory for the first variable if the live ranges of the first and second variables do not overlap each other. | 2008-12-11 |
20080307178 | DATA MIGRATION - The present invention provides for a method for managing the storage of data in a computing system that includes a data processor and local physical storage, involving the steps of: defining a virtual storage volume for access by the data processor, the data processor including a local storage pool mapped to the local physical storage and a remote storage pool mapped to physical storage at a remote site, and the virtual storage volume being overallocated with respect to the local storage pool; and migrating data between the local storage pool and the remote storage pool according to a defined migration policy. | 2008-12-11 |
20080307179 | SHARED DATA MIRRORING APPARATUS, METHOD, AND SYSTEM - A network component useful in tracking write activity by writing logs containing write address information is described. The tracking component may be used in networked systems employing data mirrors to record data block addresses written to a primary storage volume during the time a data mirror is unavailable. The tracking component can be available to any network originating node, and may therefore track write activity on multiple volumes. At the time a data mirror is reconstructed, the log written may be used to construct a list of block addresses pointing to locations on a primary storage volume wherein data differs from a secondary storage volume member of the mirror. The locations may be copied from the primary to secondary storage volume to reconstruct the data mirror. The performance impact of the tracking component is minimal and a shared network resource is offered that increases fault tolerance in the event of backup device failures. | 2008-12-11 |
20080307180 | VIRTUAL MACHINE CONTROL PROGRAM AND VIRTUAL MACHINE SYSTEM - The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in the case of operating a first OS that has a function of making another OS run on a virtual machine. A VMM creates a shadow PT for prohibiting reading-writing of privileged memory that requires emulation of reading/writing by using a RSV-bit, and registers the shadow PT and the second PT that a second OS operating on the first OS has in an x86 compatible CPU equipped with a page exception detecting function using two PT's. When a page exception occurs, the VMM refers to a cause code of the page exception and, when a P field of the cause code is 0, determines immediately that emulation is unnecessary. | 2008-12-11 |
20080307181 | Disk-Resident Streaming Dictionary - A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that is faster than one insertion per disk-head movement. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk. The dictionary employs indirect logging for physical block logging. | 2008-12-11 |
20080307182 | EFFICIENT AND FLEXIBLE MEMORY COPY OPERATION - A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline. | 2008-12-11 |
20080307183 | AUTOMATIC MEMORY MANAGEMENT (AMM) - The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident AMM activity appears to be imminent. If AMM patterns suggest that two VMs are likely to perform a (e.g., a major) AMM cycle simultaneously (or with significant overlap) in the near future, the supervisory process can trigger one of the VMs to AMM immediately, or at the first ‘safe’ interval prior to the predicted AMM collision. This will have the effect of desynchronizing the AMM behavior of the VMs and maintaining AMM latency for both VMs within the expected bounds for their independent operation, without any inter-VM effects. | 2008-12-11 |
20080307184 | MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK - The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access. | 2008-12-11 |
20080307185 | APPARATUS AND METHOD TO SET SIGNAL COMPENSATION SETTINGS FOR A DATA STORAGE DEVICE - A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length. | 2008-12-11 |
20080307186 | CONFORMAL ROLLING BUFFER APPARATUS, SYSTEMS, AND METHODS - Methods, apparatus, and systems may operate to more efficiently utilize data stored in an array of storage blocks organized as rows and columns of contiguous blocks, where non-linearity is present in the data. Activities may include organizing data to discard useless elements from storage blocks when transferring the data to a memory buffer, and perhaps compressing the data for increased memory density utilization. Additional activities may include reconstructing data stored in the memory buffer and using an image distortion formula to display a linear representation of the non-linear data. | 2008-12-11 |
20080307187 | ARRANGEMENTS FOR MEMORY ALLOCATION - In one embodiment a method is disclosed for allocating memory for a processor unit in a group of processing units. The method can include receiving a memory allocation request where the request can indicate a number of binary segments to be stored. The method can determine if the number indicates a nonstandard allocation, and locate an unallocated memory address based on a multiple of the number if the number indicates a nonstandard allocation. The method can also include locating an unallocated memory address from a pool of memory addresses, where the pool of addresses includes the integer multiples of the binary segments and excludes addresses that are two times the number of binary segments such that the address can be utilized to determine the allocation. | 2008-12-11 |
20080307188 | Management of Guest OS Memory Compression In Virtualized Systems - The present invention provides a system and method for managing compression memory in a computer system. This system includes a hypervisor having means for identifying a operating system having a plurality of memory pages allocated, means for counting the number of a plurality of memory pages allocated, and means for counting a number of free space pages in the compressed memory. The hypervisor further includes means for determining if the number of free space pages is less than a predetermined threshold, and means for increasing the number of free space pages if less than a predetermined threshold. | 2008-12-11 |
20080307189 | Data partitioning via bucketing bloom filters - Multiple Bloom filters are generated to partition data between first and second disjoint data sets of elements. Each element in the first data set is assigned to a bucket of a first set of buckets, and each element in the second data set is assigned to a bucket of a second set of buckets. A Bloom filter is generated for each bucket of the first set of buckets. The Bloom filter generated for a bucket indicates that each element assigned to that bucket is part of the first data set, and that each element assigned to a corresponding bucket of the second set of buckets is not part of the first data set. Additionally, a Bloom filter corresponding to a subsequently received element can be determined and used to identify whether that subsequently received element is part of the first data set or the second data set. | 2008-12-11 |
20080307190 | System and Method for Improved Virtual Real Memory - A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is not available, the system generates a page fault interrupt, wherein the page fault interrupt comprises a first page fault correlation number (PFCID) identifying a restorative process, and wherein the restorative process is configured to restore the requested memory page to available memory. The system monitors a plurality of pending processes and determines whether the restorative process is complete. In the event the restorative process is complete, the system notifies the requester that the restorative process is complete. | 2008-12-11 |
20080307191 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MANAGING THE STORAGE OF DATA - The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks of data meeting the compression policy are identified. A physical block is selected as a source block for data compression, and one or more physical locations are selected as target locations. Data is read from the source block, compressed, and written to the target locations. Metadata is updated to indicate a mapping between the target locations and the virtual blocks previously mapped to the source block. Extra storage capacity can be freed up until more physical storage is ordered and installed, while more important data, such as recently or frequently accessed data, is retained in an uncompressed and accessible state. | 2008-12-11 |
20080307192 | Method And System For Storage Address Re-Mapping For A Memory Device - A method and system for storage address re-mapping is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of data dispersed in logical address space are mapped in a contiguous manner into blocks in storage address space. Valid data is flushed from blocks having both valid and obsolete data to make new blocks available for receiving data when an available number of new blocks falls below a desired threshold. The system includes a host file system, processor executable instructions residing on a host separately from the host file system or residing on a flash memory device such as an embedded solid state disk, or a backend memory manager of the flash memory device that is configured to map data from a logical address space to complete blocks in storage address space in a contiguous manner. | 2008-12-11 |
20080307193 | Semiconductor integrated circuit - A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m≧2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string. | 2008-12-11 |
20080307194 | Parallel, Low-Latency Method for High-Performance Deterministic Element Extraction From Distributed Arrays - The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a local array with elements from input, a module that submits a largest element value in the local array and a processor ID for a local processor, and a module that determines a globally largest element value from the largest element values submitted by each one of the plurality of processors. The system further includes a module that broadcasts a winning globally largest element value and winning processor ID to the plurality of processors, and a module that increments an element pointer to the next value in the local array if the winning processor ID equals the processor ID for the local processor. | 2008-12-11 |
20080307195 | Parallel, Low-Latency Method for High-Performance Speculative Element Extraction From Distributed Arrays - The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a result array with globally largest elements from the input, a module that generates a partition element, a module that counts the number of local elements greater than the partition and a module that determines the globally largest elements. The method for extracting elements from distributed arrays on a parallel processing system includes populating a result array with globally largest elements from the input, generating a partition element, counting the number of local elements greater than the partition and determining the globally largest elements. | 2008-12-11 |
20080307196 | Integrated Processor Array, Instruction Sequencer And I/O Controller - A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data. | 2008-12-11 |
20080307197 | System and Method for Persistent Hardware System Serial Numbers - A system for computer hardware serial number management includes a computer system chassis comprising a chassis serial number. The chassis serial number is embodied on the computer system chassis as a physical serial number. A first RFID tag is attached to the computer system chassis at a first location. The first RFID tag stores indicia of the physical serial number. A first electronic device couples to the computer system chassis, and comprises a first RFID reader configured to retrieve the stored indicia of the physical serial number from the first RFID tag and to determine the chassis serial number based on the retrieved indicia of the physical serial number. | 2008-12-11 |
20080307198 | SIGNAL-PROCESSING APPARATUS AND ELECTRONIC APPARATUS USING SAME - A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility. | 2008-12-11 |
20080307199 | Portable extended display identification data burning device - The present invention relates to a portable extended display identification data (EDID) burning device, which could perform an EDID burning operation via an input device without connecting to a computer. The portable EDID burning device comprises: at least one video connection interface connected to a to-be-burned display device, a memory unit used for storing EDID and system data, an input device interface used for connecting to the input device, and a microcontroller electronically connected to the at least one video connection interface, the memory unit and the input device interface. Therefore, the present invention could be departed from a computer structure and could directly burn in the EDID. That is, the present invention could burn in more than one connection interface at a time during an independent operation, thereby saving cost and time. | 2008-12-11 |
20080307200 | Method of burning in extended display identification data without using a computer - The present invention relates to a method of burning in extended display identification data (EDID) without using a computer, wherein an EDID burning device is connected to an input device via an input device interface, a product barcode labeled on a to-be-burned display device is inputted for obtaining product data which is then respectively merged into a plurality of EDID, and then an EDID burning operation is performed to the to-be-burned display device via a VGA video connection interface, a DVI video connection interface and a HDMI video connection interface at the same time. Therefore, the present invention could be departed from a computer structure and could directly burn in the EDID. That is, the present invention could burn in more than one connection interface at a time during an independent operation, thereby saving cost and time. | 2008-12-11 |
20080307201 | Method and Apparatus for Cooperative Software Multitasking In A Processor System with a Partitioned Register File - A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code. | 2008-12-11 |
20080307202 | LOADING TEST DATA INTO EXECUTION UNITS IN A GRAPHICS CARD TO TEST THE EXECUTION UNITS - Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode. | 2008-12-11 |
20080307203 | Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces - A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces. | 2008-12-11 |
20080307204 | Fast Static Rotator/Shifter with Non Two's Complemented Decode and Fast Mask Generation - In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. Coupled to receive the input operand and the shift count, the rotator is configured to rotate the input operand by the shift count. Coupled to receive the shift count and the shift direction, the mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction. Additionally, in one embodiment, the rotator may be configured to perform a right rotate/shift operation using a left rotate and without performing a two's complement operation on the rotate/shift count. | 2008-12-11 |
20080307205 | COMPUTATIONALLY EFFICIENT MATHEMATICAL ENGINE - A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic unit circuits that are configured to process data in parallel to provide processed data outputs and an adder tree configured to add the processed data outputs from the arithmetic logic circuits. A shift register that has more parallel data outputs then the processor's inputs is controlled to selectively output data from the parallel outputs to the data inputs of the processor. A communication device preferably includes the calculation unit to facilitate processing of wireless communication signals. | 2008-12-11 |
20080307206 | METHOD AND APPARATUS TO EFFICIENTLY EVALUATE MONOTONICITY - A method and processor to evaluate a monotonicity of a set of input values is disclosed. The processor achieves high processing power by means of an arbitrary number of identical parallel processing elements. Each processing element allows instruction dependent data paths and makes use of ALU factories which consist of a number of separate arithmetic logical units (ALUs) are arranged in a special kind of matrix. The processor allows parallel evaluation and analysis of the monotonicity of a multitude of sets of values. A threshold value can be freely configured to allow an uncertainty of nearly equal values which is of high importance in digital signal processing. | 2008-12-11 |
20080307207 | DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR - A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes. | 2008-12-11 |
20080307208 | Application specific processor having multiple contexts - An application specific processor executes multiple dedicated applications in a system having a main control processor for controlling the operation of the system. The application specific processor includes a first context for executing a corresponding first application and a second context for executing a corresponding second application. An instruction memory outputs instructions for executing the first and second applications, and a context switch instruction for switching from one context to the other context. Context is switched in response to the context switch instruction while executing the first or second application. | 2008-12-11 |
20080307209 | METHODS AND APPARATUS FOR IMPLEMENTING POLYMORPHIC BRANCH PREDICTORS - A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to select one or more of the branch prediction methods in accordance with a dynamic setting to optimize performance of the branch predictor during operation in accordance with a current task. | 2008-12-11 |
20080307210 | System and Method for Optimizing Branch Logic for Handling Hard to Predict Indirect Branches - A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct. | 2008-12-11 |
20080307211 | METHOD AND APPARATUS FOR DYNAMIC CONFIGURATION OF AN ON-DEMAND OPERATING ENVIRONMENT - A method is provided for systematic and dynamic configuration of an On Demand Operating Environment (ODOE) and the business solutions built upon the ODOE. The method provides a configuration specification that defines an On Demand Configuration Language (ODCL). An editor enables the business user to describe the consistency constraints applicable to the business in terms of the ODCL. This language is then used to transform the high-level business consistency constraints to low-level configuration parameters applicable to services and hosted business solutions in the ODOE. These services and hosted business solutions are organized into a plurality of layers to facilitate development of the configuration specification and better enable controls over consistent implementation of configuration changes. A two phase configuration commitment protocol is provided to ensure the consistent implementation of interdependent configuration parameters applicable to the services and hosted business solutions within the ODOE. | 2008-12-11 |
20080307212 | DATA PROCESSING DEVICE - A data processing device is disclosed that is able to limit functions of a connected apparatus without providing additional components in the apparatus and without dependence on types of the apparatus. The data processing device includes a function limiting file storage unit to store a function limiting file; a function list file storage unit to store function list files dependent upon the apparatus type and function list files independent of the apparatus type, the function list files including descriptions of functions available in the apparatus; a function list file selection unit to select one of the function list files corresponding to the apparatus type; and a display item generation unit to generate a setting screen image for setting operations of the apparatus based on the selected function list file and the function limiting file stored in the function limiting file storage unit. | 2008-12-11 |
20080307213 | DEVICE ALLOCATION CHANGING METHOD - Switching of the allocation of a device to a guest OS is implemented through transmission of a virtual suspension interrupt to a guest OS in a VMM; a power control notification process module that causes the guest OS to start a return process from a suspended state; a guest power process module that traps a suspension process of the guest OS; an I/O configuration change process module that updates a logical device definition of the VMM in the suspended state of the guest OS; a guest I/O emulation process module that emulates an I/O instruction that is issued by an I/O reconfiguration process module and that is executed when the guest OS has returned from the suspended state, thereby to provide a new logical device configuration to the guest OS. | 2008-12-11 |
20080307214 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 2008-12-11 |
20080307215 | REMOTE COMPUTER OPERATING SYSTEM UPGRADE - Methods of upgrading a kernel image of a remote computer are described. The method comprises, during a first connection between an update computer and a remote computer, storing a kernel version identifier of the active kernel image of the remote computer; storing active boot partition information comprising the active kernel boot partition of the remote computer; setting the active boot partition of the remote computer as a safe boot partition; storing a second kernel image at the remote computer, wherein the second kernel image comprises a second kernel version identifier; setting the remote computer to boot from the second kernel image; rebooting the remote computer; and, during a second connection between the update computer and the remote computer, marking the second kernel image as a safe kernel image if the active kernel version is the same as the second kernel version identifier. | 2008-12-11 |
20080307216 | METHOD AND APPARATUS FOR BOOTING A COMPUTER SYSTEM - In investigating the cause of a fault in a computer storage system, it is considered useful to previously prepare maintenance logical units (LUs) of a simple structure, the operation of which has been confirmed. If the same number of LUs as servers are prepared for each server as in the prior art, the efficiency is low. Furthermore, securing these LUs complicates assignment of the LUs for construction of a system and a work for addressing the fault. The present invention provides a computer system free of these problems. The computer system has a first computer for executing a first OS (operating system), a second computer for executing a second OS, and a storage array system. The storage array system uses a disk device having a logical unit (LU) for storing a boot loader, as well as the first and second OSes. The boot loader is executed on any one of the two computers, reads in any of the OSes corresponding to the currently operating computer into this operating computer, and executes the read OS. | 2008-12-11 |
20080307217 | CONTENTS TRANSMITTING/RECEIVING APPARATUS AND METHOD - A contents transmitting apparatus includes an encryption algorithm storage section for storing a plurality of encryption algorithms; a key generation section for generating key information based on a mutual authentication result with a contents receiving apparatus; a control section for selecting one encryption algorithm from the encryption algorithm storage section and acquiring a key from the key information to provide it to an encryption section. The encryption section encrypts a content by use of a given encryption algorithm and a given key. During a period in which the generated key information is valid, a different encryption algorithm is selected from the encryption algorithm storage section every time a content to be transmitted is changed, and a different key is acquired from the key information for encryption. | 2008-12-11 |
20080307218 | System and method for using an out-of-band device to program security keys - A provisioning device is provided that communicates over a trusted out-of-band communications channel to digital electronic devices in order to exchange security data such as passwords and private or public keys, thereby establishing a secure communications network between the devices. | 2008-12-11 |
20080307219 | SYSTEM AND METHOD FOR DISTRIBUTED SSL PROCESSING BETWEEN CO-OPERATING NODES - A secure communication protocol (e.g., SSL) transaction request from a client to a server is intercepted at a client-side proxy communicatively coupled to the client and logically deployed between the client and the server. The client-side proxy initiates a secure connection with the server and passes an attribute (e.g., a cryptographic key) associated with that secure connection to a server-side proxy communicatively coupled to the server and logically deployed between the client and the server. This enables the server-side proxy to engage in secure communications with the server in a transparent fashion. | 2008-12-11 |
20080307220 | VIRTUAL CLOSED-CIRCUIT COMMUNICATIONS - A virtual closed circuit supports transactions between businesses and consumers. More generally, techniques are disclosed for supporting a secure, non-public, business-to-consumer communication link suitable for use with financial transactions and other data communications related thereto. The communication link may be deployed in a desktop widget or other application to integrate communications and interactions with various authenticated online businesses. | 2008-12-11 |
20080307221 | Event-Ordering Certification Method - An event-ordering certification system | 2008-12-11 |
20080307222 | Verifying authenticity of webpages - A certificate registry system is configured to issue authentication certificates issued to each one of a plurality of information providers and to maintain a root certificate corresponding to all of the authentication certificates. Each one of the authentication certificates links respective authentication information thereof to identification information of a corresponding one of the information providers. Each one of the authentication certificates is devoid of linkage between the corresponding one of the information providers and domain name information thereof. The authentication certificates of the certificate registry are associated in a manner at least partially dependent upon at least one of a particular type of information that the information providers provide, a particular organization that the information providers are associated with, a particular type profession in which the information providers are engaged and a particular geographical region in which the information providers are located. | 2008-12-11 |
20080307223 | APPARATUS AND METHOD FOR ISSUER BASED REVOCATION OF DIRECT PROOF AND DIRECT ANONYMOUS ATTESTATION - In some embodiments, a method and apparatus for issuer based revocation of direct proof and direct anonymous attestation are described. In one embodiment, a trusted hardware device convinces a verifier that the trusted hardware device possesses cryptographic information without revealing unique, device identification information of the trusted hardware device or the cryptographic information. Once the verifier is convinced that the hardware device possesses the cryptographic information, the verifier may issue a denial of revocation request to the trusted hardware device, including a base value B | 2008-12-11 |
20080307224 | Removable Secure Portable Electronic Entity Including Means for Authorizing Deferred Retransmission - A removable secure portable electronic entity includes elements for receiving a broadcast digital content, elements for sending the received broadcast digital content, secure elements for deferred retransmission of the received digital content adapted to prohibit reproduction of the received digital content prior to sending it and to instigate the deferred sending of the received digital content by the sending elements, the elements being adapted to operate in parallel mode or in quasi-parallel mode. In variants, the secure deferred retransmission elements include a unit for storing the received digital content, for example a non-volatile memory. In variants, the secure deferred retransmission elements include members for authentication of a user. | 2008-12-11 |
20080307225 | Method For Locking on to Encrypted Communication Connections in a Packet-Oriented Network - There is described a method for locking on or legal interception of encrypted communication connections, preferably in a peer-to-peer network. If all users in a communication network have a digital certificate, a good authentication and an end-to-end encryption of communication data is possible. A modification of network elements is disclosed to nevertheless provide legal tapping from authorized positions. The above can be used on a special tapping mode, in which the keys for all incoming and outgoing messages are provided to an authorized control position. | 2008-12-11 |
20080307226 | Verifying authenticity of e-mail messages - A certificate registry system configured to issue authentication certificates to each one of a plurality of information providers and to maintain a root certificate corresponding to all of the authentication certificates, wherein each one of the authentication certificates links respective authentication information thereof to identification information of a corresponding one of the information providers, wherein each one of the authentication certificates is devoid of linkage between the corresponding one of the information providers and e-mail address information thereof, and wherein the authentication certificates of the certificate registry are associated in a manner at least partially dependent upon at least one of a particular type of information that the information providers provide, a particular organization that the information providers are associated with, a particular type profession in which the information providers are engaged and a particular geographical region in which the information providers are located. | 2008-12-11 |
20080307227 | Digital-Invisible-Ink Data Hiding Schemes - A novel steganographic approach analogous to the real-world secret communication mechanism, in which messages to be concealed are written on white papers using invisible ink like lemon juice or milk and are revealed only after the papers are heated, is proposed. Carefully designed informed-embedders now play the role of “invisible ink”; some pre-negotiated attacks that can be provided by common content processing tools correspond to required “heating” process. Theoretic models and feasible implementations of the proposed digital-invisible-ink (DII) watermarking approach are provided. The proposed DII watermarking schemes can prevent the supervisor from interpreting secret messages even the watermark extractor, decryption tool, as well as session keys are available to the supervisor. Furthermore, under certain steganographic application scenarios, secret communication systems employing the DII watermarking schemes can aggressively mislead the channel supervisor with fake payloads and transmit genuine secrets at the same time. | 2008-12-11 |
20080307228 | WEDI: AN ENCRYPTION-BASED METHOD AND SYSTEM FOR THE IDENTIFICATION AND PROTECTION OF PRINTED DOCUMENTS OR THOSE BEING TRANSMITTED BY ELECTRONIC MEANS - WEDI it is both a method and a system that uses symmetric and asymmetric encryption algorithms which makes feasible the identification of printed documents or those being transmitted by electronic means, and allows to hold responsible any person who discloses the information they contain in an illegal way or without authorization. WEDI is the acronym for “Watermark Encryption Document Identification”. It is both a method and a system that makes feasible the identification of printed documents and the information they carry upon being distributed by electronic means through the generation and printing of a cryptographic key in a watermark format, which is generated by the use of symmetric and asymmetric encryption algorithms and Hashing's function based on various data related to documents, devices, and persons involved in the process. This makes possible the identification of the aforesaid documents concerning their origin, recipient, date and time of generation and dispatch, user's responsibility, and other information pertaining such documents through the analysis of just a portion of them that contains fragments of the cryptographic key in the form of a printed watermark, which is the ultimate goal of the invention now being presented. | 2008-12-11 |
20080307229 | Method And Apparatus For Certificate Roll-Over - A method and an electronic apparatus for rolling over from a first to second trusted certificate in the electronic apparatus. Information containing identification data for identifying the second trusted certificate is acquired in the electronic apparatus. Also, the second trusted certificate, which is preinstalled in the electronic apparatus, is activated based on said identification data. | 2008-12-11 |
20080307230 | CONTROL DEVICE, UPDATE METHOD AND CONTROL SOFTWARE - To update the program, the file is updated by verifying according to a digital signature attached to the file having the program converted whether the file is not dishonestly falsified. To verify the digital signature, a time for verifying the signature can be shortened by verifying not the entire file but only a particularly important part, and an area for temporarily storing the file can be made small. Thus, the control can be performed to update only when the file is valid. | 2008-12-11 |
20080307231 | Secure Handling of Stored-Value Data Objects - An approach to managing stored-value data objects, such as electronic tickets, comprises secure systems and procedures for ticket issuing, storage, and redemption. With these systems and procedures in place, stored-value data objects may be securely transferred to remote systems, such as a user's personal electronic device, for subsequent secure redemption, thus allowing the user to gain access to the desired goods or service upon redeeming the data object. Techniques provide secure delivery of the requested data object to the requesting device, and provide secure redemption and disposal of the data object. Ticket issuing systems may be Internet-accessible systems, and users may purchase and redeem tickets using mobile terminals or other devices adapted for wireless communication. Standardized WPKI and Internet access procedures may be employed in ticket issuance and redemption. Techniques further provide temporary and rapid verification data objects useful where rapid ticket verification is essential, such as mass transit systems. | 2008-12-11 |
20080307232 | Method and a System for Authenticating and Recording Digital Documents and/or Files - A method and a system are provided according to the present invention for authenticating and restoring digital files and/or documents, according to which, on the basis of each digital document to be authenticated, a bitmap file | 2008-12-11 |
20080307233 | Encoded Data Security Mechanism - A method and system for securing and tracing confidential data is described. A request to generate a hardcopy printout is received by a computing device. Document output instructions for the request then are generated and data to associate with the document output instructions is determined. Then the determined data is encoded with the generated document output instructions. The encoded data includes information specific to a terminal device associated with the request and an identifier representative of a starting position for reading the encoded data. One ore more software modules within a terminal device, an intermediate server, and/or a printer may perform the operation of encoding the data. A hardcopy printout includes the content requested to be printed in addition to the encoded data. The encoded data may appear as representations of noise on one or more pages of the hardcopy printout. | 2008-12-11 |
20080307234 | USE OF MOBILE COMMUNICATION NETWORK CREDENTIALS TO PROTECT THE TRANSFER OF POSTURE DATA - In one embodiment, a method for using credentials for a mobile node to protect the transfer of posture data is provided. A network access device receives a message from a mobile node for access to a network. The message includes posture data encrypted using credentials for the mobile node. The credentials may be found in a storage card that is used to identify the mobile node. The network access device determines decryption information for the mobile node. For example, the credentials for the mobile node may be stored in a home location register (HLR) and are retrieved. The posture data is then decrypted using the credentials. The posture data is processed in a network admission control procedure for allowing access to the network. For example, a policy for access to the network may be installed based on the posture data. | 2008-12-11 |
20080307235 | METHOD OF PRESENTING FEEDBACK TO USER OF CHANCES OF PASSWORD CRACKING, AS THE PASSWORD IS BEING CREATED - A method, system and computer program product for automatically displaying the potential risk associated with cracking a password. While creating or modifying a password, feedback is provided describing the risk associated with cracking the password. Risk assessment may be presented as a percentage, accompanied by an explanation of why the value was ascertained. Risk feedback during password creation provides an opportunity to improve computer, document, and file security. | 2008-12-11 |
20080307236 | METHOD AND APPARATUS FOR PASSWORD OUTPUT - A method and an apparatus for account and/or password output are disclosed. In the present invention, a hot-key corresponding to an account and/or a password is set in advance. By entering the hot-key, the related account and/or password is transferred and login automatically, thus the purpose of making login more conveniently is achieved. Besides, the present invention combines various input device to make the way of setting hot-key become more diversely, therefore security of password login is also enhanced. | 2008-12-11 |
20080307237 | Method for improving accuracy of a time estimate used to authenticate an entity to a memory device - A method for improving accuracy of a time estimate used to authenticate an entity to a memory device is disclosed. In one embodiment, a memory device receives a request to authenticate an entity. Before attempting to authenticate the entity, the memory device determines if a new time stamp is needed. If a new time stamp is needed, the memory device receives the new time stamp and then attempts to authenticate the entity using a time estimate based on the new time stamp. In another embodiment, the memory device comprises a plurality of different time stamp update policies (TUPs) that specify when a new time stamp is needed, and the determination of whether a new time stamp is needed is based on a TUP associated with the entity. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 2008-12-11 |
20080307238 | System for Unified Management of Power, Performance, and Thermals in Computer Systems - A system is provided for unified management of power, performance, and thermals in computer systems. This system incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The system employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The system provides interfaces for user-level interaction. The system also employs methods to address power/thermal concerns at multiple timescales. In addition, the system improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion. | 2008-12-11 |
20080307239 | ELECTRONIC DEVICE AND POWER SUPPLY METHOD - According to one embodiment, an electronic device includes: a switch which switches between connection and disconnection of a sideband signal transmitted by a device attached to the electronic device; a power switch circuit which switches between supply and interrupt of power to the device; a nonvolatile memory which holds a setting; and a control section which controls the switch and the power switch circuit based on the setting. | 2008-12-11 |
20080307240 | POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit including a power managed circuit ( | 2008-12-11 |
20080307241 | Microcontroller circuit and power saving method thereof - A microcontroller circuit provides proper clocks to a central processing unit of a microcontroller and peripherals according to a power saving mode and operating conditions of the peripherals. The microcontroller circuit comprises a prescaler, a second multiplexer, a central processing unit, a first switch, a second switch, a first peripheral, and an execution unit. The execution unit is installed in the central processing unit and used for controlling the first switch and the second switch. The switches control the transmission of clocks according to the power saving mode operated by the microcontroller circuit, so that the central processing unit and each peripheral can work with a proper clock to reduce power use. | 2008-12-11 |
20080307242 | COMPUTER SYSTEM POWER SOURCE WITH IMPROVED LIGHT-LOAD EFFICIENCY - Embodiments of the present invention provide a system that supplies power in a computer system. The system includes a power adapter coupled to a source of electrical power and a set of a set of power consumers coupled to a power bus in the computer system. A full-power mechanism coupled between the power adapter and the power bus supplies power for the power consumers while the computer system is operating in a full-power mode. A low-power mechanism coupled between the power adapter and the power bus in parallel with the power mechanism supplies power for the power consumers while the computer system is in operating in a low-power mode. | 2008-12-11 |
20080307243 | Anticipatory Power Management for Battery-Powered Electronic Device - Methods and apparatus for managing power consumption of a battery-powered electronic device are disclosed. According to one embodiment, power management can take action to reduce power consumption to accommodate estimated power requirements. According to another embodiment, power management can notify a user when a power deficiency is anticipated. According to still another embodiment, power management can advise a user to charge a battery of the battery-powered electronic device. According to still another embodiment, a user can influence power management by user selections. | 2008-12-11 |
20080307244 | Method of and Apparatus for Reducing Power Consumption within an Integrated Circuit - An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered. | 2008-12-11 |
20080307245 | Methods and systems to dynamically manage performance states in a data processing system - Methods and apparatuses to dynamically manage a performance state of a data processing system are described. The data processing system includes a plurality of components; one or more buses coupled to the plurality of components, and a dynamic performance state manager unit coupled to the components. The dynamic performance state manager unit is configured to receive information about a first plurality of current states of components of the system. The dynamic performance state manager unit is configured to determine a second plurality of required system performance states for the components; and to determine a current system performance state based on the first plurality and the second plurality. | 2008-12-11 |
20080307246 | SYNCHRONIZING CONTENT BETWEEN CONTENT DIRECTORY SERVICE AND CONTROL POINT - In one embodiment, a method is performed at a control point (CP) in a network. An action is invoked to create a synchronization data structure on a media server that includes a content directory service (CDS) in the network, wherein the synchronization data structure includes a synchronization relationship describing a relationship between the CP and the CDS. Then an action is invoked to add synchronization pair information to one or more objects on the CDS. A change log is requested from the CDS. Then the change log is received from the CDS, wherein the change log contains information about changes to the one or more objects to which synchronization pair information for the CP was added. | 2008-12-11 |
20080307247 | Time Certifying Server, Reference Time Distributing Server, Time Certifying Method, Reference Time Distributing Method, Time Certifying Program, and Communication Protocol Program - An object is to perform time certification at a low cost while ensuring high precision and high reliability. In a time stamp server according to the present embodiment, a time is measured by the unit of, for example, 100 milliseconds, and a time stamp is issued by using the time. However, what is important is generally a date in a time stamp although it depends on a certification target. Therefore, it is thought that no adverse affect occurs substantially, even if a second hand is doctored. Accordingly, in the present embodiment, the time measured by the internal clock of the time stamp server is divided into a part regarding the units equal to or larger than the unit of minute (year, month, day, minute) and a part regarding the unit of second (including the units smaller than one second, such as millisecond), and the part regarding the units equal to or larger than the unit of minute is audited by an auditory office, whereas the part regarding the unit of second is synchronized with a time distributed from a time distributing office. That is, as to the part regarding the units equal to or larger than the unit of minute, the coincidence with the reference time is confirmed, whereas the part regarding the unit of second is corrected by using the time distributed from the time distributing office. | 2008-12-11 |
20080307248 | Cpu Clock Control Device, Cpu Clock Control Method, Cpu Clock Control Program, Recording Medium, and Transmission Medium - A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute the program is made equal to the extent that registered request for the execution time and allowable range are met. It is thus possible to determine the execution time of the program in such a manner that a necessary processing volume is made as equal as possible within the allowable range of the request for the execution time of the program, which enables clock control that suppresses a variation of the operating frequency of the CPU. Power consumption of the CPU can be thus reduced. | 2008-12-11 |
20080307249 | Digital mixing system with double arrangement for fail safe - A digital mixing system has a console having a display and an operator for transmitting and receiving a control signal, an engine having input channels and output channels for mixing a plurality of audio signals fed from the input channels while exchanging the control signal with the console and feeding the mixed audio signals to the output channels, and peripheral input and output units connected to the input and output channels of the engine, respectively. The console and the engine are located remotely from each other, and a cable connecting therebetween is duplicated for the purpose of fail safe. The engine may be installed in pair. If a main engine fails, a sub engine backs up instantly to continue the mixing operation. The console may be also prepared in pair for the purpose of fail safe. | 2008-12-11 |
20080307250 | MANAGING NETWORK ERRORS COMMUNICATED IN A MESSAGE TRANSACTION WITH ERROR INFORMATION USING A TROUBLESHOOTING AGENT - A method, system, and program for managing network errors communicated in a message transaction with error information using a troubleshooting agent. A network facilitates message transactions between a requester and a responder for facilitating web services. When a non-application specific error occurs in relation to a particular message transaction, such as a network error, a protocol layer assigns an error code and either the requester or responder encodes the error code in the body of an envelope added to the particular message transaction. In particular, the message transaction is an XML message with a Simple Object Access Protocol (SOAP) envelope encoded with the error code to which the XML message is then attached. The error encoded message transaction is forwarded to a troubleshooting agent. The troubleshooting agent facilitates resolution of the non-application specific error and returns a descriptive message indicating the resolution of the non-application specific error to at least one of the requester and the responder. | 2008-12-11 |
20080307251 | FUSE FARM REDUNDANCY METHOD AND SYSTEM - A system and method for making efficient use of fuse ROM redundancy to increase yield and security. Some embodiments provide a memory repair system including a non-volatile memory component and a controller coupled to the non-volatile memory component. The non-volatile memory component includes a plurality of memory locations. The plurality of memory locations includes a replacement memory location to replace a faulty memory location and a replacement indicia memory location to store replacement memory location indicia. The controller coupled to the non-volatile memory component reads replacement memory location indicia from the replacement indicia memory location, determines an address for the replacement memory location using the indicia, reads the replacement memory location, and transfers a data value contained in the replacement memory location to a second memory component to repair a defective memory location of the second memory component. | 2008-12-11 |
20080307252 | Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory - A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure. | 2008-12-11 |
20080307253 | Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory - A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure. | 2008-12-11 |
20080307254 | INFORMATION-PROCESSING EQUIPMENT AND SYSTEM THEREFOR - In cases where the system which performs service provision includes plural kinds of OS, the plural kinds of OS are operated simultaneously on one standby server provided with the virtual control unit. When a failure etc. occurred in the operation system server necessitates the system switchover from the operation system server to the standby server, the virtual control unit of the standby server distinguishes an operation system server in which the failure has occurred, and takes over the processing to the switching control unit on a suitable OS on the standby server. | 2008-12-11 |
20080307255 | FAILURE RECOVERY AND ERROR CORRECTION TECHNIQUES FOR DATA LOADING IN INFORMATION WAREHOUSES - A method of data loading for large information warehouses includes performing checkpointing concurrently with data loading into an information warehouse, the checkpointing ensuring consistency among multiple tables; and recovering from a failure in the data loading using the checkpointing. A method is also disclosed for performing versioning concurrently with data loading into an information warehouse. The versioning method enables processing undo and redo operations of the data loading between a later version and a previous version. Data load failure recovery is performed without starting a data load from the beginning but rather from a latest checkpoint for data loading at an information warehouse level using a checkpoint process characterized by a state transition diagram having a multiplicity of states; and tracking state transitions among the states using a system state table. | 2008-12-11 |