50th week of 2013 patent applcation highlights part 14 |
Patent application number | Title | Published |
20130328083 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first semiconductor layer, an active layer, a second semiconductor layer, a first optical symmetric layer, a metallic layer, and a second optical symmetric layer stacked in that sequence. A first effective refractive index n | 2013-12-12 |
20130328084 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first optical symmetric layer, a metallic layer, and a second optical symmetric layer stacked on the substrate in that sequence. A first electrode is electrically connected to the first semiconductor layer, and a second electrode is electrically connected to the second semiconductor layer. A first effective refractive index n | 2013-12-12 |
20130328085 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first semiconductor layer, an active layer, a second semiconductor layer, and a cermet layer stacked together. The active layer is on a surface of the first semiconductor layer. The second semiconductor layer is on a surface of the active layer away from the first semiconductor layer. The cermet layer is on a surface of the second semiconductor layer away from the first semiconductor layer. | 2013-12-12 |
20130328086 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, a buffer layer, a first semiconductor layer, an active layer, a second semiconductor layer, and a cermet layer. The active layer is on the first semiconductor layer. The second semiconductor layer is on the active layer. The cermet layer is on the second semiconductor layer. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer. | 2013-12-12 |
20130328087 | LIGHT EMITTING DIODE - A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, and a cermet layer. The active layer is on the first semiconductor layer. The second semiconductor layer is on the active layer. The cermet layer is on the second semiconductor layer. A first electrode covers entire surface of the first semiconductor layer away from the active layer. A second electrode is electrically connected to the second semiconductor layer. | 2013-12-12 |
20130328088 | LED Module and Lighting Apparatus - According to one embodiment, an LED module according to the embodiment is configured by an LED chip, a pair of wiring bodies, and sealing resin. The pair of wiring bodies are connected to both electrodes of the LED chip, respectively. The sealing resin is light-transmissive, and is provided so as to cover a top face and a base of the LED chip, and cover at least a part of the pair of wiring bodies. | 2013-12-12 |
20130328089 | LIGHT EMITTING DIODE FOR HARSH ENVIRONMENTS - A light emitting diode for harsh environments includes a substantially transparent substrate, a semiconductor layer deposited on a bottom surface of the substrate, several bonding pads, coupled to the semiconductor layer, formed on the bottom surface of the substrate, and a micro post, formed on each bonding pad, for electrically connecting the light emitting diode to a printed circuit board. An underfill layer may be provided between the bottom surface of the substrate and the top surface of the printed circuit board, to reduce water infiltration under the light emitting diode substrate. Additionally, a diffuser may be mounted to a top surface of the light emitting diode substrate to diffuse the light emitted through the top surface. | 2013-12-12 |
20130328090 | LIGHTING DEVICE - Provided is a lighting device, comprising: a light source module comprising: at least one light source disposed on a printed circuit board; and a resin layer disposed on the printed circuit board so that the light source is embedded; an indirect light emission unit which is formed in at least any one of one side and another side of the light source module, and which reflects light irradiated from the light source; and a diffusion plate having an upper surface formed on the light source module, and a side wall which is integrally formed with the upper surface and which is adhered onto an outer side surface of the indirect light emission unit, wherein a first separated space is formed between the light source module and the upper surface of the diffusion plate, whereby flexibility of the product itself can be secured, and durability and reliability of the product can be also improved while indirect light emission using a flare effect can be implemented. | 2013-12-12 |
20130328091 | LIGHT REFLECTING MEMBER FOR OPTICAL SEMICONDUCTOR, AND SUBSTRATE FOR MOUNTING OPTICAL SEMICONDUCTOR AND OPTICAL SEMICONDUCTOR DEVICE USING THE LIGHT REFLECTING MEMBER - The present invention relates to a light reflecting member for an optical semiconductor which makes it possible to manufacture a high-quality optical semiconductor device at a low cost, as well as a substrate for mounting an optical semiconductor and an optical semiconductor device using such a light reflecting member. | 2013-12-12 |
20130328092 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device is described, including a second conductive type semiconductor layer; an active layer over the second conductive type semiconductor layer; a first conductive type semiconductor layer over the active layer; a second electrode in a first region under the second conductive type semiconductor layer; a current blocking layer including a metal; and a first electrode over the first conductive type semiconductor layer. Further, the first electrode has at least one portion that vertically overlaps the current blocking layer. | 2013-12-12 |
20130328093 | THIN-FILM LED WITH P AND N CONTACTS ELECTRICALLY ISOLATED FROM THE SUBSTRATE - A thin-film light emitting diode includes an insulating substrate, a reflective metal electrode on the insulating substrate forming a current spreading layer, and an epitaxial structure on the electrode. | 2013-12-12 |
20130328094 | LIGHT EMITTING DEVICE AND LIGHING SYSTEM HAVING THE SAME - Provided is a light emitting device. The light emitting device includes a plurality of metal layers spaced from each other, a first insulation film having an opened area in which a portion of the plurality of metal layers is opened, the first insulation film being disposed around top surfaces of the plurality of metal layers, a light emitting chip disposed on at least one of the plurality of metal layers, the light emitting chip being electrically connected to the other metal layer, a resin layer disposed on the plurality of metal layers and the light emitting chip, and a first guide member formed of a non-metallic material, the first guide member being disposed on the first insulation film. | 2013-12-12 |
20130328095 | Ceramic Composite for Light Conversion, Method for Producing Same, and Light Emitting Device Including Same - A ceramic composite for light conversion, and method of producing same and a light emitting device including the same. The ceramic composite for light conversion of the present invention is a solidified body having a structure in which at least two oxide phases including a first phase and a second phase are continuously and three-dimensionally intertwined with one another, and characterized in that the first phase is a Y | 2013-12-12 |
20130328096 | Semiconductor Light Emitting Diodes with Crack-Tolerant Barrier Structures and Methods of Fabricating the Same - A light emitting device includes an epitaxial region, an insulating layer on the epitaxial region, a bond pad on the insulating layer, and a crack reducing feature in the insulating layer. The crack reducing feature is configured to reduce the propagation of cracks in the insulating layer to an outside surface of the insulating layer. Related methods are also disclosed. | 2013-12-12 |
20130328097 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A group III nitride semiconductor light-emitting element having a rectangular shape in a planar view, the element comprises an n-electrode connecting to an n-type layer and a p-electrode connecting to a p-type layer, on a same plane side; wherein the n-electrode has a n-wiring-shaped part that is wiring-shaped and extending along a first side of the rectangular shape; the p-electrode has a p-wiring-shaped part that is wiring-shaped and extending along the first side of the rectangular shape; when a distance that is between the n-wiring-shaped part and the p-wiring-shaped part is a, and a distance that is between the one side of the rectangular shape and at least one of the n-wiring-shaped part and the p-wiring-shaped part and that is nearest to the first side is b, the n-wiring-shaped part and the p-wiring-shaped part are arranged such that the distances a and b satisfy 1.65≦a/b≦7.00. | 2013-12-12 |
20130328098 | BUFFER LAYER STRUCTURE FOR LIGHT-EMITTING DIODE - A buffer layer structure for an LED is provided. The LED includes a P-type electrode, a permanent substrate, a binding layer, a buffer layer, a mirror layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type electrode that are stacked in sequence. The buffer layer is a composite material, and includes at least one first material and at least one second material that are alternately stacked. The first material and the second material are mutually diffused to generate gradient variation after the buffer layer is processed by a thermal treatment. Thus, an interface effect and thermal stress between difference interfaces are eliminated, and a channel for ion diffusion is blocked for enhancing light-emitting efficiency of the LED. | 2013-12-12 |
20130328099 | METHOD FOR PRODUCING LARGE LIGHTING WITH POWER LED - A method of packaging a power light emitting diode (LED). The method may include providing a printed circuit board (PCB) wherein first and second copper (Cu) thin films are formed on both faces of the PCB respectively, forming a single upper opening through an entire thickness of the first Cu thin film and an partial thickness of the PCB, forming a plurality of lower openings, each lower opening extending vertically from the upper opening to the second Cu thin film, forming solder pads on the first Cu thin film, filing a cream solder in the upper opening and the plurality of lower openings so as to be in-plane with the solder pads, mounting a power LED on the PCB so that lead frames of the LED are aligned with the solder pads and a heat-discharge region of the LED is aligned with the cream solder, and soldering the cream solder. | 2013-12-12 |
20130328100 | ENCAPSULATING SHEET, LIGHT EMITTING DIODE DEVICE, AND PRODUCING METHOD THEREOF - An encapsulating sheet includes an encapsulating resin layer and a barrier film layer formed at one side in a thickness direction of the encapsulating resin layer. | 2013-12-12 |
20130328101 | METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP, AND SUCH A SEMICONDUCTOR CHIP - A method of producing an optoelectronic semiconductor chip having a semiconductor layer stack based on a material system AlInGaP includes preparing a growth substrate having a silicon surface, arranging a compressively relaxed buffer layer stack on the growth substrate, and metamorphically, epitaxially growing the semiconductor layer stack on the buffer layer stack, the semiconductor layer stack having an active layer that generates radiation. | 2013-12-12 |
20130328102 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprising: a substrate; and an epitaxial stack including a first semiconductor layer having a first conductivity-type impurity, an active layer, and a second semiconductor layer having a second conductivity-type impurity formed in sequence on the substrate; a hollow component formed inside the active layer or the second semiconductor layer, wherein the layer with the hollow component is doped with an additional impurity. | 2013-12-12 |
20130328103 | METHOD AND APPARATUS FOR PROTECTION AND HIGH VOLTAGE ISOLATION OF LOW VOLTAGE COMMUNICATION INTERFACE TERMINALS - A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions. As a result, the protection device enables superior robustness and compact protection solutions for smart power applications. | 2013-12-12 |
20130328104 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed which has a high voltage isolation structure that is a RESURF structure, wherein it is possible to reduce a displacement current generated by dV/dt noise, and a method of manufacturing the semiconductor device. It is possible to increase a lateral resistance without changing the total amount of electric charges in the uppermost surface p-type diffusion layer by using an uppermost surface p-type diffusion layer configuring a double-RESURF structure being formed so that high concentration regions with a deep diffusion depth and low concentration regions with a shallow diffusion depth are alternately arranged adjacent to each other. As a result, it is possible to reduce a displacement current generated by dV/dt noise. | 2013-12-12 |
20130328105 | NARROW ACTIVE CELL IE TYPE TRENCH GATE IGBT AND A METHOD FOR MANUFACTURING A NARROW ACTIVE CELL IE TYPE TRENCH GATE IGBT - In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact. | 2013-12-12 |
20130328106 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer. The buffer region includes a plurality of semiconductor layers having different lattice constants, and there is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when a potential that is less than a potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region. | 2013-12-12 |
20130328107 | SEMICONDUCTOR DEVICE - A semiconductor device protects against concentration of electric current at a front end portion of one of the electrodes thereof. The semiconductor device includes a substrate, a compound semiconductor layer formed on the substrate and having a channel layer based on a hetero junction, a first main electrode formed on the compound semiconductor layer, a second main electrode formed on the compound semiconductor surrounding the first main electrode and having a linear region and an arc-shaped region, a control electrode formed on the compound semiconductor layer and disposed opposite to the first main electrode and the second main electrode, an electric current being made to flow between the first main electrode and the second main electrode, and an electric current limiting section formed between the first main electrode and the arc-shaped region of the second main electrode. | 2013-12-12 |
20130328108 | ULTRA-HIGH VOLTAGE SIGE HBT DEVICE AND MANUFACTURING METHOD OF THE SAME - An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N− collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N− collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N− collector region; an N+ collector region between the two field oxide regions and through the N− collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed. | 2013-12-12 |
20130328109 | STRUCTURES AND METHODS FOR ELECTRICALLY AND MECHANICALLY LINKED MONOLITHICALLY INTEGRATED TRANSISTOR AND MEMS/NEMS DEVICES - A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated; its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.) In one embodiment, devices according to the present invention were realized in 2?m thick SOI cross-wire beams, with a MoSi2 contact metallization for stress minimization and ohmic contact. In this embodiment, the pull-in voltage for the MEMS cantilever was 21V and the pinch-off voltage of the JFET was −19V. | 2013-12-12 |
20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 2013-12-12 |
20130328111 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 2013-12-12 |
20130328112 | SEMICONDUCTOR DEVICES HAVING IMPROVED GATE HEIGHT UNIFORMITY AND METHODS FOR FABRICATING SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench. | 2013-12-12 |
20130328113 | REGENERATIVE BUILDING BLOCK AND DIODE BRIDGE RECTIFIER AND METHODS - A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices. | 2013-12-12 |
20130328114 | Integrated Transistor and Anti-Fuse as Programming Element for a High-Voltage Integrated Circuit - A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. | 2013-12-12 |
20130328115 | Contact for High-K Metal Gate Device - An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure. | 2013-12-12 |
20130328116 | DRAM WITH A NANOWIRE ACCESS TRANSISTOR - A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure. | 2013-12-12 |
20130328117 | FLOATING GATE NON-VOLATILE MEMORY BIT CELL - A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain. | 2013-12-12 |
20130328118 | NON-VOLATILE MEMORY USING PYRAMIDAL NANOCRYSTALS AS ELECTRON STORAGE ELEMENTS - A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. | 2013-12-12 |
20130328119 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively. | 2013-12-12 |
20130328120 | SEMICONDUCTOR DEVICE - A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A protective film is formed so as to continuously cover a side surface and a bottom surface of the step. A field plate electrode connected with the p-electrode is formed on the protective film. When a distance from the pn junction interface to the surface of the protective film on the bottom surface of the step is defined as h (μm), a dielectric constant of the protective film is defined as ∈ | 2013-12-12 |
20130328121 | MOSFET WITH IMPROVED PERFORMANCE THROUGH INDUCED NET CHARGE REGION IN THICK BOTTOM INSULATOR - A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2013-12-12 |
20130328122 | SPLIT TRENCH-GATE MOSFET WITH INTEGRATED SCHOTTKY DIODE - A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode. | 2013-12-12 |
20130328123 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer. | 2013-12-12 |
20130328124 | GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL - A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics. | 2013-12-12 |
20130328125 | PROTECTION COMPONENT AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH THE SAME - An electrostatic discharge protection device includes a protection component and a component controller. The protection component includes a first and a second P-type wells which are disposed in an N-type deep well, a first N-type transistor which is formed in the N-type deep well and the first P-type well, and a second N-type transistor which is formed in the N-type deep well and the second P-type well. When an electrostatic pulse occurs at a first pad or a second pad, the component controller turns on one of the first and the second N-type transistors to discharge the electrostatic pulse. When a first and a second operating signals are supplied to the first and the second pads, the component controller turns off the first and the second N-type transistors according to the first and the second operating signals so that the protection component is incapable of generating the current path. | 2013-12-12 |
20130328126 | EPITAXIAL FORMATION OF SOURCE AND DRAIN REGIONS - Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues. | 2013-12-12 |
20130328127 | SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT - The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods. | 2013-12-12 |
20130328128 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer. | 2013-12-12 |
20130328129 | LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 2013-12-12 |
20130328130 | BIPOLAR TRANSISTOR IN BIPOLAR-CMOS TECHNOLOGY - A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process. | 2013-12-12 |
20130328131 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors - Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor. | 2013-12-12 |
20130328132 | POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR - A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions. | 2013-12-12 |
20130328133 | INTEGRATED CIRCUIT DEVICE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - Integrated circuit device with transistors having different threshold voltages and methods of forming the device are provided. The device may include the first, second and third transistors having threshold voltages different from each other. The first transistor may be free of a stacking fault and the second transistor may include a stacking fault. The concentration of the channel implant region of the third transistor may be different from the concentration of the channel implant region of the first transistor. | 2013-12-12 |
20130328134 | Method and Apparatus for Improving Gate Contact - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 2013-12-12 |
20130328135 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 2013-12-12 |
20130328136 | STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE - A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode. | 2013-12-12 |
20130328137 | MODIFIED HIGH-K GATE DIELECTRIC STACK - A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO | 2013-12-12 |
20130328138 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes. | 2013-12-12 |
20130328139 | MICROMACHINED MONOLITHIC 3-AXIS GYROSCOPE WITH SINGLE DRIVE - This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency. | 2013-12-12 |
20130328140 | VIBRATION ISOLATED MEMS STRUCTURES AND METHODS OF MANUFACTURE - A microstructure device has a microstructure (e.g., a circuit card assembly, a printed circuit board, etc.) defining a sensitive axis and one or more isolators configured and adapted to be compliant along the sensitive axis and to be rigid along one or more other axes. | 2013-12-12 |
20130328141 | HERMETIC PLASTIC MOLDED MEMS DEVICE PACKAGE AND METHOD OF FABRICATION - A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad ( | 2013-12-12 |
20130328142 | INTEGRATED CIRCUIT WITH PRESSURE SENSOR AND MANUFACTURING METHOD - Disclosed is an integrated circuit ( | 2013-12-12 |
20130328143 | Semiconductor Manufacturing and Semiconductor Device with semiconductor structure - Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted. | 2013-12-12 |
20130328144 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC APPARATUS - A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer. | 2013-12-12 |
20130328145 | Integrated Optical Receiver Architecture For High Speed Optical I/O Applications - An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond. | 2013-12-12 |
20130328146 | TRANSVERSELY-ILLUMINATED HIGH CURRENT PHOTOCONDUCTIVE SWITCHES WITH GEOMETRY-CONSTRAINED CONDUCTIVITY PATH - A photoconductive switch having a wide bandgap semiconductor material substrate between opposing electrodes, with one of the electrodes having an aperture or apertures at an electrode-substrate interface for transversely directing radiation therethrough from a radiation source into a triple junction region of the substrate, so as to geometrically constrain the conductivity path to within the triple junction region. | 2013-12-12 |
20130328147 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure. | 2013-12-12 |
20130328148 | COVER FOR IMAGE SENSOR ASSEMBLY WITH LIGHT ABSORBING LAYER AND ALIGNMENT FEATURES - An image sensor assembly includes an image sensor die attached adjacent to a cavity and a lower surface in a preformed package having substantially vertical surfaces extending from the lower surface to an upper surface of the package. The image sensor die provides the light receiving surface for capturing the image. A light absorbing layer is applied to a cover such that the light absorbing layer prevents light from falling on the substantially vertical surfaces of the preformed package without preventing the passage of light that falls on the light receiving surface of the image sensor die. The light absorbing layer includes openings that provide a line-of-sight view of two opposing corners of at least one of the light receiving surface and the image sensor die to facilitate placing the cover over the upper surface of the package in registry with the image sensor die. | 2013-12-12 |
20130328149 | WAVELENGTH CONVERSION-TYPE PHOTOVOLTAIC CELL SEALING MATERIAL AND PHOTOVOLTAIC CELL MODULE USING THE SAME - The present invention provides a wavelength conversion-type photovoltaic cell sealing material, the sealing material including at least one light emitting layer containing a group of spherical phosphors, the group of spherical phosphors having a ratio of a median value D | 2013-12-12 |
20130328150 | ADJUSTABLE AVALANCHE DIODE IN AN INTEGRATED CIRCUIT - An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm. | 2013-12-12 |
20130328151 | INTEGRATED CIRCUIT STRUCTURE, BACK SIDE ILLUMINATION IMAGE SENSOR AND INTEGRATED CIRCUIT PROCESS THEREOF - An integrated circuit structure or a back side illumination image sensor is provided, wherein the integrated circuit structure includes a bond pad and a metal structure located in a dielectric layer, wherein the bond pad and the metal structure have different materials, and the back side illumination image sensor includes an image sensor unit and an interconnect structure respectively located on both sides of a bond pad. Moreover, an integrated circuit process forming said integrated circuit structure or back side illumination image sensor is also provided. | 2013-12-12 |
20130328152 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A method for manufacturing a solid-state imaging device includes: forming pixels that receive incident light in a pixel array area of a substrate; forming pad electrodes in a peripheral area located around the pixel array area of the substrate; forming a carbon-based inorganic film on an upper surface of each of the pad electrodes including a connection surface electrically connected to an external component; forming a coated film that covers upper surfaces of the carbon-based inorganic films; and forming an opening above the connection surface of each of the pad electrodes to expose the connection surface. | 2013-12-12 |
20130328153 | ELECTRONIC-COMPONENT MOUNTING STRUCTURE - An electronic-component mounting structure includes an electronic component which includes a metal substrate, a semiconductor ceramic layer located on the metal substrate, a pair of split electrodes located on the semiconductor ceramic layer, and plating films located on the split electrodes and the metal substrate, and a mounting body on which lands to be connected to the respective split electrodes of the electronic component are provided. The position of a peripheral end portion of each land to be connected to the corresponding split electrode is located farther inside than the position of a peripheral end portion of the split electrode. In addition, a plane area of the land is smaller than that of the split electrode. | 2013-12-12 |
20130328154 | ELECTRONIC COMPONENT PACKAGE STRUCTURE - A thermistor includes a metal substrate, a semiconductor ceramic layer on the metal substrate, and a pair of split electrodes on the semiconductor layer. The semiconductor ceramic layer is formed by a solid-phase method. The metal substrate includes ceramic particles and is not interrupted in the direction of thickness by the ceramic particles or a pillar defined by a chain of the ceramic particles. Preferably, the metal substrate and the ceramic layer of the thermistor have a thickness of about 10 μm to about 80 μm and about 1 μm to about 10 μm, respectively. | 2013-12-12 |
20130328155 | GENERATION OF ADDITIONAL SHAPES ON A PHOTOMASK FOR A MULTIPLE EXPOSURE PROCESS - The disclosed aspects relate to controlling density of photomasks. One or more unprintable auxiliary patterns can be placed near a mask feature as well as onto a location of a feature of the main pattern. If a density is measured and is not within an acceptable density range, one or more printable auxiliary patterns can be replaced with unprintable auxiliary patterns and/or one or more unprintable auxiliary patterns can be replaced with printable auxiliary patterns. The disclosed aspects can be utilized to create a photomask and/or a semiconductor device, such as a large scale integrated circuit device, that comprises the photomask. | 2013-12-12 |
20130328156 | DESIGN SUPPORT METHOD, RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM AND SEMICONDUCTOR DEVICE - A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively. | 2013-12-12 |
20130328157 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 2013-12-12 |
20130328158 | SEMICONDUCTOR SEAL RING DESIGN FOR NOISE ISOLATION - A semiconductor structure includes a substrate layer and a conductive layer connected with the substrate layer. An active circuit is connected with the conductive layer. A seal ring is connected with the conductive layer and separated from the active circuit by an assembly isolation region. An electrical isolation region is positioned in the conductive layer and adjacent to the assembly isolation region, where the electrical isolation region extends to the substrate layer. | 2013-12-12 |
20130328159 | IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE - Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage. | 2013-12-12 |
20130328160 | SEMICONDUCTOR DEVICE - Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant. | 2013-12-12 |
20130328161 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 2013-12-12 |
20130328162 | HOMO-JUNCTION DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING - Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells. | 2013-12-12 |
20130328163 | INDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide inductor devices and fabrication methods. In one embodiment, an inductor device can include a first dielectric layer disposed on a semiconductor substrate; a first planar spiral wiring disposed on the first dielectric layer, and optionally one or more second planar spiral wirings disposed over the first planar spiral wiring. Each of the first and the optional second planar spiral wirings can include a first spiral metal wiring and a second spiral metal wiring connected to the first spiral metal wiring. The second spiral metal wiring can include at least two sub-metal-lines isolated with one another. | 2013-12-12 |
20130328164 | INDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel. | 2013-12-12 |
20130328165 | MICROFABRICATED MAGNETIC DEVICES AND ASSOCIATED METHODS - A magnetic device includes a semiconductor wafer, a spiral winding, and a magnetic core. The spiral winding forms a plurality of turns and is disposed in a channel of the semiconductor wafer. The magnetic core is disposed at least partially in the channel of the semiconductor wafer and at least partially surrounds the plurality of turns. A width of the spiral winding optionally varies such that a respective width of an edge turn is smaller than a respective width of a middle turn. The channel is formed, for example, by a method including (1) patterning a resist layer on the semiconductor wafer using a mask including angularly extending compensation features, and (2) anistropically etching the semiconductor wafer to form the channel. | 2013-12-12 |
20130328166 | Semiconductor Device and Method of Manufacture Thereof - A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip. | 2013-12-12 |
20130328167 | SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR - A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode. | 2013-12-12 |
20130328168 | Manufacturable High-k dram mim capacitor structure - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<2nm) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material. | 2013-12-12 |
20130328169 | RESISTIVE DEVICE AND METHOD OF MANUFACTURING THE SAME - This disclosure is related to a resistive device including a silicide pattern. A resistive device can include a substrate, and a first resistive layer disposed above the substrate. The resistive device can include a second resistive layer disposed on the first resistive layer and has a resistance different from a resistance of the first resistive layer. The resistive device can include a third resistive layer disposed on a first portion of the first resistive layer such that a second portion of the first resistive layer is disposed between the third resistive layer and the second resistive layer. The resistive layer can also include a conductive plug electrically connected to the third resistive layer. | 2013-12-12 |
20130328170 | SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well. | 2013-12-12 |
20130328171 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first semiconductor layer, an active layer, a second semiconductor layer, a metallic plasma generating layer, and a first optical symmetric layer stacked in series. The first semiconductor layer, the active layer, and the second semiconductor layer constitute a source layer. A refractive index difference between the source layer and the first optical symmetric layer is less than or equal to 0.3. | 2013-12-12 |
20130328172 | WAFER-LEVEL FLIP CHIP DEVICE PACKAGES AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon. | 2013-12-12 |
20130328173 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE - A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved. | 2013-12-12 |
20130328174 | Edge Protection of Bonded Wafers During Wafer Thinning - A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers. | 2013-12-12 |
20130328175 | METHOD FOR THE HYDROGEN PASSIVATION OF SEMICONDUCTOR LAYERS - The present invention relates to a method for the hydrogen passivation of semiconductor layers, wherein the passivation is effected by using an arc plasma source, to the passivated semiconductor layers produced according to the method, and to the use thereof. | 2013-12-12 |
20130328176 | EMI-SHIELDED SEMICONDUCTOR DEVICES AND METHODS OF MAKING - A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield. | 2013-12-12 |
20130328177 | STACK SEMICONDUCTOR PACKAGE AND MANUFACTURING THE SAME - To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold. | 2013-12-12 |
20130328178 | SHIELDING DEVICE - One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit. | 2013-12-12 |
20130328179 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone. | 2013-12-12 |
20130328180 | PACKAGED SEMICONDUCTOR DEVICE WITH AN EXPOSED METAL TOP SURFACE - In a manufacturing technique for packaged semiconductor devices, a pre-form of a packaged semiconductor device is formed by a molding process which encapsulates the semiconductor device and its associated heat transfer component in a passivating material presenting a surface. The surface is then processed to at least remove excess passivating material and expose the heat transfer component. The processing may further remove a portion of the heat transfer component. The removal process may, for example, utilize a grinding and/or polishing process. The process may be controlled so as to expose or form a heat transfer surface of desired shape and size. | 2013-12-12 |
20130328181 | ELECTRONIC SYSTEM WITH A COMPOSITE SUBSTRATE - A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame. | 2013-12-12 |
20130328182 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion. | 2013-12-12 |