50th week of 2012 patent applcation highlights part 57 |
Patent application number | Title | Published |
20120317362 | SYSTEMS, METHODS, AND DEVICES FOR CACHE BLOCK COHERENCE - Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence. | 2012-12-13 |
20120317363 | Memory Caching for Browser Processes - There is disclosed a method in which a process is initiated to handle a set of information, which includes one or more resources. In the method the set of information is examined to determine whether the set of information includes a resource stored as a shareable cache element in a memory. If the determination indicates that the set of information includes a resource stored as a shareable cache element, the shareable cache element is used as the resource of the set of information. | 2012-12-13 |
20120317364 | CACHE PREFETCHING FROM NON-UNIFORM MEMORIES - An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective performance characteristics. Each memory stores a respective subset of system memory data. The apparatus includes caching logic configured to determine a portion of the system memory to prefetch into the data cache. The caching logic determines the portion to prefetch based on one or more of the respective performance characteristics of the system memory that stores the portion of data. | 2012-12-13 |
20120317365 | SYSTEM AND METHOD TO BUFFER DATA - A data storage device includes a controller, a non-volatile memory, and a buffer accessible to the controller. The buffer is configured to store data retrieved from the non-volatile memory to be accessible to a host device in response to receiving from the host device one or more requests for read access to the non-volatile memory while the data storage device is operatively coupled to the host device. The controller is configured to read an indicator of cached data in response to receiving a request for read access to the non-volatile memory. The request includes a data identifier. In response to the indicator of cached data not indicating that data corresponding to the data identifier is in the buffer, the controller is configured to retrieve data corresponding to the data identifier as well as additional data from the non-volatile memory and to write the data corresponding to the data identifier and the additional data to the buffer. The controller is configured to update the indicator of cached data in response to retrieved data from the non-volatile memory being written to the buffer. | 2012-12-13 |
20120317366 | COMPUTER SYSTEM MANAGEMENT APPARATUS AND MANAGEMENT METHOD - The present invention measures an actual utilization frequency of data and controls a location of this data in a storage apparatus in a case where a host computer makes joint use of a storage apparatus and a cache apparatus. A portion of data used by an application program | 2012-12-13 |
20120317367 | WRITING DATA TO SYSTEM MEMORY IN A DATA PROCESSING SYSTEM - A state indicator associated with a cache line is stored, wherein the cache line is one of a plurality of cache lines each associated with a corresponding unique section of a region of system memory. The state indicator comprises a dirty indication indicating that the cache line is a candidate for writing data stored in the cache line to the associated section of the region of system memory. The state indicator is one of a plurality of state indicators each associated with a corresponding cache line. For the region of system memory, a number of the plurality of state indicators that comprises the dirty indication is determined, and if a threshold is exceeded, data stored in a selected cache line is written to the associated section of the region of system memory, and a clean indication is stored in the state indicator corresponding to the cache line. | 2012-12-13 |
20120317368 | Memory interface control - A memory interface apparatus | 2012-12-13 |
20120317369 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 2012-12-13 |
20120317370 | CACHE STATE MANAGEMENT ON A MOBILE DEVICE TO PRESERVE USER EXPERIENCE - Systems and methods for cache state management to preserve user experience with a mobile application on a mobile device while conserving resources in a wireless network are disclosed. In one embodiment, the method can include, for example, storing content from a content server as cached elements in a local cache on the mobile device and in response to receiving polling requests to contact the content server, retrieving the cached elements from the local cache to respond to the polling requests made at the mobile device, and/or using state information associated with the cached elements to provide the cached elements as responses to the polling requests such that user experience is preserved. | 2012-12-13 |
20120317371 | Usage Aware NUMA Process Scheduling - Processes may be assigned to specific processors when memory objects consumed by the processes are located in memory banks closely associated with the processors. When assigning processes to threads operating in a multiple processor NUMA architecture system, an analysis of the memory objects accessed by a process may identify processor or group of processors that may minimize the memory access time of the process. The selection may take into account the connections between memory banks and processors to identify the shortest communication path between the memory objects and the process. The processes may be pre-identified as functional processes that make little or no changes to memory objects other than information passed to or from the processes. | 2012-12-13 |
20120317372 | Efficient Communication of Producer/Consumer Buffer Status - A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel. | 2012-12-13 |
20120317373 | STORAGE APPARATUS AND METHOD OF CONTROLLING STORAGE APPARATUS - Efficient data processing is implemented by using the functions of an external storage apparatus which is connected to the virtual storage apparatus. | 2012-12-13 |
20120317374 | SRAM Multiplexing Apparatus - An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer. | 2012-12-13 |
20120317375 | STORE STORAGE CLASS MEMORY INFORMATION COMMAND - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317376 | ROW BUFFER REGISTER FILE - A memory controller of a device stores data from each of a plurality of row buffers of a multiple-bank memory device in a corresponding entry of a row buffer register file (RBRF) provided in a logic/interface layer of the memory device. The memory controller serves a first memory request from an entry in the RBRF responsive to determining that the entry stores data from a first row buffer associated with the first memory request. | 2012-12-13 |
20120317377 | DUAL FLASH TRANSLATION LAYER - A method for operating a memory includes receiving memory access commands associated with respective target logical addresses, for execution in a memory. The target logical addresses are translated into respective intermediate logical addresses, in accordance with a first mapping having a first granularity of a first data unit size. The intermediate logical addresses are translated into respective physical storage locations in the memory, in accordance with a second mapping having a second granularity of a second data unit size, larger than the first data unit size. The memory access commands are executed in the memory in accordance with the respective physical storage locations. | 2012-12-13 |
20120317378 | INTERLEAVING DEVICE AND INTERLEAVING METHOD - Disclosed are an interleaving device and an interleaving method which shorten processing time for channel interleaving. A CQI memory writing unit ( | 2012-12-13 |
20120317379 | STORAGE ARCHITECTURE FOR BACKUP APPLICATION - Aspects of the subject matter described herein relate to a storage architecture. In aspects, an address provided by a data source is translated into a logical storage address of virtual storage. This logical storage address is translated into an identifier that may be used to store data on or retrieve data from a storage system. The address space of the virtual storage is divided into chunks that may be streamed to the storage system. | 2012-12-13 |
20120317380 | DEVICE AND METHOD FOR A HALF-RATE CLOCK ELASTICITY FIFO - A device and method for processing an incoming data stream in a half-rate clock elasticity first in first out (FIFO) are disclosed. In one embodiment, two data blocks are written substantially simultaneously to two locations in the elasticity FIFO specified by respective two write pointers in a write clock cycle of a write clock. Further, two data blocks are read substantially simultaneously from two consecutive or non-consecutive locations in the elasticity FIFO specified by two read pointers in a read clock cycle of a read clock. The two read pointers can independently adjust locations to read in the plurality of locations based on a type of the data blocks in the elasticity FIFO and a predetermined elasticity FIFO threshold level in the read clock cycle to maintain the elasticity FIFO level at predetermined elasticity FIFO threshold level to achieve a constant output rate. | 2012-12-13 |
20120317381 | EFFICIENT DATA STORAGE SYSTEM - A system and method are disclosed for providing efficient data storage. A plurality of data segments is received in a data stream. The system preliminarily checks in a memory having a relatively low latency whether one of the plurality of data segments may have been stored previously in a data segment repository. The memory having the relatively low latency stores data segment information. In the event that the preliminary check determines that one of the plurality of data segments may have been stored in the data segment repository, a memory having a relatively higher latency is checked to determine whether the data segment has been stored previously in the data segment repository. | 2012-12-13 |
20120317382 | APPARATUS AND METHOD FOR IMPROVED DATA RESTORE IN A MEMORY SYSTEM - A memory module interfaces with a host system as a Dual Inline Memory Module (DIMM). The memory module includes a volatile memory and a nonvolatile memory, and provides a DIMM module interface to the volatile memory. A peripheral I/O bus interfaces to the nonvolatile memory, the peripheral I/O bus interface also interfaces to control logic of the memory module to initiate data backup from the volatile to the nonvolatile memory. | 2012-12-13 |
20120317383 | FAST COPY USING FILE SYSTEM BLOCK MAPPINGS - Multiple target blocks are allocated on a first storage device to store a target object. The target blocks are arranged to be in a one-to-one correspondence with multiple source blocks of a source object. The target blocks are set to a non-populated state, and target blocks in the non-populated state are populated with data from corresponding source blocks. While the target blocks are being populated, if a request is received to retrieve data from one of the target blocks that is in the non-populated state, then the one of the target blocks is populated with the data from the corresponding source block and set to a populated state. | 2012-12-13 |
20120317384 | DATA STORAGE METHOD - There is provided a method for storing data in a database comprising a first and a second memory. The method comprises reading a first page of data from the second memory, modifying at least part of the data read from said first page with the data to be stored in said database, writing the modified data to a second page of data in the first memory, and copying the second page from the first memory to the second memory. The data in the second page are sequentially ordered based upon the order in which the data were modified. | 2012-12-13 |
20120317385 | MOVING BLOCKS OF DATA BETWEEN MAIN MEMORY AND STORAGE CLASS MEMORY - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317386 | CLEARING BLOCKS OF STORAGE CLASS MEMORY - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317387 | FAST COPY USING FILE SYSTEM BLOCK MAPPINGS - Multiple target blocks on a first storage device are allocated to store a target object. The target blocks are arranged to be in a one-to-one correspondence with multiple source blocks of a source object. The target blocks are set to a non-populated state, and target blocks in the non-populated state are populated with data from corresponding source blocks. While the target blocks are being populated, if a request is received to retrieve data from one of the target blocks that is in the non-populated state, then the one of the target blocks is populated with the data from the corresponding source block and set to a populated state. | 2012-12-13 |
20120317388 | CONFIGURE STORAGE CLASS MEMORY COMMAND - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317389 | Allocating Heaps in NUMA Systems - Processes may be assigned heap memory within locally accessible memory banks in a multiple processor NUMA architecture system. A process scheduler may deploy a process on a specific processor and may assign the process heap memory from a memory bank associated with the selected processor. The process may be a functional process that may not change state of other memory objects, other than the input or output memory objects defined in the functional process. | 2012-12-13 |
20120317390 | FIRMWARE MANAGEMENT OF STORAGE CLASS MEMORY - A computer program product is provided and includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for detecting connections of two or more input/output (I/O) adapters, each of the two or more I/O adapters having one or more solid state devices (SSDs) connected thereto, and presenting a storage class memory address space for all of the connected SSDs that is independent of connections and disconnections between each of the one or more SSDs and each of the two or more I/O adapters and the processing unit. | 2012-12-13 |
20120317391 | RELEASING BLOCKS OF STORAGE CLASS MEMORY - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317392 | CHAINING MOVE SPECIFICATION BLOCKS - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317393 | DATA RETURNED RESPONSIVE TO EXECUTING A START SUBCHANNEL INSTRUCTION - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317394 | TRANSFORMING ADDRESSING ALIGNMENT DURING CODE GENERATION - The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment. | 2012-12-13 |
20120317395 | LOW LATENCY REPLICATION TECHNIQUES WITH CONTENT ADDRESSABLE STORAGE - A CAS data storage method and apparatus comprising: receiving input data including a succession of data items with corresponding logical addresses at a source CAS data storage space for storage therein and for replication at a destination CAS data storage space, generating a hash key for each data item at the source storage space, comparing respective hash keys with hash keys stored at a hash key storage table, to determine whether respective further data items are already present at the destination storage device; transferring respective data items to the destination storage space if no match is made to a hash key stored at the hash key storage table, but not transferring respective further data items if a match is made to a hash key stored at the hash key storage table, thereby transferring to the destination storage space only unique data items. | 2012-12-13 |
20120317396 | COMPUTERS AND MICROCHIPS WITH A PORTION PROTECTED BY AN INTERNAL HARDWARE FIREWALLS - This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network | 2012-12-13 |
20120317397 | APPARATUS, METHOD, SYSTEM AND EXECUTABLE MODULE FOR CONFIGURATION AND OPERATION OF ADAPTIVE INTEGRATED CIRCUITRY HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes. | 2012-12-13 |
20120317398 | METHOD FOR REDUCING BUFFER CAPACITY IN A PIPELINE PROCESSOR - A method to reduce buffer capacity in a processor includes giving the data packets admittance to the processor through at least one interface, storing the data packets in at least one input buffer, and using a packet rate shaper outside of a processing pipeline to control flow of the data packets to the pipeline before the data packets enter the pipeline. First and second data packets are given admittance to the pipeline in dependence on cost information per packet that is dependent upon an expected time period of residence of the first data packet in the pipeline. Cost information dependent upon an expected time period of residence of the second data packet in the pipeline differs from said cost information dependent upon the expected time period of residence of the first data packet in the pipeline. | 2012-12-13 |
20120317399 | Performing A Local Reduction Operation On A Parallel Computer - A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an input buffer. Copying, in interleaved chunks by the reduction processing cores, contents of the reduction processing cores' input buffers to an interleaved buffer in shared memory; copying, by one of the reduction processing cores, contents of the network write processing core's input buffer to shared memory; copying, by another of the reduction processing cores, contents of the network read processing core's input buffer to shared memory; and locally reducing in parallel by the reduction processing cores: the contents of the reduction processing core's input buffer; every other interleaved chunk of the interleaved buffer; the copied contents of the network write processing core's input buffer; and the copied contents of the network read processing core's input buffer. | 2012-12-13 |
20120317400 | SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS - Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results. | 2012-12-13 |
20120317401 | Load/Move Duplicate Instructions for a Processor - A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register. | 2012-12-13 |
20120317402 | EXECUTING A START OPERATOR MESSAGE COMMAND - A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands. | 2012-12-13 |
20120317403 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND INTERRUPT METHOD - A multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core. | 2012-12-13 |
20120317404 | Firmware Flashing Method and Related Computer System - A firmware flashing method for a computer system is disclosed. The firmware flashing method comprises establishing a list, wherein the list comprise a plurality of identities individually corresponding to a plurality of firmwares, checking a plurality devices of the computer system and obtaining corresponding identities of the plurality of devices of the computer system, determining whether the corresponding identities of the plurality of devices of the computer system exist in the list, selecting corresponding firmwares of the plurality of devices of the computer system when the corresponding identities of the plurality of devices of the computer system exist in the list, and merging the corresponding firmwares of the plurality of devices of the computer system and writing the corresponding firmwares of the plurality of devices of the computer system in a memory. | 2012-12-13 |
20120317405 | METHOD OF OPERATING A HETEROGENEOUS COMPUTER SYSTEM - A method of operating a heterogeneous computer system for executing tasks of software that has at least one performance processor, a processor supporting logic, and a hypervisor processor. The method either i) boots up the hypervisor processor only; or ii) boots up the at least one performance processor after the hypervisor processor; or iii) boots up the at least one performance processor only; or iv) boots up the hypervisor processor after the at least one performance processor. The hypervisor processor executes tasks that the hypervisor processor has sufficient processing power to handle and puts the at least one performance processor to power-conserving state. The hypervisor processor brings the at least one performance processor out of power-conserving state to execute tasks that the hypervisor processor has insufficient processing power to handle. The at least one performance and hypervisor processors simultaneously execute tasks that require combined processing power of all processors. | 2012-12-13 |
20120317406 | FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM - The subject technology relates to a flash storage system for accessing a boot program for a computing system, the flash storage system comprising a flash storage, a random access memory and a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory. In certain aspects, the flash control is further configured to generate a ready signal indicating the boot program is accessible from the random access memory. Computing systems and methods are also provided. | 2012-12-13 |
20120317407 | APPARATUS AND METHOD FOR PERFORMING A REBALANCE OF RESOURCES FOR ONE OR MORE DEVICES AT BOOT TIME - An apparatus and a method for performing a resource rebalance during a boot operation of a computer is provided. The apparatus includes a resource manager that is coupled to a plurality of devices. The resource manager is configured to receive a signal indicative of a desired set of requested resources from each of the plurality of devices and to determine that a first child device requires more resources than an amount previously assigned thereto. The resource manager is configured to locate a lowest common parent device to the first child device, which forms a lowest common subtree and to determine a resource range and to calculate a resource requirement request for the lowest common subtree. The resource manager is further configured to compare the resource requirement to the resource range to determine if a first range of resources is adequate to satisfy a second range of requested resources. | 2012-12-13 |
20120317408 | Method and Apparatus for Changing an Operational Characteristic of a Device in Order to Adjust the Power Consumption Level - An apparatus for changing an operational characteristic of a device based at least in part on a user input in order to adjust a power consumption level of the device may include a display for displaying a power consumption indicator corresponding to the power consumption level of the device. The power consumption level may be calculated by a power consumption calculator. A touch interface may receive the user input configured to adjust the power consumption level of the device. An operational characteristic changer may thereby change the operational characteristic. The user input may manipulate the power consumption indicator to adjust the power consumption level to a desired power consumption level. A corresponding method and computer program product are also provided. | 2012-12-13 |
20120317409 | Mobile Printing - A method of printing comprising, at an imaging device, receiving a print-by-reference print request and an encryption key from a mobile device, transmitting the print-by-reference print request and the encryption key to a print service, receiving encrypted print content from the print service, receiving a decryption key from the mobile device, decrypting the encrypted print content, creating decrypted print content, and printing the decrypted print content. A method of printing content requested from a mobile device, comprising receiving a print request and encrypted print content, receiving a decryption key from the mobile device, decrypting the encrypted print content, and printing the decrypted print content. | 2012-12-13 |
20120317410 | PROTECTING DATA FROM DATA LEAKAGE OR MISUSE WHILE SUPPORTING MULTIPLE CHANNELS AND PHYSICAL INTERFACES - A system and method for two devices that communicate via a network, wherein at least one of the devices is a touch sensitive device, the two devices storing a common cryptographic key that enables all communications via the network to be encrypted. | 2012-12-13 |
20120317411 | SYSTEM AND METHOD FOR ESTABLISHING A VIRTUAL PRIVATE NETWORK - A system and method for establishing a virtual private network (VPN) between a client and a private data communication network. An encrypted data communication session, such as a-Secure Sockets Layer (SSL) data communication session, is established between a gateway and the client over a public data communication network. The gateway then sends a programming component to the client for automatic installation and execution thereon. The programming component operates to intercept communications from client applications destined for resources on the private data communication network and to send the intercepted communications to the gateway via the encrypted data communication session instead of to the resources on the private data communication network. | 2012-12-13 |
20120317412 | IMPLICITLY CERTIFIED DIGITAL SIGNATURES - Methods, systems, and computer programs for using an implicit certificate are disclosed. In some aspects, a message and an implicit certificate are accessed. The implicit certificate is associated with an entity. A modified message is generated by combining the message with a value based on the implicit certificate. A digital signature can be generated based on the modified message and transmitted to a recipient. In some aspects, a digital signature from an entity and a message to be verified based on the digital signature are accessed. An implicit certificate associated with the entity is accessed. A modified message is generated by combining the message with a value based on the implicit certificate. The message is verified based on the digital signature and the modified message. | 2012-12-13 |
20120317413 | DETECTION OF ENCRYPTED PACKET STREAMS USING A TIMER - Methods, systems, and devices are disclosed for detecting encrypted Internet Protocol packet streams. The type of data within an encrypted stream of packets is inferred using an observable parameter. The observable parameter is observable despite encryption obscuring the contents of the encrypted stream of packets. A timer is established that maintains settings despite changes in the type of inferred data. | 2012-12-13 |
20120317414 | METHOD AND SYSTEM FOR SECURING DOCUMENTS ON A REMOTE SHARED STORAGE RESOURCE - This invention discloses a novel system and method for displaying electronic documents on remote devices and enabling collaborative editing in conjunction with a content management system where the documents that are shared are securely encrypted on the system in a manner that avoids a single point of failure in the security. | 2012-12-13 |
20120317415 | Method, apparatus, terminal and system for channel encryption - The disclosure discloses a method, an apparatus, a terminal and a system for channel encryption. The method includes that: a relay server receives a channel encryption request from a client, and acquires encrypted information, client information and a locally stored channel Extensible Markup Language (XML) file of the client from the channel encryption request (S | 2012-12-13 |
20120317416 | Imparting Real-Time Priority-Based Network Communications In An Encrypted Communication Session - This specification describes technologies relating to imparting real-time priority-based network communications in an encrypted session. In general, aspects of the subject matter described can be embodied in methods that include establishing, based on cryptographic information in a reserved, random-data portion of a handshake communication, a session, receiving parameter values relating to a sub media stream, included in a header of a network communication, storing the parameter values, obtaining state information and a data payload included in a second network communication, identifying, from the state information, a purpose of the second network communication, and whether a header of the second network communication includes one or more new values corresponding to one or more of the parameters, updating one or more of the stored values based on the one or more new values, and processing the data payload based on the identified purpose and the stored parameter values. | 2012-12-13 |
20120317417 | METHOD OF GENERATION OF A SECRET KEY FOR A WIRELESS COMMUNICATION SYSTEM - The present invention concerns a method of generation of a secret key, shared between a first terminal and a second terminal. The key is generated from the impulse response of the transmission channel separating the two terminals. A first message representative of the impulse response estimated by the first terminal is transmitted to the second terminal. This message is encoded using a channel encoding and punctured at a rate which prevents any decoding if additional information is missing. The second terminal combines this first message with at least a part of a second message representative of the impulse response estimated by the second terminal in order to attempt to decode the first message. If the decoding is successful the secret key is generated by the second terminal from the first message thus decoded. | 2012-12-13 |
20120317418 | System and Method for Extracting Device Uniqueness to Assign a License to the Device - An information handling system includes a device, a controller, and a license manager subsystem. The controller is configured to determine whether the device has a license assigned and to extract a unique identification for the device in response to a request for information about the device. The license manager subsystem is configured to send the request for information about the device to the controller, to send the unique identification for the device to a license server as a request for the license for the device, to receive the license from the license server, and to assign the license to the device when the license is received. | 2012-12-13 |
20120317419 | SYSTEM FOR CONTROLLING THE DISTRIBUTION AND USE OF RENDERED DIGITAL WORKS THROUGH WATERMARKING - Method, apparatus, and media for embedding a watermark in digital content. An exemplary method comprises receiving digital content in an encrypted form, receiving a decryption key associated with the digital content, receiving permitted use information specifying conditions under which the digital content is permitted to be rendered and indicating that a watermark is to be embedded in a rendered copy of the digital content, determining whether the conditions are satisfied, and rendering the digital content if the conditions are satisfied based on the determining, the rendering including generating a watermark based on the permitted use information and creating a rendered copy of the digital content having the watermark embedded therein. | 2012-12-13 |
20120317420 | ELECTRONIC SIGNATURE DEVICE AND ELECTRONIC SIGNATURE METHOD - An electronic signature device includes a processor configured to internally execute signature generation processing of generating an electronic signature for a digital data string; and an output unit configured to output the digital data string and the generated electronic signature. | 2012-12-13 |
20120317421 | Fingerprinting Executable Code - Executable code may be fingerprinted by inserting NOP codes into the executable code in a pattern that may reflect a fingerprint. The NOP codes may be single instructions or groups of instructions that perform no operation. A dictionary of NOP codes and their corresponding portion of a fingerprint may be used to create a series of NOP codes which may be embedded into executable code. The fingerprinted executable code may be fully executable and the presence of the NOP codes may not be readily identifiable. The fingerprinting mechanism may be used to authenticate executable code in various scenarios. | 2012-12-13 |
20120317422 | Method, apparatus and system for acquiring service by portable device - The disclosure provides a method, an apparatus and a system for acquiring a service by a portable device, in order to solve the problem that the security of the user information saved in the portable device is affected as the portable device uses an illegal User Interface (UI) on a Personnel Computer (PC) in the related art. The method includes: the portable device receives the data information of each slice computed by the UI according to the first algorithm in the UI itself and identification information of each slice saved, matches the received data information of each slice with the corresponding data information of each slice saved in the portable device itself, and verifies whether the UI is legal according to the matching result. When using a UI, the portable device sends slice information of a file to the UI to verify the legality of the UI, and does not acquire the service through the UI until the verification is passed, so as to prevent the portable device from using an illegal UI and ensure the security of the user information saved in the portable device. | 2012-12-13 |
20120317423 | Memory randomization for protection against side channel attacks - Side channel attacks against a computing device are prevented by combinations of scrambling data to be stored in memory and scrambling the memory addresses of the data using software routines to execute scrambling and descrambling functions. Encrypted versions of variables, data and lookup tables, commonly employed in cryptographic algorithms, are thus dispersed into pseudorandom locations. Data and cryptographic primitives that require data-dependent memory accesses are thus shielded from attacks that could reveal memory access patterns and compromise cryptographic keys. | 2012-12-13 |
20120317424 | Switching between unsecure system software and secure system software - Unsecure system software and secure system software on the same computer system is switched between. A computer system includes one or more processors, which may not have any built-in security features, memory, and firmware. The memory stores secure system software and unsecure system software. In response to receiving a user signal, the firmware switches from the unsecure system software running on the processors to the secure system software running on the processors (and back again). While the unsecure system software is running, the secure system software is protected from tampering by the unsecure system software. | 2012-12-13 |
20120317425 | POWER SUPPLY CONTROL SYSTEM AND METHOD - A remote computer can be used to control power supply devices corresponding to baseboard management controllers (BMCs) of cloud servers of a data center. The remote computer writes parameters into the BMC of the remote computer. The remote computer obtains information from each of the BMCs of the cloud servers. The remote computer sends a command every time interval to each of the BMCs of the cloud servers in a sequence to start the power supply devices corresponding to each of the BMCs of the cloud servers according to the obtained information. | 2012-12-13 |
20120317426 | DISTRIBUTED ANTENNA SYSTEM USING POWER-OVER-ETHERNET - A system is provided for adjusting power provided to a device. The system can include power sourcing equipment and a sub-system. The power sourcing equipment can provide power to a powered device via a channel. The sub-system can determine an amount by which to increase the power based on a resistance of the channel. The power sourcing equipment or the powered device can adjust the power (or load) responsive to a command from the sub-system. The sub-system can include a measurement device and a processor. The measurement device can measure an output voltage of the power sourcing equipment, an input voltage of the powered device, and a current on the channel. The processor can determine the resistance of the channel based on the output voltage, the input voltage, and the current. The processor can output a command specifying an increase or decrease in power supplied by the power sourcing equipment. | 2012-12-13 |
20120317427 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 2012-12-13 |
20120317428 | METHOD OF REMOTELY CONTROLLING POWER DISTRIBUTION UNITS - A method of remotely controlling power distribution units enables the power distribution units to automatically transmit messages to a server once connected to the server via a network. When a user logs into a server and requests to remotely control the associated power distribution units, the user only needs to enter the serial numbers or identification data thereof. The server then automatically searches for all power distribution units owned by the user, and provides a group management interface. The user can then group the power distribution units according to their locations or their properties in order to control the on and off thereof. Without knowing the IP addresses of the power distribution units, the user can readily control the power distribution units at different locations remotely. | 2012-12-13 |
20120317429 | GREEN COMPUTING HETEROGENEOUS COMPUTER SYSTEM - A green computing heterogeneous computer system for executing software has at least one performance processor, a processor supporting logic supporting the at least one performance processor for executing tasks of the software, and a hypervisor processor that consumes less power than the at least one performance processor. Supported by the processor supporting logic, the hypervisor processor executes tasks of the software that the hypervisor processor has sufficient processing power to handle and puts the at least one performance processor to a power-conserving state. The hypervisor processor brings the at least one performance processor out of idle state to execute tasks of the software that the hypervisor processor has insufficient processing power to handle. The at least one performance and hypervisor processors simultaneously execute tasks of the software that require combined processing power of all processors. | 2012-12-13 |
20120317430 | POWER MANAGEMENT IN A DATA-CAPABLE STRAPBAND - Embodiments of the invention relates generally to electrical and electronic hardware, computer software, wired and wireless network communications, and computing devices, and more specifically to structures and techniques for managing power generation, power consumption, and other power-related functions in a data-capable strapband. Embodiments relate to a band including sensors, a controller coupled to the sensors, an energy storage device, a connector configured to receive power and control signals, and a power manager. The power manager includes at least a transitory power manager configured to manage power consumption of the band during a first power mode and a second mode. The band can be configured as a wearable communications device and sensor platform. | 2012-12-13 |
20120317431 | SYSTEM AND METHOD FOR POWER REDUCTION BY SEQUESTERING AT LEAST ONE DEVICE OR PARTITION IN A PLATFORM FROM OPERATING SYSTEM ACCESS - In some embodiments, the invention involves a system and method relating to managing power utilization in systems having multiple processing elements. In at least one embodiment, the present invention is intended to control the sleeping/wakefulness of processing elements, as necessary, to maintain a preferred level of power utilization in the platform. Activity is routed to sequestered processing elements instead of sleeping processing elements to save power. | 2012-12-13 |
20120317432 | ESTIMATING AND PRESERVING BATTERY LIFE BASED ON USAGE PATTERNS - Embodiments apply user-specific usage patterns to estimate and preserve remaining battery life on a computing device. An amount of battery drain and an execution context are determined and stored for a plurality of recurring time periods. The execution context identifies operations executed by the computing device, signal strength, and other data describing the associated time period. If one of the operations is expected to be executed during a recurrence of at least one of the time periods, the expected execution is adjusted based on execution context and an estimated remaining battery life for the computing device. For example, the computing device may postpone or reschedule the operation for a time period during which the operation is expected to have a greater likelihood of completing successfully. In some embodiments, the battery preservation operations are automatically enabled at a particular threshold. | 2012-12-13 |
20120317433 | DATA STORAGE SYSTEM WITH POWER CYCLE MANAGEMENT AND METHOD OF OPERATION THEREOF - A method of operation of a data storage system includes: providing a power monitor module for detecting a loss of host power; interrupting a unit controller by the power monitor module; configuring a memory controller by the unit controller; and writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power. | 2012-12-13 |
20120317434 | Method and Apparatus for Processor to Operate at Its Natural Clock Frequency in the System - A mechanism to generate a self-clock within a synchronous processing unit of an asynchronous digital device. The self-clock is designed to match the worst-case delay of pipeline processing unit in such a way that the pipeline processing unit is operate at its own natural clock frequency and shutting off when there is no valid data to process. The synchronization logic of the processing unit consists of self-clock that generates output clock to synchronize with the internal clock edge if the processing unit is active or synchronize with the input clock edge if the processing unit is inactive. | 2012-12-13 |
20120317435 | APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal. | 2012-12-13 |
20120317436 | OPERATOR MESSAGE COMMANDS FOR TESTING A COUPLING FACILITY - A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands. | 2012-12-13 |
20120317437 | Ranking Service Units to Provide and Protect Highly Available Services Using the Nway Redundancy Model - Presented are methods and apparatus for protecting a plurality of High Availability (HA) Service Instances (SIs) with a plurality of Service Units (SUs) with an Nway redundancy model. Any of the SUs associated with the Nway redundancy model can simultaneously be assigned an active HA state for some of the SIs and a standby HA state for other SIs. However, only one SU can have the active state for any given SI. The Nway redundancy model is a configured prior to runtime operation. | 2012-12-13 |
20120317438 | METHOD AND SYSTEM FOR PROVIDING IMMUNITY TO COMPUTERS - A method and system for providing immunity to a computer system wherein the system includes an immunity module, a recovery module, a maintenance module, an assessment module, and a decision module, wherein the immunity module, the recovery module, the maintenance module and the assessment module are each linked to the decision module. The maintenance module monitors the system for errors and sends an error alert message to the assessment module, which determines the severity of the error and the type of package required to fix the error. The assessment module sends a request regarding the type of package required to fix the error to the recovery module. The recovery module sends the package required to fix the error to the maintenance module, which fixes the error in the system. | 2012-12-13 |
20120317439 | Enhanced Storage Device Replacement System And Method - Recovery of a failed storage device of a RAID array to a replacement storage device is improved by initiating recovery before failure of the storage device occurs. If failure occurs before completing the transfer of all information from the failed storage device to the replacement storage device, then the RAID controller identifies untransferred information to recreate the failed storage device at the replacement storage device by re-building only the untransferred information with a parity operation using information stored at the array. | 2012-12-13 |
20120317440 | COMPILER INTERNAL FAULT HANDLING AND REPORTING - Embodiments of the invention provide systems and methods for handling internal compiler errors encountered during compilation of a computer program without breaking the compilation. Implementations of a computer-implemented compiler system include a compiler driver, configured to compile a computer program according to a set of compiler settings, and a number of compiler components, each corresponding to a portion of the computer program. Each compiler component is configured to detect an internal compiler error during compilation of the component; identify a recovery plan having a recovery target and at least one recovery setting; and direct the driver to continue compiling the computer program according to the recovery plan, such that the compilation recompiles from the recovery target and according to a modified set of compiler settings according to the at least one recovery setting. | 2012-12-13 |
20120317441 | NON-FAULTING AND FIRST FAULTING INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation). | 2012-12-13 |
20120317442 | EMBEDDED DEVICE AND EMBEDDED SYSTEM - The redundancy that is effected by preparing a plurality of units of hardware of an identical configuration results in high costs, complicating the application of same to inexpensive products. The present invention detects a fault in a function that is provided via hardware upon an apparatus having a variety of components, such as a CPU, capable of changing content to be processed at the application level, and an FPGA, capable of changing the content to be processed. When a fault is thus detected, the invention uses configuration information of an apparatus either within the apparatus or within apparatuses upon the network to select an apparatus capable of serving as a substitute, selects software required to implement the function, carries out procedures for facilitating the use of the software upon the substitute hardware (i.e., downloading the software, loading the software into a memory region accessible to the hardware), and carries out the processing in substitution. | 2012-12-13 |
20120317443 | VIRTUAL DEBUGGING SESSIONS - An approach to providing multiple concurrently executing debugging sessions for a currently executing operating system. The approach involves providing one first debugging session for debugging the currently executing operating system. The first debugging session has read access and write access to the data of the currently executing operating system. The approach also involves providing one or more second debugging sessions for the currently executing operating system. Each of the second debugging sessions has read-only access to the data of the currently executing operating system. The second debugging sessions run simultaneously with the first debugging session if the second debugging sessions are started while the first debugging session is active. As a result, multiple users can simultaneously debug the currently executing operating system. A lock may be used to ensure that only the first debugging session has write access to the data. The lock may be shared between the various debugging sessions for the operating system. | 2012-12-13 |
20120317444 | MONITORING AND DIAGNOSING DEVICE FOR WORKING MACHINE - Monitoring and diagnosing device including: a classification information storage section; frequency information storage section; a first data classifier section reading out reference classification information from the classification information storage section, comparing operational data, detected by a plurality of sensors and inputted in time sequence, with the reference classification information to classify the operational data, and then generating operational data classification information; a frequency comparator section compiling the operational data classification information, generating operational data frequency information by adding, to the operational data classification information, appearance frequency information for each classification of operational data, reading out reference frequency information from the frequency information storage section, and then generating operational data frequency comparison information by comparing operational data frequency information with the reference frequency information; and an abnormality diagnosing section performing an abnormality diagnosis upon the working machine by use of the operational data classification information and operational data frequency comparison information. | 2012-12-13 |
20120317445 | DECONFIGURE STORAGE CLASS MEMORY COMMAND - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 2012-12-13 |
20120317446 | COMPLIANCE MODE DETECTION FROM LIMITED INFORMATION - Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto. | 2012-12-13 |
20120317447 | PROPAGATING UNOBSERVED EXCEPTIONS IN DISTRIBUTED EXECUTION ENVIRONMENTS - The present invention extends to methods, systems, and computer program products for propagating unhandled exceptions in distributed execution environments, such as clusters. A job (e.g., a query) can include a series of computation steps that are executed on multiple compute nodes each processing parts of a distributed data set. Unhandled exceptions can be caught while computations are running on data partitions of different compute nodes. Unhandled exception objects can be stored in a serialized format in a compute node's local storage (or an alternate central location) along with auxiliary details such as the data partition being processed at the time. Stored serialized exception objects for a job can be harvested and aggregated in a single container object. The single container object can be passed back to the client. | 2012-12-13 |
20120317448 | SENDING NETWORK REJECT/ERROR CODES FROM A TERMINAL ADAPTOR TO TERMINAL EQUIPMENT THROUGH AN AT COMMAND INTERFACE - Error information is sent from a terminal adaptor that accesses a wireless network to terminal equipment coupled to access the wireless network through the terminal adaptor. The error information is sent in response to existence of any one of a plurality of errors conditions with respect to access to the wireless network. The error information includes an error type identifying a domain associated with a source of the error condition being reported and an error code providing a reject error cause for the error condition. One of the error conditions may include an unsolicited error received by the terminal adaptor from the wireless network or when a request by the TA is ignored by the wireless network. | 2012-12-13 |
20120317449 | DEVICE AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine. | 2012-12-13 |
20120317450 | SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops. | 2012-12-13 |
20120317451 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 2012-12-13 |
20120317452 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 2012-12-13 |
20120317453 | POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 2012-12-13 |
20120317454 | MULTI-TARGETING BOOLEAN SATISFIABILITY-BASED TEST PATTERN GENERATION - Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults. | 2012-12-13 |
20120317455 | SYMBOL ERROR DETECTION METHOD - The invention disclosed in this application describes an error detection method that can be used to identify an OFDM symbol that is interfered with. The method is based on computing a symbol by symbol path error metric from error correction code and by comparing the statistics of each individual symbol to the mean and the variance of the metric computed from the whole data packet. | 2012-12-13 |
20120317456 | Method and Apparatus for N+1 Packet Level Mesh Protection - Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN−1, to generate a codeword that includes the message symbols, m0 through mN−1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN−1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN−1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN−1, and the one or more check symbols through the linear feedback shift register. | 2012-12-13 |
20120317457 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 2012-12-13 |
20120317458 | MEMORY CONTROLLER AND NON-VOLATILE STORAGE DEVICE - A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group. | 2012-12-13 |
20120317459 | SYSTEMS AND METHODS FOR OPERATING ON A STORAGE DEVICE USING A LIFE-CYCLE DEPENDENT CODING SCHEME - Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme. | 2012-12-13 |
20120317460 | IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS - Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation. | 2012-12-13 |
20120317461 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING PACKET IN BROADCASTING AND COMMUNICATION SYSTEM - A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method and apparatus allows a receiver to recognize data in a packet lost due to data loss occurring in a network. To this end, Forward Error Correction (FEC) control-related information is generated, a packet including the generated FEC control-related information is generated, and the packet is transmitted. The FEC control-related information includes at least one of FEC configuration-related information and FEC encoding configuration-related information. | 2012-12-13 |