51st week of 2017 patent applcation highlights part 58 |
Patent application number | Title | Published |
20170365648 | Display Device, Display Module, Electronic Device, and Method for Manufacturing the Display Device - A display device with high visibility regardless of the ambient brightness is provided. The display device includes a first display element, a second display element, a first transistor, and a second transistor. The first display element has a function of reflecting visible light. The second display element has a function of emitting visible light. The first transistor has a function of controlling the driving of the first display element. The second transistor has a function of controlling the driving of the second display element. The first transistor is positioned closer to a display surface side of the display device than the first display element is. The first display element is positioned closer to the display surface side of the display device than the second display element and the second transistor are. | 2017-12-21 |
20170365649 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND A METHOD OF MANUFACTURING THE SAME - An organic light-emitting diode display including a substrate, a first transistor, and an organic light-emitting element. The first transistor is positioned on the substrate. The first transistor includes a first active layer including a first source region, a first channel region extending from the first source region, a first drain region extending from the first channel region, a first conductive pattern, and a first gate electrode positioned on the first active layer. The organic light-emitting element is connected to the first transistor. The first conductive pattern is in contact with the first active layer and covers the first source region and the second source region. | 2017-12-21 |
20170365650 | DISPLAY DEVICE HAVING A BENDING REGION - A display device includes a substrate having a first region in which an image is displayed, a second region in which an image is not displayed, and a bending region connecting the first region and the second region. The bending region is configured to bend along a bending axis which extends in a first direction. A plurality of pad terminals is disposed within the second region. A first width of the bending region, measured along the first direction, is narrower than a second width of the second region, measured along the first direction. | 2017-12-21 |
20170365651 | ORGANIC LIGHT-EMITTING DIODE DISPLAY - An organic light-emitting diode display is disclosed. The display includes a semiconductor layer formed over a substrate, a scan line formed over the semiconductor layer and configured to provide a scan signal, and a light emission control line formed over the semiconductor layer and configured to provide a light emission control signal. The display includes a data line configured to provide a data voltage and a driving voltage line configured to provide a driving voltage, wherein the driving voltage line crosses the scan line and is electrically insulated from the scan line. A switching transistor is electrically connected to the scan line and the data line and includes a switching drain electrode. A driving transistor includes a driving source electrode electrically connected to the switching drain electrode. Any one of the semiconductor layer and the light emission control line includes an extension at least partially overlapping the data line. | 2017-12-21 |
20170365652 | SLIM-BEZEL FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A slim-bezel flexible display device and a manufacturing method thereof are disclosed. A through hole is formed in a first base plate of a lower substrate in an area adjacent to an edge thereof. A conductive connection body is mounted in the through hole. The conductive connection body is connected to a circuit layout layer and a flexible connection circuit that is connected to a drive circuit board so as to have the drive circuit board and the circuit layout layer connected. It is not necessary for the side of the lower substrate associated with the circuit layout layer to provide an additional connection zone for connection with the flexible connection circuit so that an effective display zone of a flexible display device can be enlarged and a bezel area can be reduced. | 2017-12-21 |
20170365653 | DISPLAY APPARATUS HAVING GROOVED TERMINALS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a display panel comprising a display substrate on which a plurality of pad terminals is disposed, and a driving unit comprising a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals. | 2017-12-21 |
20170365654 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device including a base structure, a first pattern having at least one projection disposed on the base structure, a first conductive layer including a first portion disposed on the base structure and a second portion disposed on the first pattern and connected to the first portion, an insulating layer disposed on the first conductive layer covering the first portion and exposing the second portion, and a second conductive layer provided on the insulating layer and overlapping the first conductive layer. The second conductive layer is spaced apart from the first portion and is in contact with the second portion. Methods of manufacturing an electronic device capable of reducing the number of process steps in the manufacturing process are also disclosed. | 2017-12-21 |
20170365655 | CHIP RESISTOR AND ELECTRONIC EQUIPMENT HAVING RESISTANCE CIRCUIT NETWORK - A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value. | 2017-12-21 |
20170365656 | METHOD AND APPARATUS FOR A THIN FILM DIELECTRIC STACK - A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor having a substrate, a first electrode layer on the substrate, a first dielectric layer on the first electrode layer where the first dielectric layer has a columnar-oriented grain structure, a group of second dielectric layers stacked on the first dielectric layer where each of the group of second dielectric layers has a randomly-oriented grain structure, and a second electrode layer on the group of second dielectric layers. Other embodiments are disclosed. | 2017-12-21 |
20170365657 | STANDARD CELL ARCHITECTURE FOR PARASITIC RESISTANCE REDUCTION - A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together. | 2017-12-21 |
20170365658 | FINFET WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer. | 2017-12-21 |
20170365659 | FINFET WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer. | 2017-12-21 |
20170365660 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND ELECTRONIC DEVICE - A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material. | 2017-12-21 |
20170365661 | Structures and Methods for Long-Channel Devices in Nanosheet Technology - Techniques for providing supporting structures for suspended nanosheets/wires in long-channel devices are provided. In one aspect, a method of forming a device structure includes: forming a series of alternating active and sacrificial layers as a stack on a substrate; patterning at least one feature through each of the active and sacrificial layers in the stack; filling the feature with a fill material that is resistant to etching performed on the sacrificial layers; and etching the sacrificial layers to selectively remove at least a portion of each of the sacrificial layers from the stack thereby suspending the active layers, wherein following the etching the fill material remains as a structure supporting the suspended active layers. Transistor devices and methods for formation thereof are also provided. | 2017-12-21 |
20170365662 | VERTICAL SINGLE ELECTRON TRANSISTOR FORMED BY CONDENSATION - A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer. | 2017-12-21 |
20170365663 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING SAME - A method for producing a tunnel field-effect transistor (TFET) having a source region, a channel region, and a drain region includes arranging an epitaxial layer on a silicon substrate; applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate; forming a doped pocket region below the gate dielectric adjacent to the source region; forming a selectively silicidated region in the source region, the selectively silicidated region extending as far as to below a gate; and forming a counter-doped region doped in an opposite way to the pocket region adjacent to the pocket region in the source region by diffusion of dopants out of the silicidated region, as a result of which a tunnel junction parallel to the electric field lines of the gate electrode is achieved. | 2017-12-21 |
20170365664 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device according to an embodiment, includes: a silicon carbide layer; a gate electrode; and a gate insulating layer, the gate electrode including a p-type silicon carbide region containing aluminum, the gate insulating layer having a first region and a second region, the first region including a silicon oxide or a silicon oxynitride, the second region being positioned between the first region and the gate electrode, the second region including an oxide containing aluminum. | 2017-12-21 |
20170365665 | SEMICONDUCTOR DEVICE - On a front surface of an n | 2017-12-21 |
20170365666 | NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR - A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266. | 2017-12-21 |
20170365667 | EPITAXIAL SUBSTRATE - A GaN epitaxial substrate comprises a growth substrate and a multilayer structure grown on the growth substrate in the Ga-polar direction. The multilayer structure comprises: a buffer layer, an n-type conductive layer formed on the buffer layer, a first GaN layer formed on the n-type conductive layer, an electron supply layer formed on the first GaN layer, and a second GaN layer formed on the electron supply layer. | 2017-12-21 |
20170365668 | Semiconductor Device Channel System and Method - A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not. | 2017-12-21 |
20170365669 | POWER SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate. | 2017-12-21 |
20170365670 | WIDE BANDGAP FIELD EFFECT TRANSISTORS WITH SOURCE CONNECTED FIELD PLATES - A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device. | 2017-12-21 |
20170365671 | SEMICONDUCTOR DEVICE, POWER SUPPLY CIRCUIT, AND COMPUTER - A semiconductor device of an embodiment includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first electrode on the second nitride semiconductor layer, a second electrode on the second nitride semiconductor layer, a gate electrode located between the first electrode and the second electrode, and a first insulating layer located at least between the gate electrode and the second electrode on the second nitride semiconductor layer, the first insulating layer being an oxide of at least one first element selected from the group consisting of Hf, Zr, and Ti, and containing 5×10 | 2017-12-21 |
20170365672 | COMPOSITE GATE DIELECTRIC LAYER APPLIED TO GROUP III-V SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an Al | 2017-12-21 |
20170365673 | UNIFORM VERTICAL FIELD EFFECT TRANSISTOR SPACERS - Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer. | 2017-12-21 |
20170365674 | SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region. | 2017-12-21 |
20170365675 | DUMMY PATTERN ARRANGEMENT AND METHOD OF ARRANGING DUMMY PATTERNS - A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region. | 2017-12-21 |
20170365676 | DEVICE FOR IMPROVING PERFORMANCE THROUGH GATE CUT LAST PROCESS - Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method. | 2017-12-21 |
20170365677 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 2017-12-21 |
20170365678 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - An embodiment of a semiconductor device includes forming an active region that extends vertically into the semiconductor material in which the semiconductor device is formed. The active region may include a P-N junction or alternately a gate or a channel region of an MOS transistor. | 2017-12-21 |
20170365679 | SEMICONDUCTOR DEVICE HAVING A METAL GATE ELECTRODE STACK - A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer. | 2017-12-21 |
20170365680 | GATE PATTERNING FOR AC AND DC PERFORMANCE BOOST - A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multi-layer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom. | 2017-12-21 |
20170365681 | FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCESSES OF FORMING SAME, AND SYSTEMS CONTAINING SAME - An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer. | 2017-12-21 |
20170365682 | SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES - A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material. | 2017-12-21 |
20170365683 | POWER DEVICE HAVING A POLYSILICON-FILLED TRENCH WITH A TAPERED OXIDE THICKNESS - In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step. | 2017-12-21 |
20170365684 | Method for Forming Mask Pattern, Thin Film Transistor and Method for Forming the Same, and Display Device - A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern. | 2017-12-21 |
20170365685 | INTEGRATION OF STRAINED SILICON GERMANIUM PFET DEVICE AND SILICON NFET DEVICE FOR FINFET STRUCTURES - A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer. | 2017-12-21 |
20170365686 | Method and Structure for FinFET Comprising Patterned Oxide and Dielectric Layer under Spacer Features - A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials. | 2017-12-21 |
20170365687 | METHOD FOR MANUFACTURING AN EMITTER FOR HIGH-SPEED HETEROJUNCTION BIPOLAR TRANSISTORS - A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench isolation; an isolation layer arranged on the semiconductor substrate, wherein the first isolation layer comprises a recess forming an emitter window; lateral spacers arranged on sidewalls of the emitter window; a base layer arranged in the emitter window on the semiconductor substrate; and an emitter layer arranged on the isolation layer, the lateral spacers and the base layer. A sacrificial layer is provided on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window. The sacrificial layer is selectively removed up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer. The emitter layer is selectively removed up to the isolation layer while maintaining the filled recess of the emitter layer. | 2017-12-21 |
20170365688 | HETEROJUNCTION BIPOLAR TRANSISTOR FULLY SELF-ALIGNED TO DIFFUSION REGION WITH STRONGLY MINIMIZED SUBSTRATE PARASITICS AND SELECTIVE PRE-STRUCTURED EPITAXIAL BASE LINK - Methods for manufacturing a bipolar junction transistor are provided. A method includes providing a semiconductor substrate having a trench isolation, where a pad resulting from a manufacturing of the trench isolation is arranged on the semiconductor substrate, providing an isolation layer on the semiconductor substrate and the pad such that the pad is covered by the isolation layer, removing the isolation layer up to the pad, and selectively removing the pad to obtain an emitter window. | 2017-12-21 |
20170365689 | MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE - A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side. | 2017-12-21 |
20170365690 | TRANSISTOR DEVICE AND FABRICATION METHOD - Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the dummy gate film to form a modified film. The modified film and the remaining dummy gate film are etched to form a modified layer and a dummy gate layer on the substrate. Source/drain regions are formed in the substrate and on both sides of the dummy gate layer. A dielectric film is formed on each of the substrate, the source/drain regions, and the dummy gate layer. The dielectric film and the modified layer are planarized to provide a dielectric layer, and to remove the modified layer and expose the dummy gate layer. The dielectric film has a planarization rate lower than the modified layer, and the formed dielectric layer has a surface higher than the exposed dummy gate layer. | 2017-12-21 |
20170365691 | Method of Forming a Contact - A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers. | 2017-12-21 |
20170365692 | ASPECT RATIO TRAPPING IN CHANNEL LAST PROCESS - A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening. | 2017-12-21 |
20170365693 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask. | 2017-12-21 |
20170365694 | COMPLEMENTARY TUNNELING FET DEVICES AND METHOD FOR FORMING THE SAME - Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions. | 2017-12-21 |
20170365695 | FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS - Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening. | 2017-12-21 |
20170365696 | POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from each other in a substrate; a body region having a first conductivity type disposed between the first trench and the second trench; a pair of floating regions having a first conductivity type spaced apart from each other and surrounding a bottom surface and at least one side surface of the first trench and the second trench, respectively; and a drift region having a second conductivity type which extends from below the pair of floating regions through a region between the pair of floating regions to the body region, wherein, in the drift region, the doping concentration of a second conductivity type between the pair of floating regions is higher than the doping concentration of a second conductivity type below the pair of floating regions. | 2017-12-21 |
20170365697 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N | 2017-12-21 |
20170365698 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface; a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity; a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type; a first electrode disposed on the second surface of the substrate; a second electrode disposed on the first nitride semiconductor layer; and a gate electrode disposed on the second nitride semiconductor layer. | 2017-12-21 |
20170365699 | Low Dislocation Density III-Nitride Semiconductor Component - There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a III-Nitride buffer layer situated over the group III-V intermediate stack, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers. | 2017-12-21 |
20170365700 | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE AND METHOD OF MAKING THE SAME - A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1×10 | 2017-12-21 |
20170365701 | Charge Trapping Prevention III-Nitride Transistor - There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer. | 2017-12-21 |
20170365702 | High-Electron-Mobility Transistor Having a Buried Field Plate - A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel including a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects. | 2017-12-21 |
20170365703 | FIELD-EFFECT TRANSISTOR AND METHOD OF MAKING THE SAME - A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer. | 2017-12-21 |
20170365704 | VERTICAL DMOS TRANSISTOR - A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side of the gate electrode, the trench being lined with a sidewall dielectric layer and filled with a bottom dielectric layer and a conductive layer above the bottom dielectric layer, the conductive layer being electrically connected to the gate electrode; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor. | 2017-12-21 |
20170365705 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACKS - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack over the semiconductor substrate. The first gate stack includes a metal electrode. The semiconductor device structure also includes a second gate stack over the semiconductor substrate, and the second gate stack includes a polysilicon element. | 2017-12-21 |
20170365706 | FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED EXTENSION PORTIONS OF EPITAXIAL ACTIVE REGIONS - A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an implantation mask to amorphize surface portions of the semiconductor fin into inverted U-shaped amorphous semiconductor portions. A gate spacer is formed around the gate structure, and the inverted U-shaped amorphous semiconductor portions are etched selective to a single crystalline portion of the semiconductor fin and the gate structure. A pair of inverted U-shaped cavities is formed underneath the gate spacer and above the remaining portion of the semiconductor fin. A doped epitaxial semiconductor material is deposited by a selective epitaxy process to form doped epitaxial active regions that include self-aligned extension portions underlying the gate spacer. | 2017-12-21 |
20170365707 | SEMICONDUCTOR DEVICE INCLUDING FIN-FET AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer. | 2017-12-21 |
20170365708 | TRENCH POWER SEMICONDUCTOR DEVICE - A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer. | 2017-12-21 |
20170365709 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region. | 2017-12-21 |
20170365710 | LATERAL SUPER-JUNCTION MOSFET DEVICE AND TERMINATION STRUCTURE - A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased. | 2017-12-21 |
20170365711 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film. | 2017-12-21 |
20170365712 | PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS - A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor. | 2017-12-21 |
20170365713 | VERTICAL TRANSISTOR HAVING UNIFORM BOTTOM SPACERS - A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure. | 2017-12-21 |
20170365714 | PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS - A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor. | 2017-12-21 |
20170365715 | Damage Implantation of a Cap Layer - A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer. | 2017-12-21 |
20170365716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern. | 2017-12-21 |
20170365717 | SILICON-CONTAINING, TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING III-N SOURCE - Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material. | 2017-12-21 |
20170365718 | INSULATOR/METAL PASSIVATION OF MOTFT - A method of passivating a MOTFT including providing a metal oxide thin film transistor having a surface defined by spaced apart source/drain terminals positioned on a layer of semiconductor metal oxide and material in a space between the source/drain terminals, the space between the source/drain terminals defining a conduction channel in the layer of semiconductor metal oxide. Forming a layer of passivation material on the surface defined by the spaced apart source/drain terminals and the material in the space between the source/drain terminals. Establishing oxygen vacancy equilibrium in the conduction channel of the layer of semiconductor metal oxide by annealing in an oxygen containing ambient the MOTFT and layer of passivation material and depositing a layer including a noble metal, a refractory metal, and/or a transparent conducting metal oxide on the layer of passivation material overlying the space between the source/drain terminals. | 2017-12-21 |
20170365719 | Negative Capacitance Field Effect Transistor - A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO | 2017-12-21 |
20170365720 | TRANSISTOR, ELECTRONIC DEVICE, MANUFACTURING METHOD OF TRANSISTOR - Reducing the power consumption of a transistor and stably controlling its threshold value. Providing a transistor comprising a first conductive layer, a first insulating layer and a second insulating layer over the first conductive layer, a semiconductor layer over the first insulating layer, a third insulating layer over the first conductive layer and the semiconductor layer, a second conductive layer over the second insulating layer, and a gate electrode over the third insulating layer. The first conductive layer is in an electrically floating state. The first conductive layer has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween, a region overlapping with the second conductive layer with the second insulating layer provided therebetween, and a region overlapping with the gate electrode with the third insulating layer provided therebetween. | 2017-12-21 |
20170365721 | DIODES AND FABRICATION METHODS THEREOF - Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material. | 2017-12-21 |
20170365722 | PROCESS OF FORMING METAL-INSULATOR-METAL (MIM) CAPACITOR - A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 μm at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of metal same with a metal contained in the lower layer of the lower electrode. | 2017-12-21 |
20170365723 | VACUUM PACKAGE, ELECTRONIC DEVICE, AND VEHICLE - A vacuum package includes a substrate, a pair of through electrodes that penetrates the substrate, each of the pair of the trough electrodes having first end portion, and a getter that is joined to the first end portions of the pair of the through electrodes, and is heated by electronic conduction via the pair of the through electrodes A portion of the getter between the through electrodes is spaced apart from the substrate. | 2017-12-21 |
20170365724 | Transparent Conductive Oxide In Silicon Heterojunction Solar Cells - Devices and methods for reducing optical losses in transparent conductive oxides (TCOs) used in silicon heterojunction (SHJ) solar cells while enhancing series resistance are disclosed herein. In particular, the methods include reducing the thickness of TCO layers by about 200% to 300% and depositing hydrogenated dielectric layers on top to form double layers of antireflection coating. It has been discovered that the conductivity of a thin TCO layer can be increased through a hydrogen treatment supplied from the capping dielectric during the post deposition annealing. The optimized cells with ITO/SiO | 2017-12-21 |
20170365725 | ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP - The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV. | 2017-12-21 |
20170365726 | METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS - Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure. | 2017-12-21 |
20170365727 | SOLAR CELL MODULE - A solar cell module includes: a light-diffusing member adjacent to a solar cell; a tab line disposed on front surfaces of solar cells and having a light-diffusing shape on a light-entering side; and a protective member having first and second principal surfaces. When an average distance between a front surface of the solar cell and the second principal surface is expressed as D, a refractive index of the protective member is expressed as n, and a critical angle for total reflection satisfying sin R=1/ | 2017-12-21 |
20170365728 | TANDEM SOLAR CELL MODULE - A tandem solar cell module includes a transparent substrate, a first solar cell unit, and a second solar cell unit disposed between the transparent substrate and the first solar cell unit. The first solar cell unit includes a first electrode, a second electrode, and a first absorption layer disposed between the first electrode and the second electrode, and the second solar cell unit includes a third electrode, a fourth electrode, and a second absorption layer disposed between the third electrode and the fourth electrode, wherein the second electrode is located adjacent to the third electrode, and the positions of the second electrode, the third electrode, and the fourth electrode are corresponding to each other. | 2017-12-21 |
20170365729 | NANOWIRE COMPOSITE STRUCTURE AND METHODS OF FORMING THE SAME, SENSING DEVICE AND METHODS OF FORMING THE SAME AND PROTECTIVE STRUCTURES OF A NANOWIRE - A nanowire composite structure is provided. The nanowire composite structure includes a nanowire core, wherein a material of the nanowire core includes Se, Te or a combination thereof. The nanowire composite structure also includes a metal layer covering the nanowire core. A method for forming the nanowire composite structure, a protective structure of a nanowire, a sensing device, and a method for forming a sensing device are also provided. | 2017-12-21 |
20170365730 | SOLAR CANOPY SYSTEM - A solar canopy has a solar panel assembly including a first solar panel coupled to a second solar panel and oriented non-parallel with respect to the second solar panel. The solar panel assembly has an effective solar-panel-assembly wind loading less than a sum of a first-solar-panel effective wind loading and a second-solar-panel effective wind loading determined individually. An actual load applied by the solar panel assembly to a solar-panel-assembly support structure coupled thereto when the solar panel assembly is subject to a wind loading is less than a design load for the solar panel assembly subject to the wind loading based on a sum of a first-solar-panel net pressure and a second-solar-panel net pressure determined independently. | 2017-12-21 |
20170365731 | MAIN-GATE-FREE AND HIGH-EFFICIENCY BACK-CONTACT SOLAR CELL MODULE, MAIN-GATE-FREE AND HIGH-EFFICIENCY BACK-CONTACT ASSEMBLY, AND PREPARATION PROCESS THEREOF - The present application relates to the field of solar cells, and in particular to a main-gate-free and high-efficiency back-contact solar cell module, assembly, and a preparation process thereof. The main-gate-free and high-efficiency back-contact solar cell module comprises solar cells and an electrical connection layer, a backlight side of the solar cells having P-electrodes connected to a P-type doping layer and N-electrodes connected to an N-type doping layer, wherein the electrical connection layer comprises a number of small conductive gate lines, part of which are connected to the P-electrodes on the backlight side of the solar cells while the other part of which are connected to the N-electrodes on the backlight side of the solar cells; and, the small conductive gate lines are of a multi-section structure. The present application has the following beneficial effects: the usage of silver paste is decreased, and the cost is reduced; moreover. The arrangement of small conductive gate lines in a multi-section structure reduces the series resistance and the transmission distance of a filling factor, so that the efficiency is improved and the stress on the cells from the small conductive gate lines can be effectively reduced. | 2017-12-21 |
20170365732 | DILUTE NITRIDE BISMIDE SEMICONDUCTOR ALLOYS - High efficiency dilute nitride bismide alloys and multijunction photovoltaic cells incorporating the high efficiency dilute nitride bismide alloys are disclosed. Bismuth-containing dilute nitride subcells exhibit a high efficiency across a broad range of irradiance energies, a high short circuit current density, and a high open circuit voltage. | 2017-12-21 |
20170365733 | METHOD FOR PRODUCING DOPED POLYCRYSTALLINE SEMICONDUCTOR LAYERS - The present invention relates to a method for producing highly doped polycrystalline semiconductor layers on a semiconductor substrate, wherein a first Si precursor composition comprising at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate; optionally a second Si precursor composition comprising at least one second dopant is applied to one or more other regions of the surface of the semiconductor substrate, where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; and the coated regions of the surface of the semiconductor substrate are each converted, so as to form polycrystalline silicon from the Si precursor. The invention further relates to the semiconductor obtainable by the method and to the use thereof, especially in the production of solar cells. | 2017-12-21 |
20170365734 | LASER DOPING OF SEMICONDUCTORS - The present invention relates to a process for the production of structured, highly efficient solar cells and of photovoltaic elements which have regions of different doping. The invention likewise relates to the solar cells having increased efficiency produced in this way. | 2017-12-21 |
20170365735 | REDUCING DARK CURRENT IN GERMANIUM PHOTODIODES BY ELECTRICAL OVER-STRESS - Methods and systems for reducing dark current in a photodiode include heating a photodiode above room temperature. A reverse bias voltage is applied to the heated photodiode to reduce a dark current generated by the photodiode. | 2017-12-21 |
20170365736 | SEMICONDUCTOR CHIP, METHOD FOR PRODUCING A PLURALITY OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING AN ELECTRONIC OR OPTOELECTRONIC DEVICE AND ELECTRONIC OR OPTOELECTRONIC DEVICE - A method for producing a multiplicity of semiconductor chips ( | 2017-12-21 |
20170365737 | OPTOELECTRONIC DEVICE COMPRISING THREE-DIMENSIONAL SEMICONDUCTOR ELEMENTS AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic device including a carrier having a face including flat butt-jointed facets inclined in relation to each other; seeds, mainly made of a first compound selected from the group including the compounds III-V, the compounds II-VI, and the compounds IV, in contact with the carrier in the region of at least some of the joints between the facets; and conical or frustoconical, wire-like three-dimensional semiconductor elements of a nanometric or micrometric size, mainly made of the first compound, on the seeds. | 2017-12-21 |
20170365738 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A light emitting element includes an n-side semiconductor layer, a p-side semiconductor layer, a plurality of holes, a first p-electrode, a second p-electrode and an n-electrode. The n-side semiconductor layer has a hexagonal shape in plan view. The p-side semiconductor layer has a hexagonal shape in plan view and provided over the n-side semiconductor layer. The holes are arranged in the p-side semiconductor layer so that the n-side semiconductor layer is exposed through the plurality of holes. The first p-electrode is in contact with the p-side semiconductor layer. The second p-electrode is arranged on the first p-electrode adjacent to a corner corresponding to one of vertices of the hexagonal shape. The second p-electrode has sides that are respectively parallel to sides defining the corner in plan view. The n-electrode is arranged over the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes. | 2017-12-21 |
20170365739 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A semiconductor light emitting device package includes a light emitting structure having a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first surface, and a second surface, a first electrode and a second electrode disposed on the second surface of the light emitting structure; an insulating layer, a first metal pad and a second metal pad disposed on the insulating layer, and each having a surface with a first fine uneven pattern so as to have a first surface roughness, a first bonding pad and a second bonding pad disposed on the first metal pad and the second metal pad, respectively, and each having a surface with a second fine uneven pattern so as to have a second surface roughness, and an encapsulant encapsulating the first bonding pad, the second bonding pad, the first metal pad, and the second metal pad. | 2017-12-21 |
20170365740 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - A light-emitting device comprises a textured substrate comprising a plurality of textured structures, wherein the textured structures and the textured substrate are both composed of sapphire; and a light-emitting stack overlaying the textured substrate, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, wherein one of the plurality of textured structures comprises a top portion and a bottom portion, wherein a first distance between a first projection of the top portion on the bottom portion and the bottom portion at one side is different from a second distance between a second projection of the top portion on the bottom portion and the bottom portion at another side. | 2017-12-21 |
20170365741 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a rectangular shape with a 1 | 2017-12-21 |
20170365742 | DIODE HAVING VERTICAL STRUCTURE - A light emitting device can include a GaN layer having a multilayer structure that can include an n-type layer, an active layer, and a p-type layer, the GaN layer having a first surface and a second surface; a conductive structure on the first surface of the GaN layer, the conductive structure includes a first electrode in contact with the first surface of the GaN layer, the first electrode is configured to reflect light from the active layer back through the second surface of the GaN layer; and a metal layer including Au, in which the metal layer serves as a first pad; a second electrode on the second surface of the GaN layer; and a second pad on the second electrode, in which a thickness of the second pad is about 0.5 μm or higher. | 2017-12-21 |
20170365743 | VERTICAL LIGHT EMITTING DIODE HAVING ELECTRODE CONFIGURATION AND LIGHT EMITTING DIODE PACKAGE HAVING THE SAME - A light emitting diode including a semiconductor stack including a lower semiconductor layer, an active layer, and an upper semiconductor layer; an upper electrode connected to the upper semiconductor layer and including an electrode pad and extensions extending from the electrode pad; and a lower electrode connected to the lower semiconductor layer. The electrode pad includes a first electrode pad having an elongated shape, disposed along a first side of the upper semiconductor layer, and covering the upper semiconductor layer near the first side of the upper semiconductor layer, and the extensions include an edge extension extending along an edge of the upper semiconductor layer in the electrode pad and surrounding a luminous region and middle extensions extending from the edge extension or the electrode pad and dividing the luminous region into a plurality of luminous regions. | 2017-12-21 |
20170365744 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT ARRAY COMPRISING THE SAME - Embodiments of a light-emitting element and a light-emitting element array comprise: a light-emitting structure which includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; first and second electrodes which are disposed respectively on the first and second conductive type semiconductor layers; and an insulation layer which is disposed on the light-emitting structure exposed between the first electrode and the second electrode, wherein the second electrode comprises a light-emitting element including: a first part which overlaps with the second conductive type semiconductor layer in the thickness direction of the light-emitting structure; and a second part which extends from the first part and does not overlap with the second conductive type semiconductor layer in the thickness direction, thereby being capable of improving the productivity of a light-emitting element manufacturing process while minimizing the light leakage phenomenon between the light-emitting structure and the second electrode. | 2017-12-21 |
20170365745 | SEMICONDUCTOR LIGHT-EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor light-emitting device may include an emission structure, a protection pattern layer on a limited region of the emission structure, and an insulating pattern layer on the emission structure. The protection pattern layer may expose a separate remaining region of the emission structure, and the first insulating pattern layer may cover at least the remaining region of the emission structure. The insulating layer may include an opening that exposes at least a portion of a surface of the protection pattern layer, such that the emission structure remains covered by at least one of the insulating layer and the protection pattern layer. | 2017-12-21 |
20170365746 | WAVELENGTH CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE - In some embodiments of the invention, a device includes a semiconductor light emitting device having a first light extraction surface, a wavelength converting element, and a second light extraction surface. A majority of light extracted from the semiconductor light emitting device is extracted from the first light extraction surface. The first light extraction surface has a first area. The second light extraction surface is disposed over the first light extraction surface and has a second area. The first area is larger than the second area. | 2017-12-21 |
20170365747 | LED WITH HIGH THERMAL CONDUCTIVITY PARTICLES IN PHOSPHOR CONVERSION LAYER - In one embodiment, a solid cylindrical tablet is pre-formed for a reflective cup containing an LED die, such as a blue LED die. The tablet comprises uniformly-mixed phosphor particles and transparent/translucent particles of a high TC material, such as quartz, in a hardened silicone binder, where the index of refraction of the high TC material is matched to that of the silicone to minimize internal reflection. Tablets can be made virtually identical in composition and size. The bulk of the tablet will be the high TC material. After the tablet is placed in the cup, the LED module is heated, preferably in a vacuum, to melt the silicone so that the mixture flows around the LED die and fills the voids to encapsulate the LED die. The silicone is then cooled to harden. | 2017-12-21 |