51st week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100320497 | LED bracket structure - The present invention relates to a new LED bracket structure and in particular to a bracket that adopts the structure in which the upper section and lower section are made of different materials, the main improvements including: the bottom of the bracket is provided with a groove for embedding and fixing of a conductive pin, the bracket may be made of other conductive materials such as iron plated with silver, and the conductive pin may be made of red brass and bronze of good conductive performance so as to reduce the consumption of copper in this structure and the consumption of precious metal copper significantly. | 2010-12-23 |
20100320498 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device includes: a substrate; and a semiconductor layered structure including an n-type semiconductor layer that has an exposed region, and a p-type semiconductor layer that is disposed over the n-type semiconductor layer without extending over the exposed region. An electrode unit is electrically coupled to the semiconductor layered structure, and includes a first electrode and a second electrode. The second electrode has an electrode pad, an end node, and a connecting strip. The electrode pad is larger than the end node. The connecting strip is narrower than the end node. | 2010-12-23 |
20100320499 | LIGHT EMITTING DIODE REPLACEMENT LAMP - Thermal management and control techniques for light emitting diode and other incandescent replacement light technologies using a current controller are disclosed. | 2010-12-23 |
20100320500 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN EVEN COATING THICKNESS USING ELECTRO-LESS PLATING AND RELATED DEVICE - A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions. | 2010-12-23 |
20100320501 | NON-SNAPBACK SCR FOR ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) protection device ( | 2010-12-23 |
20100320502 | GERMANIUM/SILICON AVALANCHE PHOTODETECTOR WITH SEPARATE ABSORPTION AND MULTIPLICATION REGIONS - A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region. | 2010-12-23 |
20100320503 | STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOF - The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions. | 2010-12-23 |
20100320504 | SEMICONDUCTOR DEVICE COMPRISING GATE ELECTRODE SURROUNDING ENTIRE CIRCUMFERENCE OF CHANNEL REGION AND METHOD FOR MANUFACTURING THE SAME - Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film. | 2010-12-23 |
20100320505 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND AMPLIFIER - A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face. | 2010-12-23 |
20100320506 | Ultra-Low Dislocation Density Group III - Nitride Semiconductor Substrates Grown Via Nano- Or Micro-Particle Film - A high quality Group III-Nitride semiconductor crystal with ultra-low dislocation density is grown epitaxially on a substrate via a particle film with multiple vertically-arranged layers of spheres with innumerable micro- and/or nano-voids formed among the spheres. The spheres can be composed of a variety of materials, and in particular silica or silicon dioxide (SiO2). | 2010-12-23 |
20100320507 | Electronic device, method for manufacturing the same, and silicon substrate for electronic device - An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate; and forming a back-surface element aligned with respect to the element, on a back-surface side of the Si substrate after the substrate is etched. A mark is formed by etching and removing the Si layer and the insulating layer in a predetermined position of the SOI substrate. The element is formed using a concave part as a reference position. The concave part appears on the front surface of the Si substrate epitaxially grown on the mark. The back-surface element is formed using the mark as a reference position. The mark appears after the substrate is etched. | 2010-12-23 |
20100320508 | HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR - The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESPET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region. | 2010-12-23 |
20100320509 | Method for forming and integrating metal gate transistors having self-aligned contacts and related structure - According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate. | 2010-12-23 |
20100320510 | Interfacial Barrier for Work Function Modification of High Performance CMOS Devices - A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact. | 2010-12-23 |
20100320511 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is fabricated by forming a semiconductor substrate as a convex shape to increase a effective channel of a transistor and by stacking a first silicon germanium layer and a first silicon layer on the semiconductor substrate to form a first layer and stacking a second silicon germanium layer and a second silicon layer on the first layer to form a second layer such that the current reduced due to the increased effective channel is ensured, thereby being capable of high speed performance. | 2010-12-23 |
20100320512 | Semiconductor device manufacturing method and semiconductor device - Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps. | 2010-12-23 |
20100320513 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device ( | 2010-12-23 |
20100320514 | DIGITAL RADIOGRAPHY IMAGER WITH BURIED INTERCONNECT LAYER IN SILICON-ON-GLASS AND METHOD OF FABRICATING SAME - A method of forming an imaging array includes providing a single crystal silicon substrate having an internal separation layer, forming a patterned conductive layer proximate a first side of the single crystal silicon substrate, forming an electrically conductive layer on the first side of the single crystal silicon substrate and in communication with the patterned conductive layer, securing the single crystal silicon substrate having the patterned conductive layer and electrically conductive layer formed thereon to a glass substrate with the first side of the single crystal silicon substrate proximate the glass substrate, separating the single crystal silicon substrate at the internal separation layer to create an exposed surface opposite the first side of the single crystal silicon substrate and forming an array comprising a plurality of photosensitive elements and readout elements on the exposed surface. | 2010-12-23 |
20100320515 | High sensitivity image sensors and methods of operating the same - A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.) | 2010-12-23 |
20100320516 | IMAGE SENSOR HAVING FOUR-TRANSISTOR OR FIVE-TRANSISTOR PIXELS WITH RESET NOISE REDUCTION - The invention relates to image sensors produced with CMOS technology, whose individual pixels, arranged in an array of rows and columns, each consist of a photodiode associated with a charge storage region which receives the photogenerated charge before a charge readout phase. To eliminate the risk of introducing kTC-type noise into the signal, during the reset of the storage zone at the end of a readout cycle, the invention proposes that the storage zone be divided into two parts one of which, adjacent to the reset gage, is covered by a diffused region of the same type of conductivity as the substrate in which the photodiode is formed, this region being brought to the fixed potential of the substrate, and the other of which is not covered by such a region and is not adjacent to the reset gate. | 2010-12-23 |
20100320517 | SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging apparatus comprises: a plurality of photoelectric conversion elements for converting light into an electric charge, including a first photoelectric conversion element; a first semiconductor region from which the electric charge is transferred from a first photoelectric conversion element; an amplifying MOS transistor including a gate electrode connected to the first semiconductor region to amplify the potential of the first semiconductor region; an insulating film; a metal wiring layer above the insulating film; a local interconnect of a first conductor, formed in the insulating film, for connecting the gate electrode of the amplifying MOS transistor to the first semiconductor region not through the metal wiring layer; a second semiconductor region, different from the first semiconductor region; and a second conductor for connecting the second semiconductor region to at least a part of the metal wiring layer. | 2010-12-23 |
20100320518 | SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film. | 2010-12-23 |
20100320519 | FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR - Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode. | 2010-12-23 |
20100320520 | DIELECTRIC, CAPACITOR USING DIELECTRIC, SEMICONDUCTOR DEVICE USING DIELECTRIC, AND MANUFACTURING METHOD OF DIELECTRIC - To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced. | 2010-12-23 |
20100320521 | Semiconductor device - A semiconductor device according to an exemplary embodiment of the present invention includes a memory cell including an information storage portion including a capacitor upper electrode of a DRAM cell and a capacitor lower electrode formed below the upper electrode and an access transistor for controlling access to the information storage portion, a bit-line connected to the access transistor to write or read data to or from the information storage portion, a word line connected to a gate electrode of the access transistor to control the access transistor, and a capacitive element including an upper electrode made from a same layer as a first metal line formed above the capacitor upper electrode and a lower electrode made from a same layer as the capacitor upper electrode, the capacitive element being formed outside an area where the memory cell is formed. | 2010-12-23 |
20100320522 | Semiconductor device - A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films. | 2010-12-23 |
20100320523 | FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching. | 2010-12-23 |
20100320524 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. The second insulating film may be a laminated multi-layered insulator featuring a non-conductive charge trap film as an intermediate layer therein which is made of a silicon nitride film. | 2010-12-23 |
20100320525 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: fin-shaped control gate electrodes formed on an insulating layer; and a body layer having a channel region arranged to cross the control gate electrodes and embedded in the control gate electrodes sequentially via a first insulating layer, a charge storage layer, and a second insulating layer. | 2010-12-23 |
20100320526 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor. | 2010-12-23 |
20100320527 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction. | 2010-12-23 |
20100320528 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - In a three-dimensional semiconductor memory device, the device includes a semiconductor substrate having a recessed region, an active pattern extending in a direction transverse to the recessed region, an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region, and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate. The active pattern is disposed between the insulating pillar and the lower select gate. | 2010-12-23 |
20100320529 | INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor. | 2010-12-23 |
20100320530 | METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH - Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described. | 2010-12-23 |
20100320531 | STANDING CHIP SCALE PACKAGE - A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed. | 2010-12-23 |
20100320532 | TRENCH GATE MOSFET AND METHOD OF MANUFACTURING THE SAME - A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region ( | 2010-12-23 |
20100320533 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 2010-12-23 |
20100320534 | Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices - A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench. | 2010-12-23 |
20100320535 | TRANSISTOR COMPONENT HAVING AN AMORPHOUS CHANNEL CONTROL LAYER - Disclosed is a semiconductor component, including: a drift zone arranged between a first and a second connection zone; a channel control layer of an amorphous semi-insulating material arranged adjacent to the drift zone. | 2010-12-23 |
20100320536 | TRANSISTOR COMPONENT HAVING AN AMORPHOUS SEMI-ISOLATING CHANNEL CONTROL LAYER - Disclosed is a transistor component having a control structure with a channel control layer of an amorphous semiconductor insulating material extending in a current flow direction along a channel zone. | 2010-12-23 |
20100320537 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode. | 2010-12-23 |
20100320538 | Semiconductor device - The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET. | 2010-12-23 |
20100320539 | Semiconductor device with electrostatic protection device - A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively. The fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of the N-channel FET and the P-channel FET, respectively. At least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device. | 2010-12-23 |
20100320540 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 2010-12-23 |
20100320541 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block. | 2010-12-23 |
20100320542 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To improve the performance of a CMISFET having a high-k gate insulating film and a metal gate electrode. An n-channel MISFET has, over the surface of a p-type well of a semiconductor substrate, a gate electrode formed via a first Hf-containing insulating film serving as a gate insulating film, while a p-channel MISFET has, over the surface of an n-type well, another gate electrode formed via a second Hf-containing insulating film serving as a gate insulating film. These gate electrodes have a stack structure of a metal film and a silicon film thereover. The first Hf-containing insulating film is an insulating material film comprised of Hf, a rare earth element, Si, O, and N or comprised of Hf, a rare earth element, Si, and O, while the second Hf-containing insulating film is an insulating material film comprised of Hf, Al, O, and N or comprised of Hf, Al, and O. | 2010-12-23 |
20100320543 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 2010-12-23 |
20100320544 | METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor. | 2010-12-23 |
20100320545 | PLANAR AND NON-PLANAR CMOS DEVICES WITH MULTIPLE TUNED THRESHOLD VOLTAGES - A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material. | 2010-12-23 |
20100320546 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 2010-12-23 |
20100320547 | SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC - A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y M | 2010-12-23 |
20100320548 | Silicon-Rich Nitride Etch Stop Layer for Vapor HF Etching in MEMS Device Fabrication - A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C.). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process. | 2010-12-23 |
20100320549 | Methods and Apparatuses for Integrated Packaging of Microelectromechanical Devices - Microelectromechanical systems (MEMS) packages, packaged MEMS devices, and methods for making the same are disclosed. The method may include forming a chamber sacrificial layer above an insulating layer that is coupled to a wafer. The method further may include forming a packaging layer above the chamber sacrificial layer. The method additionally may include forming one or more openings through the packaging layer. The method also may include removing the chamber sacrificial layer through the one or more openings. The method may include forming a sealing layer above the packaging layer such that the sealing layer substantially seals the one or more openings to form a hermetic cavity. | 2010-12-23 |
20100320550 | Spin-Torque Magnetoresistive Structures with Bilayer Free Layer - Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a ferromagnetic layer, a ferrimagnetic layer coupled to the ferromagnetic layer, a pinned layer and a nonmagnetic spacer layer. A free side of the magnetoresistive structure comprises the ferromagnetic layer and the ferrimagnetic layer. The nonmagnetic spacer layer is at least partly between the free side and the pinned layer. A saturation magnetization of the ferromagnetic layer opposes a saturation magnetization of the ferrimagnetic layer. The nonmagnetic spacer layer may include a tunnel barrier layer, such as one composed of magnesium oxide (MgO), or a nonmagnetic metal layer. | 2010-12-23 |
20100320551 | Magnetoresistive Random Access Memory with Improved Layout Design and Process Thereof - A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and the conductive layers. Thus, a conventional deep tungsten plug process, interconnecting two conductive layers, is eliminated. | 2010-12-23 |
20100320552 | CMOS Image Sensor - The present invention discloses a CMOS image sensor comprising: a substrate; a photo diode formed in the substrate; an interconnection formed on the substrate, wherein the portions of the interconnection are insulated from one another by a dielectric material; a light passage penetrating through at least part of the dielectric material; a micro lens above the light passage; and a color filter above the micro lens. | 2010-12-23 |
20100320553 | ILLUMINATED FINGER SENSOR ASSEMBLY AND RELATED METHODS - A finger sensor assembly may include a circuit board and an integrated circuit (IC) finger sensor grid array package including a grid array on a lower end thereof mounted to the circuit board, and a finger sensing area on an upper end thereof. The finger sensor assembly may further include at least one visible light source carried by the circuit board and a visible light guide optically coupled to the at least one visible light source. The at least one visible light source may at least partially laterally surround the upper end of the IC finger sensor grid array package to provide visual light indications. The IC finger sensor grid array package may also include circuitry for controlling the at least one visible light source. | 2010-12-23 |
20100320554 | METHOD OF MANUFACTURING SOLID STATE IMAGING DEVICE, AND SOLID STATE IMAGING DEVICE - Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment. | 2010-12-23 |
20100320555 | CONTROLLING ELECTROMECHANICAL BEHAVIOR OF STRUCTURES WITHIN A MICROELECTROMECHANICAL SYSTEMS DEVICE - In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device. | 2010-12-23 |
20100320556 | CONTINUOUS LARGE AREA IMAGING AND DISPLAY ARRAYS USING READOUT ARRAYS FABRICATED IN SILICON-ON-GLASS SUBSTRATES - A vertically-integrated image sensor is proposed with the performance characteristics of single crystal silicon but with the area coverage and cost of arrays fabricated on glass. The image sensor can include a backplane array having readout elements implemented in silicon-on-glass, a frontplane array of photosensitive elements vertically integrated above the backplane, and an interconnect layer disposed between the backplane array and the image sensing array. Since large area silicon-on-glass backplanes are formed by tiling thin single-crystal silicon layers cleaved from a thick silicon wafer side-by-side on large area glass gaps between the tiled silicon backplane would normally result in gaps in the image captured by the array. Therefore, embodiments further propose that the pixel pitch in both horizontal and vertical directions of the frontplane be larger than the pixel pitch of the backplane, with the pixel pitch difference being sufficient that the frontplane bridges the gap between backplane tiles. | 2010-12-23 |
20100320557 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having an anode of a Si-FRD and a cathode of a Si-SBD which are serially connected. The Si-SBD has a junction capacitance whose amount of accumulable charge is equal to or more than an amount of charge occurring at the time of reverse recovery of the Si-FRD, and has a lower breakdown voltage than the Si-FRD does. | 2010-12-23 |
20100320558 | CIRCUIT LAYOUT STRUCTURE AND METHOD TO SCALE DOWN IC LAYOUT - A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different. | 2010-12-23 |
20100320559 | SEMICONDUCTOR DEVICE INCLUDING INDEPENDENT ACTIVE LAYERS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects. | 2010-12-23 |
20100320560 | Metallic Bump Structure Without Under Bump Metallurgy And a Manufacturing Method Thereof - The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed. | 2010-12-23 |
20100320561 | Method for forming a one-time programmable metal fuse and related structure - According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure. | 2010-12-23 |
20100320562 | SEMICONDUCTOR DEVICE - The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. | 2010-12-23 |
20100320563 | ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element. | 2010-12-23 |
20100320564 | NANOWIRE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes. | 2010-12-23 |
20100320565 | WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER - A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV. | 2010-12-23 |
20100320566 | Semiconductor constructions - The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices. | 2010-12-23 |
20100320567 | INTEGRATED CIRCUIT COMPRISING A CAPACITOR WITH METAL ELECTRODES AND PROCESS FOR FABRCATING SUCH A CAPACITOR - An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes ( | 2010-12-23 |
20100320568 | SEMICONDUCTOR DEVICE, RF-IC AND MANUFACTURING METHOD OF THE SAME - Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region. | 2010-12-23 |
20100320569 | CARBON NANOTUBE RESISTOR, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a fist electrode and a second electrode, wherein the first concentration is 1(E10 | 2010-12-23 |
20100320570 | SEMICONDUCTOR DEVICE - The present invention includes a memory cell area that includes a plurality of transistors, and a core area that is arranged adjacent to the memory cell area. The memory cell area and the core area include a semiconductor layer, and an n-type well region and a first p-type well region formed above the semiconductor layer. The memory cell area further includes a second p-type well region formed under the n-type well region and the first p-type well region in the semiconductor layer. The second p-type well region contacts to at least the first p-type well region. | 2010-12-23 |
20100320571 | BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY - A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure. | 2010-12-23 |
20100320572 | Thin-Body Bipolar Device - A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively. | 2010-12-23 |
20100320573 | ORGANOSILANE POLYMERS, HARDMASK COMPOSITIONS INCLUDING THE SAME AND METHODS OF PRODUCING SEMICONDUCTOR DEVICES USING ORGANOSILANE HARDMASK COMPOSITIONS - Provided herein, according to some embodiments of the invention, are organosilane polymers prepared by reacting organosilane compounds including | 2010-12-23 |
20100320574 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. | 2010-12-23 |
20100320575 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 2010-12-23 |
20100320576 | Die-warpage compensation structures for thinned-die devices, and methods of assembling same - A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die. | 2010-12-23 |
20100320577 | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure - A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die. | 2010-12-23 |
20100320578 | PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING THE SAME - A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material. | 2010-12-23 |
20100320579 | Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds - A leadframe for the assembly of a semiconductor chip has regions ( | 2010-12-23 |
20100320580 | EQUIPOTENTIAL PAD CONNECTION - A conduction member is used to connect in-chip equipotential pads | 2010-12-23 |
20100320581 | Semiconductor device - The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out. | 2010-12-23 |
20100320582 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect shorter than the outer interconnect over the base circuit assembly, the inner interconnect over the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and an end of the outer interconnect. | 2010-12-23 |
20100320583 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base conductive material on opposite sides of the base substrate; connecting an internal interconnect having a substantially spherical shape on the base substrate; forming a top substrate having a top conductive material on opposite sides of the top substrate with an upper component thereon facing the base substrate; and attaching the top substrate on the internal interconnect. | 2010-12-23 |
20100320584 | SEMICONDUCTOR CHIP LAMINATED BODY - A semiconductor chip laminated body includes a wiring board having a connecting terminal; a plurality of semiconductor chips laminated on the wiring board, each of the semiconductor chips having a pad; conductive connecting members having first end parts connected to the pads of the corresponding semiconductor chips and second end parts projecting from side surfaces of the corresponding semiconductor chips; and a conductive member configured to connect the connecting terminal of the wiring board and the second end parts of the conductive connecting members; wherein conductive materials are exposed at the side surfaces of the semiconductor chips; and a gap is provided between the side surfaces of the semiconductor chips and the conductive member. | 2010-12-23 |
20100320585 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 2010-12-23 |
20100320586 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a base component to the substrate by a first interconnect; attaching a stack component connected by a second interconnect to the substrate and partially over the base component, the second interconnect different from the first interconnect; molding an encapsulation over the base component, the first interconnect, the stack component, and the second interconnect; and removing the substrate to partially expose the first interconnect and the second interconnect from the encapsulation. | 2010-12-23 |
20100320587 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a device having a conductor with ends exposed on opposite sides of the device; forming a first surface depression on the device around the conductor; connecting a first component over the conductor and surrounded by the first surface depression; and applying a first underfill between the first component and the device, the first underfill substantially filled within a perimeter of the first surface depression. | 2010-12-23 |
20100320588 | Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die - A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated. | 2010-12-23 |
20100320589 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMPS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base strip having a base top side; forming a terminal body with a substantially spherical shape partially in the base strip; attaching a device adjacent the terminal body and over the base top side, a device mount side of the device below a top portion of the terminal body; attaching a device connector to the device and the top portion of the terminal body; applying an encapsulant over the device connector, the device, and the top portion of the terminal body; and removing the base strip providing the terminal body partially exposed from the encapsulant. | 2010-12-23 |
20100320590 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADFRAME HAVING RADIAL-SEGMENTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing inwardly converging leadfingers having continuously decreasing widths along lengths thereof to inward ends thereof; electrically connecting an integrated circuit device on the leadfingers only on portions of the continuously decreasing widths; and encapsulating the integrated circuit device and the leadfingers with an encapsulation. | 2010-12-23 |
20100320591 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: attaching contact pads to a base structure; connecting a base die to the base structure; connecting a supporting die over the base die by conductive balls to the contact pads on two sides of the base die; encapsulating the contact pads, the base die, the supporting die, and the conductive balls; and removing the base structure. | 2010-12-23 |
20100320592 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device in which overall thickness is reduced by suppressing the rising of a metal thin line and connection reliability is enhanced at the joint of metal thin line and other member during resin sealing. A method for manufacturing such semiconductor device is also provided. The semiconductor device ( | 2010-12-23 |
20100320593 | Chip Package Structure and Manufacturing Methods Thereof - A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit. | 2010-12-23 |
20100320594 | SEMICONDUCTOR DEVICE WITH REINFORCEMENT PLATE AND METHOD OF FORMING SAME - A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate. | 2010-12-23 |
20100320595 | HYBRID HERMETIC INTERFACE CHIP - A hermetically sealed MEMS device package comprises a MEMS device platform, a hermetic interface chip, and an outer seal ring. The MEMS device platform includes a MEMS device surrounded by a continuous outer boundary wall with a top surface. The hermetic interface chip includes a glass substrate and at least one silicon mesa. The glass substrate includes at least one hole and has a lower surface with an inner portion surrounded by an outer portion. The at least one silicon mesa is bonded to the inner portion of the lower surface of the glass substrate, such that the at least one silicon mesa is aligned with the at least one hole in the glass substrate. The outer seal ring bonds the outer portion of the lower surface of the glass substrate to the top surface of the continuous outer boundary wall of the MEMS device platform. | 2010-12-23 |
20100320596 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process. | 2010-12-23 |