51st week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210398918 | CHIP OR SYSTEM-IN-PACKAGE PROTECTION USING THE GMI EFFECT - Device of the chip or electronic system-in-package type, comprising at least one element for protecting at least part of at least one face of the device, said protective element comprising at least:
| 2021-12-23 |
20210398919 | PROTECTION OF INTEGRATED CIRCUITS - A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut. | 2021-12-23 |
20210398920 | Method and System for Improved Noise Isolation in an Electrostatic Discharge Protection Scheme - An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise. | 2021-12-23 |
20210398921 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate. | 2021-12-23 |
20210398922 | ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT ASSEMBLY CONNECTORS - Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly. | 2021-12-23 |
20210398923 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure. | 2021-12-23 |
20210398924 | SEMICONDUCTOR PACKAGES INCLUDING ANTENNA PATTERN - A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip. | 2021-12-23 |
20210398925 | MANUFACTURING METHOD OF THE CHIP PACKAGE STRUCTURE - A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip. | 2021-12-23 |
20210398926 | SEMICONDUCTOR PACKAGE HAVING ENLARGED GATE PAD AND METHOD OF MAKING THE SAME - A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface. | 2021-12-23 |
20210398927 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion. | 2021-12-23 |
20210398928 | BONDED BODY, CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE - A bonded body according to an embodiment includes a substrate, a metal member, and a bonding layer. The bonding layer is provided between the substrate and the metal member. The bonding layer includes a first particle including carbon, a first region including a metal, and a second region including titanium. The second region is provided between the first particle and the first region. A concentration of titanium in the second region is greater than a concentration of titanium in the first region. | 2021-12-23 |
20210398929 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern. | 2021-12-23 |
20210398930 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate. | 2021-12-23 |
20210398931 | CONNECTION STRUCTURE - A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite. | 2021-12-23 |
20210398932 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure, including steps of providing a first substrate, and forming a first bonding layer on a surface of the first substrate, wherein a material of the first bonding layer includes dielectric material of silicon, nitrogen and carbon. | 2021-12-23 |
20210398933 | ELECTRONIC DEVICE AND DISPLAY DEVICE USING THE SAME - An electronic device which connects a circuit film to a display panel by applying a conductive material to the insides of holes formed in the circuit film, so as to improve reliability of bonding, and a display device using the same, are discussed. | 2021-12-23 |
20210398934 | SENSOR PACKAGE STRUCTURE - A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer. | 2021-12-23 |
20210398935 | CHIP BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE APPARATUS - A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity. | 2021-12-23 |
20210398936 | LASER BONDED DEVICES, LASER BONDING TOOLS, AND RELATED METHODS - In one example, a system can comprise a laser assisted bonding (LAB) tool comprising a stage block and a laser source facing the stage block. The stage block can be configured to support a first substrate and a first electronic component coupled with the first substrate, the first electronic component comprising a first interconnect. The laser source can be configured to emit a first laser towards the stage block to induce a first heat on the first interconnect to bond the first interconnect with the first substrate. Other examples and related methods are also disclosed herein. | 2021-12-23 |
20210398937 | SOLDER REFLOW OVEN FOR BATCH PROCESSING - A solder reflow oven may include a reflow chamber and a plurality of vertically spaced apart wafer-support plates positioned in the reflow chamber. A plurality of semiconductor wafers each including a solder are configured to be disposed in the reflow chamber such that each semiconductor wafer is disposed proximate to, and vertically spaced apart from, a wafer-support plate. Each wafer-support plate may include at least one of liquid-flow channels or resistive heating elements. A control system control the flow of a hot liquid through the channels or activate the heating elements to heat a wafer to a temperature above the solder reflow temperature. | 2021-12-23 |
20210398938 | Uniform Pressure Gang Bonding Method - A uniform pressure gang bonding device and fabrication method are presented using an expandable upper chamber with an elastic surface. Typically, the elastic surface is an elastomer material having a Young's modulus in a range of 40 to 1000 kilo-Pascal (kPA). After depositing a plurality of components overlying a substrate top surface, the substrate is positioned over the lower plate, with the top surface underlying and adjacent (in close proximity) to the elastic surface. The method creates a positive upper chamber medium pressure differential in the expandable upper chamber, causing the elastic surface to deform. For example, the positive upper chamber medium pressure differential may be in the range of 0.05 atmospheres (atm) and 10 atm. Typically, the elastic surface deforms between 0.5 millimeters (mm) and 20 mm, in response to the positive upper chamber medium pressure differential. | 2021-12-23 |
20210398939 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a display device includes preparing a circuit board including a drive circuit for driving a LED chip, forming a connecting electrode on the circuit board, forming an adhesive layer on the connecting electrode, adhering a terminal electrode of the LED chip on the adhesive layer and joining the connecting electrode and the terminal electrode by irradiating a laser light. The adhesive layer may be formed only on a upper surface of the connecting electrode. | 2021-12-23 |
20210398940 | HYBRID BONDING INTERCONNECTION USING LASER AND THERMAL COMPRESSION - In one example, a method to manufacture a semiconductor device comprises providing an electronic component over a substrate, wherein an interconnect of the electronic component contacts a conductive structure of the substrate, providing the substrate over a laser assisted bonding (LAB) tool, wherein the LAB tool comprises a stage block with a window, and heating the interconnect with a laser beam through the window until the interconnect is bonded with the conductive structure. Other examples and related methods are also disclosed herein. | 2021-12-23 |
20210398941 | DIE INTERCONNECT SUBSTRATES, A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A DIE INTERCONNECT SUBSTRATE - Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height. | 2021-12-23 |
20210398942 | INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another. | 2021-12-23 |
20210398943 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures. | 2021-12-23 |
20210398944 | EM AND RF MITIGATION SILICON STRUCTURES IN STACKED DIE MICROPROCESSORS FOR DIE TO PLATFORM AND DIE-DIE RF NOISE SUPPRESSION - Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die. | 2021-12-23 |
20210398945 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS - A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described. | 2021-12-23 |
20210398946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes. | 2021-12-23 |
20210398947 | CHIP-STACKED SEMICONDUCTOR PACKAGE WITH INCREASED PACKAGE RELIABILITY - A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip. | 2021-12-23 |
20210398948 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode. | 2021-12-23 |
20210398949 | MEMORY DEVICE INCLUDING MODULAR MEMORY UNITS AND MODULAR CIRCUIT UNITS FOR CONCURRENT MEMORY OPERATIONS - An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings. | 2021-12-23 |
20210398950 | SEMICONDUCTOR PACKAGE AND PRODUCTION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads. | 2021-12-23 |
20210398951 | SEMICONDUCTOR DEVICE - A semiconductor device includes: multiple semiconductor elements each having a one surface and a rear surface in a plate thickness direction; a first member that sandwiches the multiple semiconductor elements and is electrically connected to an electrode on the one surface; a second member electrically connected to an electrode on the rear surface; and multiple terminals that are continuous from the first or second member. An area of the second member is smaller than that of the first member. Semiconductor elements are arranged in a longitudinal direction of the second member. The semiconductor device further includes a first joint portion that electrically connects each semiconductor element and the second member and a second joint portion that electrically connects a terminal and the second member. The multiple solder joint portions are symmetrically placed. | 2021-12-23 |
20210398952 | MICRO LIGHT EMITTING DIODE DISPLAY PANEL, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE - The present disclosure provides a micro light emitting diode display panel, a method for fabricating the same, and a display device comprising the same. The micro light emitting diode display panel includes an active layer, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, a pixel electrode, a micro light emitting diode, and a gate insulating layer covering the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode. The light shielding layer blocks light emitted by the micro light emitting diode from being incident on the thin film transistor, thereby reducing influence of the light emitted by the micro light emitting diode light on the thin film transistor. | 2021-12-23 |
20210398953 | DISPLAY PANEL AND HEAD MOUNTED DEVICE - The present invention discloses a display panel and a head mounted device. The display panel includes a substrate and a plurality of micro light emitting units. A first position and a second position are defined at an edge and a center of the substrate respectively. The micro light emitting units are arranged and disposed on the substrate. Any two of the micro light emitting units are disposed at the first position and the second position respectively. Wherein each micro light emitting unit defines a luminating top surface, and a reference angle is defined between each luminating top surface and a reference plane respectively. Wherein the reference angle defined between each luminating top surface and the reference plane gradually decreases from the first position to the second position, and the luminating top surface of the micro light emitting unit located at the second position is parallel to the reference surface. | 2021-12-23 |
20210398954 | LED DISPLAY UNIT GROUP AND DISPLAY PANEL - Provided is an LED display unit group, comprising: an insulation substrate, a front circuit board, and a back circuit board. The front circuit board is divided into pixel areas arranged in an array of 2m rows and 2n columns. Each pixel area comprises three A-electrode pads, three LED light-emitting chips of different light emission colors, and B-electrode pads corresponding to the three LED light-emitting chips. In each pixel area, the electrode A of each LED light-emitting chip is electrically connected to a corresponding A-electrode pad, and the electrode B of each LED light-emitting chip is electrically connected to a corresponding B-electrode pad. In the same column of pixel areas, B-electrode pads corresponding to all LED light-emitting chips are electrically connected to each other. In the same row of pixel areas, A-electrode pads corresponding to LED light-emitting chips of the same light emission color are electrically connected to each other. | 2021-12-23 |
20210398955 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - An array substrate is provided. In the array substrate, an organic material layer includes a first planar portion, a bending portion and a second planar portion which are connected in sequence. The first planar portion and the second planar portion are disposed on both sides of a base substrate. A lead structure includes a first lead portion, a bent lead portion and a second lead portion which are connected in sequence, wherein the first lead portion is disposed outside the first plane portion, the bent lead portion is disposed outside the bending portion, and the second lead portion is disposed outside the second plane portion. An LED layer and a control circuit are respectively disposed on the both sides of the base substrates. | 2021-12-23 |
20210398956 | LIGHT EMITTING ELEMENT DISPERSANT, LIGHT EMITTING ELEMENT INK COMPRISING THE SAME, AND METHOD OF MANUFACTURING DISPLAY DEVICE - The invention relates to a light-emitting element dispersing agent; a light-emitting element ink comprising the same; and a method for producing a display device. This method for producing a display device may comprise spraying an ink including a solvent, light emitting elements, and a light emitting element dispersant onto a target substrate provided with a first electrode and a second electrode, applying a voltage to the first electrode and the second electrode to generate an electric field on the target substrate, irradiating the ink sprayed on the target substrate with light to form a dispersant fragment in which the light emitting element dispersant is decomposed, and removing the solvent and the dispersant fragment of the ink. | 2021-12-23 |
20210398957 | THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH PASSIVE ELEMENTS FORMED BY HYBRID BONDING - A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias. | 2021-12-23 |
20210398958 | SOLID STATE SWITCHING DEVICE INCLUDING NESTED CONTROL ELECTRONICS - A solid state switching device, such as a solid state circuit breaker, includes at least one heat sink, a control electronics printed circuit board (PCB), and power electronics. The power electronics are useful to regulate the flow of current from one terminal of the solid state switching device to another terminal. The power electronics can include one or more solid state devices such as FETs, Thyristors, Thyristors+SiC JFET in parallel, IGBTs, and IGCTs. The control PCB can include a variety of circuit elements useful to perform the function of a gate driver useful to activate the solid state device of the power electronics. The heat sink includes one or more signal vias formed therethrough to permit nesting of the control PCB within the heat sink. | 2021-12-23 |
20210398959 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present application provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a first glass substrate, a thin-film transistor layer disposed on the first glass substrate, black matrices disposed on the thin-film transistor layer and arranged in an array, first color micro light-emitting diodes (LEDs) disposed on the thin-film transistor layer and disposed between the black matrices, a pixel layer disposed on the first color micro LEDs, and a second glass substrate disposed on the black matrices and the pixel layer. | 2021-12-23 |
20210398960 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A display panel, a manufacturing method thereof, and a display device are provided. The display panel includes a driving backplate, functional component groups, and micro-LED chips. The functional component groups are integrated in regions where the micro-LED chips are not disposed and are multiplexed as alignment marks. In a mass transfer process of the micro-LED chips, the alignment marks are prevented from additionally occupying pixel space by using part of functional components multiplexed as the alignment marks under a precondition of ensuring alignment accuracy. | 2021-12-23 |
20210398961 | High Density Optical Interconnection Assembly - A high density opto-electronic interconnection arrangement includes an interposer disposed over the substrate and used to provide a high density electrical connection to a group of electrical ICs flip-chip mounted on the substrate. A set of optical ICs are disposed over and attached to the electrical ICs, where the positioning of the optical IC on the top of the stack eliminates the need to form vias through the thickness of the optical substrate. Thus, a relatively thick optical IC component may be used, providing a stable optical axis and improving alignment and coupling of optical signal paths. | 2021-12-23 |
20210398962 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a first switching element, a second switching element, an optical coupling element, a plurality of leads and an outer resin member. The first switching element includes a first semiconductor chip and a first inner resin member sealing the first semiconductor chip. The second switching element includes a second semiconductor chip and a second inner resin member sealing the second semiconductor chip. The optical coupling element includes a light-emitting element, a light-receiving element and a third inner resin member sealing the light-emitting element and the light-receiving element. The first and second switching element and the optical coupling element are provided with terminals projecting from the first to third inner resin member, and the plurality of leads are electrically connected to the terminals. The outer resin member seals the first and second switching elements, the optical coupling element, and the plurality of leads. | 2021-12-23 |
20210398963 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a driving substrate and a first light emitting diode element. The driving substrate has a plurality of driving structures. Each of the driving structures includes a first pad, a second pad, a third pad and a fourth pad. The plurality of driving structures include a first driving structure. The first light emitting diode element is electrically connected to a first pad and a second pad of the first driving structure, and the first light emitting diode element crosses a line connecting a third pad and a fourth pad of the first driving structure. A manufacturing method of the display apparatus is also provided. | 2021-12-23 |
20210398964 | INTERNAL THERMAL TRANSFER FOR MEMORY DEVICE - Apparatuses, systems, and methods are presented for data storage with internal thermal transfer. A plurality of memory elements may be disposed within a thermally conductive housing. A controller may be disposed within the housing and thermally connected to the housing. A heat spreader may be thermally connected to the housing and to the plurality of memory elements, and not thermally connected to the controller. | 2021-12-23 |
20210398965 | DISPLAY MODULE AND ELECTRONIC DEVICE - A display module and an electronic device are provided. The display module includes a substrate, a display part, a driving chip, a flexible circuit, and a buffer part. The substrate includes a soldering portion. The display part is disposed on a light emitting side of the substrate. The driving chip is disposed on a light emitting side of the soldering portion. The flexible circuit board is bent from a first surface of the soldering portion to a second surface of the soldering portion. The buffer part is disposed between the flexible circuit board and the soldering portion. | 2021-12-23 |
20210398966 | THERMAL SPREADING MANAGEMENT OF 3D STACKED INTEGRATED CIRCUITS - An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die. | 2021-12-23 |
20210398967 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED BASE STRUCTURES FOR MICROELECTRONIC DEVICES - A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described. | 2021-12-23 |
20210398968 | ELECTROSTATIC DISCHARGE AND OVERDRIVE PROTECTION CIRCUITRY - Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters. | 2021-12-23 |
20210398969 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring. | 2021-12-23 |
20210398970 | ELECTROSTATIC PROTECTION CIRCUIT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - An electrostatic protection circuit and a manufacturing method thereof, an array substrate, and a display device are provided. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. | 2021-12-23 |
20210398971 | INTEGRATION OF MULTIPLE DISCRETE GAN DEVICES - Examples of integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane. | 2021-12-23 |
20210398972 | INTEGRATING A GATE-ALL-AROUND (GAA) TRANSISTOR WITH A SILICON GERMANIUM (SiGe) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) - Certain aspects of the present disclosure generally relate to a semiconductor device with a heterojunction bipolar transistor (HBT) integrated with a gate-all-around (GAA) transistor. One example semiconductor device generally includes a first substrate, a second substrate adjacent to the first substrate, a GAA transistor disposed above the first substrate, and a HBT disposed above the second substrate. Other aspects of the present disclosure generally relate to a method for fabricating a semiconductor device. An exemplary fabrication method generally comprises forming a GAA transistor disposed above a first substrate and forming a HBT disposed above a second substrate, wherein the second substrate is adjacent to the first substrate. | 2021-12-23 |
20210398973 | METHODS OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure includes: forming an interconnect structure over a substrate; forming a pad over the interconnect structure, wherein the pad is electrically connected to the interconnect structure; forming a bonding dielectric layer over the interconnect structure; and forming a bonding metal layer in the bonding dielectric layer to electrically connect to the interconnect structure, wherein the bonding metal layer includes a via plug and a metal feature formed over the via plug, a height of the metal feature is greater than or equal to a height of the via plug. | 2021-12-23 |
20210398974 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure. | 2021-12-23 |
20210398975 | METAL GATE STRUCTURE AND METHODS THEREOF - Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer. | 2021-12-23 |
20210398976 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structure is provided. The semiconductor structure includes a substrate including device regions and an isolation region located adjacent to and between the device regions; a fin on the substrate; gate structures across the fin at the device regions; source/drain doped regions in the fin at two sides of each of the gate structures; a first opening in the fin at the isolation region; and an insulation structure located in the first opening. Two opposite sidewalls of the first opening are respectively in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions. | 2021-12-23 |
20210398977 | DOUBLE-SIDED INTEGRATED CIRCUIT TRANSISTOR STRUCTURES WITH DEPOPULATED BOTTOM CHANNEL REGIONS - Integrated circuitry comprising interconnect metallization on both front and back sides of a gate-all-around (GAA) transistor structure lacking at least one active bottom channel region. Bottom channel regions may be depopulated from a GAA transistor structure following removal of a back side substrate that exposes an inactive portion of a semiconductor fin. During back-side processing, one or more bottom channel region may be removed or rendered inactive through dopant implantation. Back-side processing may then proceed with the interconnection of one or more terminal of the GAA transistor structures through one or more levels of back-side interconnect metallization. | 2021-12-23 |
20210398978 | SEMICONDUCTOR DEVICES INCLUDING WORK FUNCTION LAYERS - A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer. | 2021-12-23 |
20210398979 | TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE - Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications. | 2021-12-23 |
20210398980 | Multi-Die Fine Grain Integrated Voltage Regulation - A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. | 2021-12-23 |
20210398981 | Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor - Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side. | 2021-12-23 |
20210398982 | MEMORY STURCTURE AND MANUFACTURING METHOD THEREFOR - A memory structure including a substrate, a bit line structure, a contact structure, and a capacitor structure is provided. The bit line structure is located on the substrate. The contact structure is located on the substrate on one side of the bit line structure. The capacitor structure is located on the contact structure. The capacitor structure includes a first electrode, a second electrode, and an insulating layer. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is only located on a part of the contact structure. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. | 2021-12-23 |
20210398983 | DRAM AND MANUFACTURING METHOD THEREFORE - A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer. | 2021-12-23 |
20210398984 | METHOD FOR FORMING MEMORY AND MEMORY - A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures. | 2021-12-23 |
20210398985 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer. | 2021-12-23 |
20210398986 | MEMORY DEVICE - A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein. | 2021-12-23 |
20210398987 | MICROELECTRONIC DEVICES WITH TIER STACKS WITH VARIED TIER THICKNESSES, AND RELATED METHODS AND SYSTEMS - Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed. | 2021-12-23 |
20210398988 | SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. | 2021-12-23 |
20210398989 | MEMORY DEVICE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE - A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure. | 2021-12-23 |
20210398990 | FERROELECTRIC TUNNEL JUNCTION DEVICES WITH METAL-FE INTERFACE LAYER AND METHODS FOR FORMING THE SAME - A memory device, transistor, and methods of making the same, the memory device including a memory device including: a ferroelectric (FE) structure including: a dielectric layer, an FE layer disposed on the dielectric layer, and an interface metal layer disposed on the FE layer, in which the interface metal layer comprises W, Mo, Ru, TaN, or a combination thereof to induce the FE layer to have an orthorhombic phase; and a top electrode layer disposed on the interface metal. | 2021-12-23 |
20210398991 | FERROELECTRIC TUNNEL JUNCTION MEMORY DEVICE USING A MAGNESIUM OXIDE TUNNELING DIELECTRIC AND METHODS FOR FORMING THE SAME - A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer. | 2021-12-23 |
20210398992 | SEMICONDUCTOR STRUCTURE HAVING MEMORY DEVICE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode. | 2021-12-23 |
20210398993 | MEMORY CELLS WITH FERROELECTRIC CAPACITORS SEPARATE FROM TRANSISTOR GATE STACKS - Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode. | 2021-12-23 |
20210398994 | GATED FERROELECTRIC MEMORY CELLS FOR MEMORY CELL ARRAY AND METHODS OF FORMING THE SAME - A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel. | 2021-12-23 |
20210398995 | Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate - A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material. | 2021-12-23 |
20210398996 | MICROELECTRONIC DEVICES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described. | 2021-12-23 |
20210398997 | MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS - A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described. | 2021-12-23 |
20210398998 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern. | 2021-12-23 |
20210398999 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer. | 2021-12-23 |
20210399000 | METHODS OF SEMICONDUCTOR DEVICE FABRICATION - Aspects of the disclosure provide a method to manufacture a semiconductor device. The method includes filling a sacrificial layer in a first via of a first stack. An initial top CD is larger than an initial bottom CD of the first via. A second stack is formed along a vertical direction over the first stack. A third stack is formed along the vertical direction over the second stack. The first stack, the second stack, and the third stack include alternating insulating layers and gate layers. The insulating layers of the second stack etch at a faster rate than the insulating layers of the third stack and the gate layers of the second stack etch at a faster rate than the gate layers of the third stack. A first via, a second via, and a third via are formed in the first stack, the second stack, and the third stack, respectively. | 2021-12-23 |
20210399001 | MEMORY CELL STRUCTURE OF A THREE-DIMENSIONAL MEMORY DEVICE - Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction. | 2021-12-23 |
20210399002 | SELF-ALIGNED FRONT-END CHARGE TRAP FLASH MEMORY CELL AND CAPACITOR DESIGN FOR INTEGRATED HIGH-DENSITY SCALED DEVICES - Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size. | 2021-12-23 |
20210399003 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes a peripheral circuit structure, a cell array structure above the peripheral circuit structure, and peripheral contact via structures connecting the cell array structure to the peripheral circuit structure, the peripheral contact via structures including a first peripheral contact via structure in a first through region in the peripheral circuit structure, and a second peripheral contact via structure in a second through region in the peripheral circuit structure, the second through region being spaced apart from the first through region above the peripheral circuit structure, and a difference between a second critical dimension of the second peripheral contact via structure and a first critical dimension of the first peripheral contact via structure being differently configured according to material layers included in the second through region and the first through region. | 2021-12-23 |
20210399004 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer. | 2021-12-23 |
20210399005 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction. | 2021-12-23 |
20210399006 | MICROELECTRONIC DEVICES INCLUDING A VARYING TIER PITCH, AND RELATED ELECTRONIC SYSTEMS AND METHODS - A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described. | 2021-12-23 |
20210399007 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer. | 2021-12-23 |
20210399008 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively. | 2021-12-23 |
20210399009 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel. | 2021-12-23 |
20210399010 | MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure. | 2021-12-23 |
20210399011 | CONFINED CHARGE TRAP LAYER - Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide. | 2021-12-23 |
20210399012 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed. | 2021-12-23 |
20210399013 | MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode. | 2021-12-23 |
20210399014 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers. | 2021-12-23 |
20210399015 | MEMORY DEVICES - A memory device includes a multi-layer stack. The multi-layer stack is disposed on a substrate and includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately, wherein each of the plurality of first conductive lines has a first side and a second side opposite to the first side. The memory device further includes a plurality of second conductive lines crossing over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become far away from the first side. | 2021-12-23 |
20210399016 | MEMORY DEVICE AND METHOD OF FORMING THE SAME - A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The memory material layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive lines respectively. | 2021-12-23 |
20210399017 | MEMORY DEVICE AND METHOD OF FORMING THE SAME - A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (In | 2021-12-23 |