52nd week of 2015 patent applcation highlights part 61 |
Patent application number | Title | Published |
20150372135 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor substrate, a stress providing layer formed in the semiconductor substrate between pillars and forming a junction with the semiconductor substrate below each pillar to cause lattice deformation in the pillar, a source region having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the pillar, a drain region having the second conductivity type formed in an upper portion of the pillar, a gate insulating layer formed on a lateral surface of the pillar and a surface of the stress providing layer, and a gate electrode formed to surround the lateral surface of the pillar. | 2015-12-24 |
20150372136 | Pattern Layout to Prevent Split Gate Flash Memory Cell Failure - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided. | 2015-12-24 |
20150372137 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device which is provided with: a gate insulating film which contains a high dielectric constant insulating material and has a first width; a lower gate electrode which has a second width that is narrower than the first width; an upper gate electrode which has a third width; and a first spacer layer which covers the lateral part of the upper gate electrode, a part of the lower part of the upper gate electrode, a part of the lower gate electrode, a part of the upper surface of the gate insulating film, said part of the upper surface being out of contact with the lower gate electrode, and the lateral surface of the gate insulating film. | 2015-12-24 |
20150372138 | GATE CONFIGURATION WITH STRESS IMPACT AMPLIFICATION - A gate configuration with stress impact amplification comprises an element activation zone, at least two source/drain electrodes, a first x direction poly configuration, at least two second x direction dummy poly configurations, at least two y direction dummy poly configurations and two gate electrodes. The at least two source/drain electrodes are located on the element activation zone and are paired as top-down sequence. The first x direction poly configuration is located on the element activation zone, divides the element activation zone into two equal zones and separates the at least two source/drain electrodes. The present invention disperses the stress of the contact-etch-stop-layer (CESL) to the y direction dummy poly configurations. | 2015-12-24 |
20150372139 | CONSTRAINING EPITAXIAL GROWTH ON FINS OF A FINFET DEVICE - A method includes forming at least one fin in a semiconductor substrate, forming a fin spacer on at least a first portion of the fin, the fin spacer having an upper surface, recessing the at least one fin to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer, and forming a first epitaxial material on the recessed fin, wherein a lateral extension of the epitaxial material is constrained by the fin spacer. | 2015-12-24 |
20150372140 | FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS - Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET. | 2015-12-24 |
20150372141 | SILICON-CONTAINING, TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING III-N SOURCE - Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material. | 2015-12-24 |
20150372142 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel. | 2015-12-24 |
20150372143 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. A fin type active pattern, extending in a first direction, protrudes from a substrate. A gate electrode is disposed on the fin type active pattern. The gate electrode extends in a second direction crossing the first direction. A recess region is disposed in the fin type active pattern disposed at one side of the gate electrode. The recess region includes an upper region having a first width in the first direction and a lower region having a second width smaller than the first width. A first epitaxial layer is disposed on the upper and lower regions of the recess region. A second epitaxial layer is disposed on the first epitaxial layer to fill the recess region. | 2015-12-24 |
20150372144 | Integrated Circuit Structure and Method with Solid Phase Diffusion - The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration. | 2015-12-24 |
20150372145 | HIGH DENSITY VERTICAL NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor. | 2015-12-24 |
20150372146 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor film, a first gate electrode, a second gate electrode, a first conductive film, and a second conductive film. The first gate electrode is electrically connected to the second gate electrode. The first conductive film and the second conductive film function as a source electrode and a drain electrode. The oxide semiconductor film includes a first region that overlaps with the first conductive film, a second region that overlaps with the second conductive film, and a third region that overlaps with a gate electrode and the third conductive film. The first region includes a first edge that is opposed to the second region. The second region includes a second edge that is opposed to the first region. The length of the first edge is shorter than the length of the second edge. | 2015-12-24 |
20150372147 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×10 | 2015-12-24 |
20150372148 | COMPOSITIONS FOR SOLUTION PROCESS, ELECTRONIC DEVICES FABRICATED USING THE SAME, AND FABRICATION METHODS THEREOF - Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure. | 2015-12-24 |
20150372149 | Gate Structure and Method for Fabricating the Same - An apparatus comprises a nanowire having a channel region, a gate structure surrounding a lower portion of the channel region, wherein the gate structure comprises a first dielectric layer comprising a vertical portion and a horizontal portion, a first workfunction metal layer over the first dielectric layer comprising a vertical portion and a horizontal portion and a low-resistivity metal layer over the first workfunction metal layer, wherein an edge of the low-resistivity metal layer and an edge of the vertical portion of the first workfunction metal layer are separated by a dielectric region and the low-resistivity metal layer is electrically coupled to the vertical portion of the first workfunction metal layer through the horizontal portion of the first workfunction metal layer. | 2015-12-24 |
20150372150 | Oxidizing the Source and Doping the Drain of a Thin-Film Transistor - A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain, A TFT is also provided. | 2015-12-24 |
20150372151 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p′-type polysilicon film with a high impurity concentration deposited thereon. | 2015-12-24 |
20150372152 | Semiconductor Device - A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type. | 2015-12-24 |
20150372153 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, a first semiconductor region that is formed between the first electrode and the second electrode and is in contact with the first electrode, a second semiconductor region that is formed between the first semiconductor region and the second electrode, a contact region that is formed between the second semiconductor region and the second electrode and is in contact with the second semiconductor region and the second electrode, a plurality of third semiconductor regions that are formed between the second electrode and the first semiconductor region and are in contact with the second electrode, and a wiring that is in contact with the second electrode, a portion of the wiring bonded to the second electrode being positioned above the third semiconductor region and not positioned above the contact region. | 2015-12-24 |
20150372154 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V | 2015-12-24 |
20150372155 | Controllable Integrated Capacitive Device - An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes. | 2015-12-24 |
20150372156 | SOLAR CELL MODULE MANUFACTURING METHOD - A solar cell module manufacturing method includes: applying, when applying the adhesive in a narrow and long manner in a predetermined direction on a surface of the solar cell, the adhesive such that the thickness of the adhesive from the surface has a predetermined thickness at a central portion of the solar cell and such that the thickness from the surface becomes thinner gradually in a direction from the central portion of the solar cell toward an outer edge portion of the solar cell at an end portion of the solar cell. | 2015-12-24 |
20150372157 | SOLAR CELL MODULE - An embodiment of a solar cell module is provided, comprising solar cell strings arranged side by side in a widthwise direction, each of the solar cell strings including solar cells arranged side by side in a lengthwise direction, and a wiring member electrically connecting at least some of the solar cells to each other, an interconnection wiring member electrically connecting at least some of the solar cell strings to each other, and a reflective filler member provided on back surface sides of the solar cell strings. Each of the solar cells includes a busbar electrode extending in the lengthwise direction, and a distance between the solar cells in each of the solar cell strings is larger than a distance between the solar cell strings. | 2015-12-24 |
20150372158 | SOLAR BATTERY-SEALING SHEET, SOLAR BATTERY MODULE AND METHOD FOR MANUFACTURING THE SAME - There are disclosed a pair of solar battery-sealing sheets composed of a light-receiving side-sealing sheet and a backside-sealing sheet for solar electricity generating elements of a solar battery module and reducing the coming-around of the backside-sealing sheet, wherein the melt peak temperature based on a differential scanning calorimetry (DSC) of the backside-sealing sheet is higher than the melt peak temperature based on the differential scanning calorimetry (DSC) of the light-receiving side-sealing sheet; and a solar battery module using the light-receiving side-sealing sheet and the backside-sealing sheet of the solar battery-sealing sheet, and a method for manufacturing the solar battery module. | 2015-12-24 |
20150372159 | SYSTEMS AND METHODS FOR GRAPHENE PHOTODETECTORS - Systems and methods for graphene photodetectors are disclosed herein. A device for detecting photons can include a waveguide and at least one graphene layer disposed proximate to the waveguide. An insulating layer can be disposed between the waveguide and the graphene layer. A first electrode can be connected to a first end of the graphene layer, and a second electrode can be connected to a second end of the graphene layer opposite the first end. | 2015-12-24 |
20150372160 | P-TYPE DOPANT AND METHOD FOR P-TYPE DOPING OF A SEMICONDUCTOR - A p-type dopant for a Group IV semiconductor, the p-type dopant comprising at least: a mixture of nitrogen and phosphorous configured for plasma ion implantation on the Group IV semiconductor. A method of p-type doping of a Group IV semiconductor; the method comprising the steps of: a) dissociating and ionizing a feedstock comprising a mixture of nitrogen and phosphorous a using an input power; and b) applying a bias onto a support for the Group IV semiconductor so that ions from the ionized nitrogen and phosphorous are attracted to and implanted on a surface of the Group IV semiconductor. | 2015-12-24 |
20150372161 | PHOTOVOLTAIC MODULE INCLUDING HIGH CONTACT ANGLE COATING ON ONE OR MORE OUTER SURFACES THEREOF, AND/OR METHODS OF MAKING THE SAME - Certain example embodiments of this invention relate to photovoltaic modules that include high contact angle coatings on one or more outermost major surfaces thereof, and/or associated methods. In certain example embodiments, the high contact angle coatings advantageously reduce the likelihood of electrical losses through parasitic leakage of the electrical current caused by moisture on surfaces of the photovoltaic modules, thereby potentially improving the efficiency of the photovoltaic devices. In certain example embodiments, the high contact angle coatings may be nitrides and/or oxides of or including Si, Ti, Ta, TaCr, NiCr, and/or Cr; hydrophobic DLC; and/or polymer-based coatings. The photovoltaic modules may be substrate-type modules or superstrate-type modules in different example embodiments. | 2015-12-24 |
20150372162 | SENSOR ARRAY WITH SELF-ALIGNED OPTICAL CAVITIES - A sensing device includes an array of sensing elements. Each sensing element includes a thermal infrared sensor, configured to output an electric signal in response to an intensity of infrared radiation that is incident on the sensor. An individual reflector is formed integrally with the sensor at a location separated from the sensor by one quarter wave at a selected wavelength of the infrared radiation. | 2015-12-24 |
20150372163 | NANOSTRUCTURE AND OPTICAL DEVICE INCLUDING THE NANOSTRUCTURE - Provided are a nanostructure and an optical device including the nanostructure. The nanostructure is formed on a two-dimensional material layer such as graphene and includes nanopatterns having different shapes. The nanopattern may include a first nanopattern and a second nanopattern and may be spherical; cube-shaped; or poly-pyramid-shaped, including a triangular pyramid shape; or polygonal pillar-shaped. | 2015-12-24 |
20150372164 | PHOTODETECTOR ARRANGEMENT - According to embodiments of the present invention, a photodetector arrangement is provided. The photodetector arrangement includes a plurality of germanium-based photodetectors, each germanium-based photodetector configured to receive an optical signal and to generate an electrical signal in response to the received optical signal, and an electrode arrangement arranged to conduct the electrical signals. | 2015-12-24 |
20150372165 | PHOTOELECTRIC CONVERTING ELEMENT - There is provided a photoelectric converting element in which conversion efficiency increases, by being evenly passivated. The photoelectric converting element is a photoelectric converting element that converts light to electricity, and has a silicon substrate ( | 2015-12-24 |
20150372166 | SOLAR CELL - An embodiment of a solar cell is provided comprising a silicon substrate, on a first surface of which a texture structure including mountain portions and valley portions is formed, and an amorphous silicon layer provided on the first surface of the silicon substrate. The texture structure, in a cross section passing through the mountain portions and the valley portions, includes pairs of slant portions, each pair slanting to extend from a pair of neighboring ones of the mountain portions toward the valley portion therebetween while coming closer to each other. The valley portion located between the slant portions is in a round shape with a radius of curvature of 150 nm or smaller. The amorphous silicon layer includes an epitaxial growth area grown from the valley portion, the epitaxial growth area on the valley portion is thicker than that on a region other than the valley portion. | 2015-12-24 |
20150372167 | CAPACITIVELY COUPLED ELECTRODELESS PLASMA APPARATUS AND A METHOD USING CAPACITIVELY COUPLED ELECTRODELESS PLASMA FOR PROCESSING A SILICON SUBSTRATE - There is provided a capacitive coupled electodeless plasma apparatus for processing a silicon substrate. The apparatus includes at least one inductive antenna driven by time-varying power sources for providing at least one electrostatic field; and a chamber for locating the silicon substrate. There is also provided a method for processing a silicon substrate using capacitively coupled electrodeless plasma. | 2015-12-24 |
20150372168 | Photovoltaic Device For Generating Electrical Power Using Nonlinear Multi-Photon Absorption Of Incoherent Radiation - Methods, systems, and photovoltaic devices converting broad spectrum incoherent optical power into electrical power by utilizing nonlinear multi-photon absorption and optionally enhanced by the application of magnetic fields, electric fields, or both during the power conversion process. | 2015-12-24 |
20150372169 | Solar Cell and Method of Manufacturing Same, and Solar Cell Module - A solar cell of the present invention includes a collecting electrode on one main surface of a photoelectric conversion section. The collecting electrode includes first and second electroconductive layers in this order from the photoelectric conversion section side, and an insulating layer between the first and second electroconductive layers, the insulating layer having an opening section formed therein. The first electroconductive layer is covered with the insulating layer, contains a low-melting-point material, and is conductively connected with a part of the second electroconductive layer via the opening section. The surface roughness of the second electroconductive layer is preferably 1.0 μm to 10.0 μm. The second electroconductive layer is preferably formed by a plating method. In order to conductively connect the first and second electroconductive layers, annealing of the first electroconductive layer by heating is preferably performed prior to forming the second electroconductive layer. | 2015-12-24 |
20150372170 | METHOD AND DEVICE FOR PRODUCING A SELECTIVE EMITTER STRUCTURE FOR A SOLAR CELL, SOLAR CELL - The invention relates to a method for producing a selective emitter structure ( | 2015-12-24 |
20150372171 | CONDUCTOR FOR A SOLAR CELL - The paste composition of the instant invention consists of silver powder, glass frit, Bi | 2015-12-24 |
20150372172 | PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element includes a semiconductor, an intrinsic layer disposed on the semiconductor and containing hydrogenated amorphous silicon, a first-conductivity-type layer that covers a part of the intrinsic layer and contains hydrogenated amorphous silicon of a first conductivity type, a second-conductivity-type layer that covers a part of the intrinsic layer and contains hydrogenated amorphous silicon of a second conductivity type, an insulating film covering an end region of the first-conductivity-type layer, a first electrode disposed on the first-conductivity-type layer, and a second electrode disposed on the second-conductivity-type layer. An end portion of the second-conductivity-type layer is located on the insulating film or above the insulating film. | 2015-12-24 |
20150372173 | GRADED TRANSPARENT CONDUCTING OXIDE (G-TCO) FOR THIN FILM SOLAR CELLS - A graded transparent conducting oxide (G-TCO) electrode allows the thickness of the electrode to vary from a very thin distal end to a relatively thick proximal end that resides near a metal current collector, generally for a grid of an ensemble of photovoltaic cells such that the thickness increases with the current carrying requirement of the electrode and the optical losses by the electrode are minimized. In this manner a photovoltaic cell can be improved in efficiency by the minimization of the optical losses while assuring the electrode can support all photogenerated current. The G-TCO electrode is prepared by sputtering through a mask that is suspended above a substrate, such as a photovoltaic cell absent its top electrode, where the mask does not reside on the substrate, but is suspended above the substrate. | 2015-12-24 |
20150372174 | SEMICONDUCTOR DEVICE - An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs | 2015-12-24 |
20150372175 | Vertical Pillar Structured Infrared Detector and Fabrication Method for the Same - Photodetector devices and methods for making the photodetector devices are disclosed herein. In an embodiment, the device may include a substrate; and one or more core structures, each having one or more shell layers disposed at least on a portion of a sidewall of the core structure. Each of the one or more structures extends substantially perpendicularly from the substrate. Each of the one or more core structures and the one or more shell layers form a Schottky barrier junction or a metal-insulator-semiconductor (MiS) junction. | 2015-12-24 |
20150372176 | OPTOELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An optoelectronic device comprising a substrate having a first and a second series of grooves and a channel therebetween. Each groove of the first and second series of grooves has a first and a second face and a cavity therebetween. The cavity is at least partially filled with a first semiconductor material. The first face is coated with a conductor material and the second face coated with a second semiconductor material. The channel transects the grooves of the first and second series of grooves. Also a method of producing an optoelectronic device. | 2015-12-24 |
20150372177 | SOLAR CELL MODULE - A solar cell module includes a plurality of solar cells each including a semiconductor substrate, and first electrodes and second electrodes formed on the semiconductor substrate, a plurality of lines connected to the first and second electrodes of first and second solar cells, which are positioned adjacent to each other among the plurality of solar cells, the plurality of lines using a conductive adhesive or insulated from the first and second electrodes of the first and second solar cells through an insulating layer, and a connector positioned between the first and second solar cells and connected to the plurality of lines. A width of the connector is equal to or greater than at least one of a first distance between the first solar cell and the connector or a second distance between the second solar cell and the connector. | 2015-12-24 |
20150372178 | HIGH EFFICIENCY MULTIJUNCTION SOLAR CELLS - Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed. | 2015-12-24 |
20150372179 | MULTI-JUNCTION SOLAR CELL, METHODS FOR THE PRODUCTION THEREOF, AND USES THEREOF - A multi-junction solar cell having at least three p-n junctions is proposed, which comprises a rear-side subcell comprising GaSb, which has at least one p-n junction, and a front-side subcell which has at least two p-n junctions and which is characterised in that the rear-side subcell has a ≧2%, in particular >4%, larger lattice constant than the front-side subcell and the two subcells are connected to each other via an optically transparent and electrically conductive wafer-bond connection. The multi-junction solar cell achieves a high absorption up to the band gap energy of the lowermost GaSb-comprising subcell and a photoelectric voltage which is increased relative to multi-junction solar cells from the state of the art. Furthermore, methods for the production of the multi-junction solar cell according to the invention are presented and uses of the multi-junction solar cell according to the invention are indicated. | 2015-12-24 |
20150372180 | OXYGEN DOPED CADMIUM MAGNESIUM TELLURIDE ALLOY - A band gap material includes an alloy of cadmium, tellurium and magnesium. The alloy is doped with oxygen wherein the alloy includes an intermediate band positioned between conduction and valance bands of the alloy. The alloy has the formula: Cd | 2015-12-24 |
20150372181 | ACTIVE PHOTONIC DEVICE HAVING A DARLINGTON CONFIGURATION - An active photonic device having a Darlington configuration is disclosed. The active photonic device includes a substrate with a collector layer over the substrate. The collector layer includes an inner collector region and an outer collector region that substantially surrounds the inner collector region. A base layer resides over the collector layer. The base layer includes an inner base region and an outer base region that substantially surrounds and is spaced apart from the inner base region. An emitter layer resides over the base layer. The emitter layer includes an inner emitter region that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region. The emitter layer further includes an outer emitter region that is ring-shaped and resides over and extends substantially around the outer base region. A connector structure electrically couples the inner emitter region with the outer base region. | 2015-12-24 |
20150372182 | RADIATION MICRODOSIMETERS CORRELATED WITH BIOLOGICAL CELLS AND CELL COMPONENTS - One feature pertains to a radiation dosimeter comprising a microdosimeter cell array that includes a first microdosimeter cell having a first semiconductor volume configured to generate a first current in response to incident radiation. The first semiconductor volume may have at least one of a first size, a first shape, a first semiconductor type, and/or a first semiconductor doping type and concentration that is associated with a first biological cell type or a first biological cell component type. The dosimeter may further comprise a processing circuit communicatively coupled to the microdosimeter cell array and configured to generate a signal based on the first current. The signal generated may be indicative of an amount of radiation absorbed by the microdosimeter cell array. A display may be utilized by the dosimeter to show a radiation level reading based on the signal generated. | 2015-12-24 |
20150372183 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell is formed to have a silicon semiconductor substrate of a first conductive type; an emitter layer having a second conductive type opposite the first conductive type and formed on a first surface of the silicon semiconductor substrate; a back surface field layer having the first conductive type and formed on a second surface of the silicon semiconductor substrate opposite to the first surface; and wherein the emitter layer includes at least a first shallow doping area and the back surface field layer includes at least a second shallow doping area, and wherein a thickness of the first shallow doping area of the emitter layer is different from a thickness of the second shallow doping area of the back surface field layer. | 2015-12-24 |
20150372184 | METHOD OF MANUFACTURING SOLAR BATTERY CELL - The present invention provides a boron diffusion layer forming method capable of sufficiently oxidizing a boron silicide layer formed on a silicon substrate to remove it and obtaining a high-quality boron silicate glass layer. The present invention is a boron diffusion layer forming method of forming a boron diffusion layer on a silicon substrate by a boron diffusion process, the process including a first step of thermally diffusing boron on the silicon substrate and a second step of oxidizing a boron silicide layer formed on the silicon substrate at the first step, wherein the second step has a state at a temperature of 900° C. or higher and a treatment temperature at the first step or lower, for 15 minutes or more. | 2015-12-24 |
20150372185 | COMPACT LIGHT SENSING MODULES INCLUDING REFLECTIVE SURFACES TO ENHANCE LIGHT COLLECTION AND/OR EMISSION, AND METHODS OF FABRICATING SUCH MODULES - The disclosure describes light sensing optoelectronic modules that include reflective surfaces to enhance light collection and/or light emission. For example, an optoelectronic module can include a light sensing element mounted on a substrate. A spacer over the substrate has a through-hole over the light sensing element. The through-hole is defined by a surface that is at least partially sloped or curved with respect to a plane of the substrate. The surface is highly reflective for light detectable by the light sensing element. Various methods for fabricating the modules are described as well. | 2015-12-24 |
20150372186 | METHOD FOR MANUFACTURING NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a method of manufacturing a nanostructure semiconductor light emitting device including providing a base layer formed of a first conductivity-type semiconductor, forming a mask including an etch stop layer on the base layer, forming a plurality of openings with regions of the base layer exposed therethrough, in the mask; forming a plurality of nanocores by growth of the first conductivity-type semiconductor on the exposed regions of the base layer to fill the plurality of openings, partially removing the mask using the etch stop layer to expose side portions of the plurality of nanocores, and sequentially growth of an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores. | 2015-12-24 |
20150372187 | SYSTEMS AND METHODS FOR PREPARING GAN AND RELATED MATERIALS FOR MICRO ASSEMBLY - The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly. | 2015-12-24 |
20150372188 | METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A method for producing a semiconductor light emitting element includes a wafer preparation step, a first irradiation step, a second irradiation step, and a wafer division step. The wafer includes a semiconductor structure on a first main surface of a substrate. In the first irradiation step, a first light-condensing position in the thickness direction of the substrate is irradiated with a first laser beam from a second main surface of the substrate to form an altered area. The second main surface is opposite to the first main surface. In the second irradiation step, a second light-condensing position is irradiated with a second laser beam. The second light-condensing position is located at a position in the altered area different from the first light-condensing position. In the wafer division step, the wafer is divided into individual light emitting elements. | 2015-12-24 |
20150372189 | III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - To provide a III nitride semiconductor light emitting device in which the formation of cracks in an active layer is suppressed and the light output power is improved, a III nitride semiconductor light emitting device has an n-type cladding layer, an active layer, and a p-type cladding layer in order. The active layer has a multiple quantum-well structure in which barrier layers made of Al | 2015-12-24 |
20150372190 | ULTRAVIOLET LIGHT EMITTING DIODE AND METHOD FOR PRODUCING SAME - An ultraviolet LED having increased light extraction efficiency includes: a single crystal sapphire substrate on which an array of protruding portions are formed; an AlN crystal buffer layer formed on the sapphire substrate; and an ultraviolet light emitting layer, in contact with the buffer layer, formed into a layered stack including an n-type conductive layer, a recombination layer, and a p-type conductive layer, in order from the buffer layer. The buffer layer includes a pillar array section and an integration section wherein pillars in the array are connected with one another. Each pillar extends from a protruding portion of the sapphire substrate, in a direction normal to one surface thereof. The pillars are separated from one another in the plane of the surface by a gap G. Light emitted from the ultraviolet light emitting layer is extracted to the outside through the pillar array section and the sapphire substrate. | 2015-12-24 |
20150372191 | SURFACE LIGHT-EMISSION ELEMENT USING ZINC OXIDE SUBSTRATE - Provided is a surface light-emitting device comprising a substrate composed of an oriented polycrystalline zinc oxide sintered body in a plate shape, a light emitting functional layer provided on the substrate, and an electrode provided on the light emitting functional layer. According to the present invention, a surface light-emitting device having high luminous efficiency can be inexpensively provided. | 2015-12-24 |
20150372192 | METHOD AND APPARATUS FOR CREATING A PORUS REFLECTIVE CONTACT - A light emitting device includes a semiconductor structure having a light emitting region ( | 2015-12-24 |
20150372193 | Patterned Layer Design for Group III Nitride Layer Growth - A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. | 2015-12-24 |
20150372194 | NANO-STRUCTURED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer. | 2015-12-24 |
20150372195 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor light emitting device includes a substrate; a base layer made of a first conductivity-type semiconductor and disposed on the substrate; a plurality of nanoscale light emitting units disposed in a region of an upper surface of the base layer and including a first conductivity-type nano-semiconductor layer protruding from the upper surface of the base layer, a nano-active layer disposed on the first conductivity-type nano-semiconductor layer, and a second conductivity-type nano-semiconductor layer disposed on the nano-active layer; and a light emitting laminate disposed in a different region of the upper surface of the base layer and having a laminated active layer. | 2015-12-24 |
20150372196 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - The light emitting element including: a semiconductor laminate including a first layer, an active layer and a second layer; a first electrode including protrusions that penetrate the second layer and the active layer, the first electrode connected to the first layer via the protrusions; a second electrode connected to the second layer on an lower face of the second layer; and an insulation film between the protrusions and the semiconductor laminate, wherein the protrusions each include a protrusion body covered with the insulation film and a protrusion tip, an upper face and a side face of the protrusion tip being exposed from the insulation film, the first layer includes recesses arranged on an upper face of the first layer so as to sandwich first areas located above the respective the protrusions, and a distance between the recesses sandwiching the first area is larger than a width of the protrusion tip. | 2015-12-24 |
20150372197 | LIGHT-EMITTING DIODE ILLUMINATION APPARATUS - An Light-Emitting Diode illumination apparatus includes a light source unit which has a first housing storing a Light-Emitting Diode and in which a pair of contact point portions connected to the Light-Emitting Diode are exposed from the first housing; and a function unit which has a second housing storing the first housing and has a pair of contacted point portions provided in the second housing for supplying power to the Light-Emitting Diode connected to the pair of contact point portions, wherein the pair of contact point portions are provided with engagement protruding portions having different outline shapes, respectively, and the pair of contacted point portions are provided with engagement recessed portions into which the engagement protruding portions of the pair of contact point portions are insertable, respectively. | 2015-12-24 |
20150372198 | LIGHT EMITTING MODULE - A light emitting module includes a semiconductor light emitting element, an optical wavelength conversion member configured to convert the wavelength of element light emitted from the semiconductor light emitting element and to emit converted light, having a color different from the element light, a transmitting member disposed between the semiconductor light emitting element and the optical wavelength conversion member and configured to allow the element light to be transmitted therethrough, the transmitting member being made of a thermal conductive material that transfers the heat generated from the optical wavelength conversion member to the outside, and a transparent adhesive bonding the optical wavelength conversion member and the transmitting member to each other, the adhesive having a thickness of 2.0 μm or less. | 2015-12-24 |
20150372199 | LIGHT EMITTING DIODE DEVICE WITH LUMINESCENT MATERIAL - The invention provides a light emitting diode device comprising a light emitting diode ( | 2015-12-24 |
20150372200 | SEMICONDUCTOR LIGHT-EMITTING APPARATUS AND VEHICLE HEADLIGHT - A reliable semiconductor light-emitting apparatus and a headlight using the light-emitting apparatus provided with a light source module including a semiconductor light-emitting device and a wavelength converting module including a wavelength converting layer. The wavelength converting module can include a base having a mounting board, which mounts the wavelength converting layer via metallic bumps, and the base can be configured to attach the light source module directly or via a connecting guide including an optical fiber, and therefore can transmit light emitted from the light-emitting device towards the wavelength converting layer while efficiently radiating heat generated from the wavelength converting layer. Thus, the disclosed subject matter can provide reliable semiconductor light-emitting apparatuses having a high thermal resistance that can emit various color lights having favorable optical characteristics, which can also include the optical fiber, and which can be used for the headlight that can provide a favorable light distribution pattern. | 2015-12-24 |
20150372201 | ARRAY PANEL AND MANUFACTURING METHOD FOR THE SAME - An array panel including a substrate, a scanning line, a data line, and a pixel array is disclosed. A pixel unit in the pixel array includes a thin film transistor, a pixel electrode, and a color filter layer disposed between a first plane and a second plane. The first plane is a plane in which a gate electrode of the thin film transistor is located. The second plane is a plane in which the pixel electrode is located. The scanning line, the data line, and the pixel array are disposed on the substrate. The present invention is advantageous since it reduces power consumption. | 2015-12-24 |
20150372202 | REUSABLE ENCAPSULATION LAYER SUPPORT PLATE AND METHOD OF ENCAPSULATING OLED SUBSTRATE - The embodiments of the present invention disclose a reusable encapsulation layer support plate comprising: a support plate body, the top of the support plate body being arranged with at least one first opening for accommodating an encapsulation layer; a cavity arranged within the support plate body, the cavity being filled with a porous material, and the top of the cavity having at least one second opening; wherein the first opening is connected with and arranged opposite to the second opening, and the top surface of the porous material is parallel and level with the bottom surface of the first opening. The encapsulation layer support plate can avoid crash of OLED substrate, realize effective OLED encapsulation, and can be reused as far as possible. The embodiments of the present invention further disclose a method of encapsulating an OLED substrate using the encapsulation layer support plate. | 2015-12-24 |
20150372203 | Optoelectronic Semiconductor Chip Encapsulated with an ALD Layer and Corresponding Method for Production - An optoelectronic semiconductor chip includes a semiconductor body with an active region provided for generating electromagnetic radiation, a first mirror layer provided for reflecting the electromagnetic radiation, a first encapsulation layer formed with an electrically insulating material, and a carrier provided for mechanically supporting the first encapsulation layer, the first mirror layer and the semiconductor body. The first mirror layer is arranged between the carrier and the semiconductor body. The first encapsulation layer is arranged between the carrier and the first mirror layer. The first encapsulation layer is an ALD layer. | 2015-12-24 |
20150372204 | ULTRAVIOLET LIGHT EMITTING DEVICE - An ultraviolet light emitting device of the present invention includes a light emitting element provided on a substrate, an optical system provided at a position facing the light emitting element, a metal cylinder holding the optical system, and a holding component holding the metal cylinder on a substrate. Light the emitting element is disposed in an area of the substrate, the area surrounded by one end of the metal cylinder closer to the substrate. This provides the ultraviolet light emitting device that prevents the distortion of the optical system as well as the influence of ultraviolet light on the holding component. | 2015-12-24 |
20150372205 | ELECTRON BEAM CURABLE RESIN COMPOSITION, REFLECTOR RESIN FRAME, REFLECTOR, SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND MOLDED ARTICLE PRODUCTION METHOD - Provided are an electron beam curable resin composition including an olefin resin, and a crosslinking agent, in which the crosslinking agent has a saturated or unsaturated ring structure, at least one atom among atoms forming at least one ring is bonded to any allylic substituent of an allyl group, a methallyl group, an allyl group through a linking group, and a methallyl group through a linking group, and the crosslinking agent is blended in an amount of more than 15 parts by mass and 40 parts by mass or less with respect to 100 parts by mass of olefin resin, a reflector resin frame using the resin composition, a reflector, a semiconductor light-emitting device, and a molding method using the resin composition. | 2015-12-24 |
20150372206 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device package and a lighting system including the light emitting device package. The light emitting device package includes a package body, at least one electrode on the package body, a light emitting device on the package body, a reflective structure around the light emitting device on the package body and a lens on the light emitting device and the electrode. | 2015-12-24 |
20150372207 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A semiconductor light emitting device package includes a semiconductor laminate having first and second surfaces and side surfaces, and including first and second conductivity-type semiconductor layers, and an active layer, a support body disposed on the second surface and including first and second package electrodes, a first electrode layer disposed on the first surface and connected to the first conductivity-type semiconductor layer and extended along a side of the semiconductor laminate to be connected to the first package electrode, a side insulating layer disposed on a side of the semiconductor laminate and electrically insulating the first electrode layer from the side of the semiconductor laminate, and a second electrode layer disposed on the second surface and electrically connecting the first conductivity-type semiconductor layer to the second package electrode. | 2015-12-24 |
20150372208 | LIGHT EMITTING DEVICE - Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction. | 2015-12-24 |
20150372209 | OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME - An optical device includes a metal substrate wherein at least one vertical insulation layer is formed from the upper to the lower surface; a metal plated layer formed on the upper surface of the metal substrate except for the vertical insulation layer; and an optical device chip bonded to one portion of the metal plated layer. One electrode of the optical device chip is electrically connected to a bonded surface of the metal plated layer, and the other electrode of the optical device chip is wire bonded to the other portion of metal plated layer. The optical device chip and a peripheral region thereof is shielded with a sealant, and at least one groove is formed on a partial surface of the metal plated layer so that a portion of the sealant is directly bonded to the metal substrate. | 2015-12-24 |
20150372210 | LEAD FRAME FOR MOUNTING LED ELEMENTS, LEAD FRAME WITH RESIN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND LEAD FRAME FOR MOUNTING SEMICONDUCTOR ELEMENTS - A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region. | 2015-12-24 |
20150372211 | LIGHT EMITTING DIODE PACKAGE - This application relates to a packaging structure, particularly to a light emitting diode package structure. | 2015-12-24 |
20150372212 | TE-BASED THERMOELECTRIC MATERIAL HAVING COMPLEX CRYSTAL STRUCTURE BY ADDITION OF INTERSTITIAL DOPANT - This invention relates to a Te-based thermoelectric material having stacking faults by addition of an interstitial dopant, including unit cells configured such that A-B-A-C-A elements are stacked to five layers, in which A element of a terminal of a unit cell and A element of a terminal of another unit cell are repeatedly stacked by a van der Waals interaction, wherein an interstitial element as the dopant is located at an interstitial position between the repeatedly stacked A elements adjacent to each other, thus generating stacking faults of the repeatedly stacked unit cells to thereby form a twin as well as a complex crystal structure different from the unit cells (where A is Te or Se, B is Bi or Sb, and C is Bi or Sb). | 2015-12-24 |
20150372213 | Thermoelectric Conversion Element and Method for Making the Same - In order to further improve the spin-current/electric-current conversion efficiency in a spin-current thermoelectric conversion element, a thermoelectric conversion element includes a magnetic material layer having in-plane magnetization; and an electromotive material layer magnetically coupled with the magnetic material layer. The electromotive material layer includes a first conductor with a spin orbit coupling arising, and a second conductor having lower electric conductivity than electric conductivity of the first conductor. | 2015-12-24 |
20150372214 | COOLED COOLING AIR SYSTEM HAVING THERMOELECTRIC GENERATOR - Various embodiments include a cooled cooling-air system including: an inlet hot fluid conduit fluidly connected with a hot air source from a turbomachine; an inlet cold fluid conduit fluidly connected with a cold fluid source, the cold fluid source having a lower temperature than the hot air source; and a first thermoelectric generator fluidly connected with the inlet hot fluid conduit and the inlet cold fluid conduit, the first thermoelectric generator for cooling the inlet hot fluid conduit and simultaneously generating an electrical output. | 2015-12-24 |
20150372215 | MANUFACTURING METHOD FOR THERMOELECTRIC CONVERSION DEVICE - An insulating substrate is prepared. In this substrate, plural via holes penetrating in a thickness direction are filled with a conductive paste. This paste is produced by adding an organic solvent to a powder of an, and by processing the power of the alloy to a paste. The substrate is then pressed from a front surface and a back surface of the substrate, while being heated. The conductive paste is solid-phase sintered and interlayer connecting members are formed. A front surface protective member is disposed on a front surface of the substrate and a back surface protective member is disposed on a back surface of the substrate, and a laminate is formed. The laminate is integrated by a lower pressure being applied while heating at a lower temperature, compared to the temperature and pressure in the process of forming the interlayer connecting members. | 2015-12-24 |
20150372216 | Thermodiode Element for a Photosensor for Infrared Radiation Measurement, Photosensor and Method for producing a Thermodiode Element - A thermodiode element for a photosensor of a thermocamera usable for infrared radiation measurement includes a semiconductor substrate that has a first layer, and a second layer adjoining the first layer. The first layer has a base doping zone, and the second layer has a side doping zone that is the same doping type as the base doping zone. The second layer also has a further doping zone that is arranged as an island in the side doping zone and that has a doping type that is opposite to the doping type of the base doping zone. The base doping zone is further arranged in the first layer so as to adjoin the further doping zone. | 2015-12-24 |
20150372217 | METHODS FOR MAKING A SUPERCONDUCTING DEVICE WITH AT LEAST ONE ENCLOSURE - Some embodiments are directed to a device including multiple substrates comprising one or more troughs. The substrates are disposed such that the one or more troughs form at least one enclosure. At least one superconducting layer covers at least portion of the at least one enclosure. Other embodiments are directed to a method for manufacturing a superconducting device. The method includes acts of forming at least one trough in at least a first substrate; covering at least a portion of the first substrate with a superconducting material; covering at least a portion of a second substrate with the superconducting material; and bonding the first substrate and the second substrate to form at least one enclosure comprising the at least one trough and the superconducting material. | 2015-12-24 |
20150372218 | PIEZO HAPTIC DRIVER AND METHOD FOR DRIVING THE SAME - Disclosed herein is a piezo haptic driver capable of preventing a malfunction and being more effectively operated and a method for driving the same. According to an exemplary embodiment of the present disclosure, a piezo haptic driver includes: an analog signal processor driving a piezo element; a controller transferring a control signal controlling the piezo element to the analog signal processor; an interface controller determining a driving of the analog signal processor in response to at least one of an under voltage lock out (UVLO) signal and a thermal shutdown (TSD) signal. | 2015-12-24 |
20150372219 | PIEZOELECTRIC TRANSDUCER, ULTRASONIC PROBE, AND PIEZOELECTRIC TRANSDUCER MANUFACTURING METHOD - According to embodiment, a piezoelectric transducer includes a polarized single crystal piezoelectric body comprising a lead complex perovskite compound containing niobium oxide and at least one of magnesium oxide and indium oxide and including a first plane whose crystal orientation is [100] and a second plane which faces the first plane and whose crystal orientation is [100], and first electrode provided on the first plane side of the body and a second electrode provided on the second plane side of the body. A ratio of a second FWHM of diffracted X-rays at the Miller index (400) of the body to a first FWHM of diffracted X-rays at the miller index (400) of the body which is unpolarized or has undergone depolarization processing is not less than 0.22 and not more than 0.4. | 2015-12-24 |
20150372220 | ALL COMPLIANT ELECTRODE - The invention relates to a dielectric transducer structure comprising a body of elastomeric material that is provided with an electrode arrangement on each of two boundary surfaces lying oppositely to one another. At least one boundary surface comprises a corrugated area that comprises heights and depths. The aim of the invention is to improve the compliance to elastic deformations of the dielectric transducer structure. To this end, the heights and depths are arranged in both perpendicular directions of the boundary surface. | 2015-12-24 |
20150372221 | LEAD-FREE PIEZOELECTRIC MATERIAL - A lead-free piezoelectric ceramic material has the general chemical formula xBiCoO3-y(Bi0.5Na0.5)TiO3-z(Bi0.5K0.5)TiO3, xBiCoO3-y(Bi0.5Na0.5)TiO3-zNaN-bO3, xBiCoO3-y(Bi0.5Na0.5)TiO3-zKNbO3, xBiCoO3-yBi(Mg0.5Ti0.5)O3-z(Bi0.5Na0.5)TiO3, xBiCoO3-yBa-TiO3-z(Bi0.5Na0.5)TiO3, or xBiCoO3-yNaNbO3-zKNbO3; wherein x+y+z=1, and x, y, z≠0. | 2015-12-24 |
20150372222 | ELECTROSTATICALLY CONTROLLED MAGNETIC LOGIC DEVICE - A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion. | 2015-12-24 |
20150372223 | Strap Configuration to Reduce Mechanical Stress Applied to Stress Sensitive Devices - An apparatus includes an elongated strap with a first platform and a second platform linked by a connector that is substantially narrower than the first platform and the second platform, where the first platform and the second platform are each configured to receive a stress sensitive device. | 2015-12-24 |
20150372224 | HYBRIDIZED OXIDE CAPPING LAYER FOR PERPENDICULAR MAGNETIC ANISOTROPY - A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining reference layer. The HOCL has an interface oxide layer adjoining the reference layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the reference layer. | 2015-12-24 |
20150372225 | METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING - A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask. | 2015-12-24 |
20150372226 | VARIABLE SELECTIVITY SILICON GROWTH PROCESS - The present invention is a means and a method for speeding up the fabrication process, lowering the cost and improving yields. The present invention is a method for manufacturing memory cells in a diode memory array by utilizing selective epitaxial growth techniques to form high quality silicon for diodes and then lesser quality silicon to fill recesses and prepare the surface for subsequent planarization or etching steps. | 2015-12-24 |
20150372227 | MEMORY CELLS - Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the second electrode. The second electrode comprises a plurality of portions of material, each portion having a respective distance from the surface of the phase change material and each portion having a respective resistivity. A portion of the plurality of portions of material farthest from the surface of the phase change material has a lowest resistivity and a portion of the plurality of portions of material closest to the surface of the phase change material has a highest resistivity. The resistivity of each individual portion is lower than the resistivity of each portion located closer to the surface of the phase change material, and higher than the resistivity of each portion located farther from the surface of the phase change material. | 2015-12-24 |
20150372228 | Memory Device Having Oxygen Control Layers And Manufacturing Method Of Same - A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content. | 2015-12-24 |
20150372229 | RESISTIVE MEMORY DEVICE HAVING ASYMMETRIC DIODE STRUCTURE - A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode. | 2015-12-24 |
20150372230 | METHOD OF FORMING A MEMORY AND METHOD OF FORMING A MEMORY ARRAY - A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is electrically contacting the antifuse element. | 2015-12-24 |
20150372231 | METHODS TO FABRICATE NON-METAL FILMS ON SEMICONDUCTOR SUBSTRATES USING PHYSICAL VAPOR DEPOSITION - Embodiments of the invention relate generally to semiconductor device fabrication and processes, and more particularly, to methods for implementing arrangements of magnetic field generators configured to facilitate physical vapor deposition (“PVD”) and/or for controlling impedance matching associated with a non-metal-based plasma used to modify a non-metal film, such as a chalcogenide-based film. | 2015-12-24 |
20150372232 | Method for Producing a Semiconducting Organic Film - A method for producing a semiconducting organic film comprising the steps:
| 2015-12-24 |
20150372233 | PROCESS FOR FORMING ORGANIC SEMICONDUCTOR FILM - In the present invention, an organic semiconductor film is formed by using a cover member which is disposed on a substrate for forming the organic semiconductor film and forms a space relative to the substrate, filling the space between the cover member and the substrate with a solution, and drying the filled solution, wherein the cover member has a control surface on which an uppermost part most separated from the substrate and a descending part provided on both sides in the y-direction of the uppermost part so as to descend from the uppermost part toward the substrate are formed. | 2015-12-24 |
20150372234 | METHOD FOR PRODUCING ORGANIC SEMICONDUCTOR ELEMENT - In the method for producing an organic semiconductor element having a semiconductor layer according to the present invention, an optical system for irradiating a laser beam with a wavelength of at least 4 μm and a donor substrate prepared by forming an organic semiconductor film on a surface of a supporting member having a laser beam transmittance of at least 50% are used; and the donor substrate and a substrate to be treated serving as a semiconductor element are opposite one another; the laser beam is irradiated from the supporting member side; the laser beam is scanned while modulating in accordance with the semiconductor layer to be formed; and the organic semiconductor film is transferred to the substrate to be treated so as to form the semiconductor layer. | 2015-12-24 |