52nd week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150372636 | Tracking Photovoltaic Solar System, and Methods for Installing or for Using Such Tracking Photovoltaic Solar System - A tracking photovoltaic solar system, and methods for installing or for using such tracking comprising at least a dual axis tracker unit maintaining an array of photovoltaic modules aligned to the sun. Said tracker unit includes: a pair of sub-frames supporting photovoltaic modules, a torque tube supporting said subframes rotating around a primary rotation axis, a pole structure fixed and extending vertically above an anchoring basis and being rotatively connected to said longitudinal support, secondary rotating means controlling the orientation of said sub-frames around corresponding secondary rotation axis of said sub-frames, said secondary rotation axis being orthogonal to said primary rotation axis and actuators means for controlling said primary and secondary rotating means. The secondary rotation axis are located at each end of said torque tube, said pole structure being central with regard to said sub-frames and said actuators means of both primary and secondary rotating means are linear. | 2015-12-24 |
20150372637 | SOLAR MODULE FRAME - A solar module frame includes two first borders and two second borders. At least one first border includes a first segment and a second segment, where one end of the first segment is connected to one end of the second border, and one end of the second segment is connected to one end of the other second border. The solar module frame includes at least one connection component. One end of the connection component is connected to the other end of the first segment, and the other end of the connection component is connected to the other end of the second segment. Each of the first segment, the second segment, and the connection component includes an external wall, a support wall, a first clamping wall, and a second clamping wall. Each of the first segment and the second segment includes an internal wall. | 2015-12-24 |
20150372638 | DIODE-INCLUDED CONNECTOR, PHOTOVOLTAIC LAMINATE AND PHOTOVOLTAIC ASSEMBLY USING SAME - One embodiment relates to a connector that includes a diode. The diode has an anode and a cathode. The connector further includes a first electrical connection which connects to the anode, a second electrical connection which also connects to the anode, and a third electrical connection which connects to the cathode. Another embodiment relates to a photovoltaic laminate which includes a string of photovoltaic cells and three electrical conductors extending out of two discrete penetrations of the laminate. A first electrical conductor is connected to a first end of the string, a second electrical conductor is connected to a second end of the string, and a third electrical conductor is also connected to the second end of the string. The first and third electrical conductors extend out of the first discrete penetration, while the second electrical conductor extends out of the second discrete penetration. Other features and embodiments are also disclosed. | 2015-12-24 |
20150372639 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present invention provides a display substrate and a display device, belonging to the field of display technology. In view of the problem that the energy-saving techniques of an existing liquid crystal display have yet to be further developed and improved, the present invention provides the display substrate comprising photoelectric conversion element for converting light energy into electric energy and the display device including the above display substrate. According to the display substrate and the display device of the present invention, renewable light energy is converted into electric energy by using the photoelectric conversion elements to supply power to the display device, so that the energy consumption of an external power supply by the display device may be reduced, and further, non-renewable resources may be favorably saved. | 2015-12-24 |
20150372640 | Utility-friendly Hybrid Energy Conversion System for Apportioning Concentrated Solar Radiation in Real Time Upon Selective Demand Between a Plurality of Solar Energy Conversion Devices, Including a Photovoltaic Receiver - Extremely fast dynamic control is allowed for hybrid PV/T (photovoltaic/thermal) distributed power production using concentrated solar power by manipulating the transmissive or reflective state of a capture element or mirror or lens that can pass highly concentrated solar light from one energy conversion device to another, such as a thermal collector and a photovoltaic receiver, such as a vertical multijunction cell array. This allows superior quality electrical backfeed into an electric utility, enhanced plant electrical production revenue, and responsiveness to a multitude of conditions to meet new stringent engineering requirements for distributed power plants. The mirror or lens can be physically articulated using fast changing of a spatial variable, or can be a fixed smart material that changes state. A mechanical jitter or variable state jitter can be applied to the capture element, including at utility electric grid line frequency. | 2015-12-24 |
20150372641 | OPTIMALLY PLACING PHOTOVOLTAIC ARRAYS TO MAXIMIZE VALUE OF ENERGY PRODUCTION BASED ON PEAK POWER PRODUCTION, LOCAL SOLAR RADIATION, WEATHER, ELECTRICITY MARKET PRICES AND RATE STRUCTURES - A method, system and computer program product for optimally placing photovoltaic arrays to maximize a value of energy production. Incident solar radiation for various placements of the photovoltaic arrays accommodating different azimuths and tilts is calculated. Alternating current solar photovoltaic electricity energy and power production is then estimated from the calculated solar radiation on a plane and weather data. Furthermore, a value of solar photovoltaic electricity energy and power produced by the photovoltaic arrays for the various placements is calculating using the estimated alternating current solar photovoltaic electricity production. A placement out of the various placements for the photovoltaic arrays is then selected corresponding to a highest value of the solar photovoltaic electricity produced by the photovoltaic arrays. In this manner, the appropriate placement for the photovoltaic arrays is determined that maximizes the value of energy production (where “value” may correspond to an economic value or a non-economic value). | 2015-12-24 |
20150372642 | COMPACT APPARATUS FOR THE SEMI-AUTOMATIC HORIZONTAL ASSEMBLY OF PHOTOVOLTAIC PANELS - Compact apparatus for the semi-automatic horizontal assembly of photovoltaic panels with solar cells, made up of a multi-function workstation in the form of a pilot system integrating multiple working and conveying means which carry out the various operations concomitantly and in a coordinated way. On the sides of the working surface there is the loading zone of the cells, the loading zone of the conductive ribbons and a pair of longitudinal rails which are intended to guide two mobile gantries, which roto-translate above the working surface, from one loading zone to the other, being equipped for the purpose of assembly. In particular, the compact apparatus is versatile in use and allows to obtain already in the experimental laboratory phases the levels of accuracy and control of an industrial system, for the purpose of optimizing the product and the assembly technologies reducing wastes and faults. | 2015-12-24 |
20150372643 | VOLTAGE-CONTROLLED OSCILLATOR WITH REDUCED SINGLE-ENDED CAPACITANCE - Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO. | 2015-12-24 |
20150372644 | Apparatus and Method for Generating an Oscillator Signal - An apparatus comprises a mechanical resonator-based oscillator module generating a local oscillator signal with a frequency of more than 700 MHz. Further, the apparatus comprises a digital-to-time converter module generating a frequency adapted signal based on the local oscillator signal. | 2015-12-24 |
20150372645 | CLASS-E OUTPHASING POWER AMPLIFIER WITH EFFICIENCY AND OUTPUT POWER ENHANCEMENT CIRCUITS AND METHOD - An outphasing amplifier includes a first class-E power amplifier ( | 2015-12-24 |
20150372646 | Linearization Circuits And Methods For Multilevel Power Amplifier Systems - Circuits and methods for achieving high linearity, high efficiency power amplifiers, including digital predistortion (DPD) and pulse cancellation in switched-state RF power amplifier systems are described. | 2015-12-24 |
20150372647 | SYSTEMS AND METHODS UTILIZING ADAPTIVE ENVELOPE TRACKING - A communication system utilizing adaptive envelope tracking includes a transmit path, a feedback receiver, a parameter component and an envelope tracking component. The transmit path is configured to generate a transmit signal. The feedback receiver is configured to generate a feedback signal from the transmit signal. The parameter component is configured to generate linearity parameters from the feedback signal and the baseband signal. The envelope tracking component is configured to generate a supply control signal having time delay adjustments. | 2015-12-24 |
20150372648 | TRANSIMPEDANCE AMPLIFIER - A TIA comprises a TIA core that converts a current signal to a voltage signal, a single-to-differential converter that generates a differential voltage signal from the voltage signal, a feedback circuit that generates a control signal from the differential voltage signal, a bypass circuit that generates the current signal by subtracting the bypass current from the input current so that an average value of the current signal is maintained at a predetermined value, and a monitor circuit that generates a monitor current proportional to the bypass current from the control signal | 2015-12-24 |
20150372649 | SIGNAL AMPLIFICATION SYSTEM - An input signal amplification system comprises at least two different means of amplifying input signals in order to obtain amplified signals. It also comprises at least one means of summing amplified signals, and dynamic means of activating or deactivating one or more of the amplifying means based on input signals. | 2015-12-24 |
20150372650 | AUDIO DRIVER SYSTEM AND METHOD - An audio driver equipped with a distortion compensation unit corrects for detected distortion and includes a digital to analog converter (DAC), an amplifier, and an output driver that drives a loudspeaker. Between the output driver and the loudspeaker, the audio driver can include a series resistor and a differential amplifier to measure the voltage across the resistor. A distortion detection unit can use the detected voltage to determine whether distortion, such as rub and buzz distortion is present. The distortion detection unit can comprise an analog to digital converter (ADC) to digitize the voltage data, an FFT to transform the voltage data into frequency information, a root-mean-square (RMS) module that measures the energy at each frequency, and an analysis module which looks for the distortion signature in the energy spectrum. | 2015-12-24 |
20150372651 | COMPLEMENTARY CURRENT REUSING PREAMP FOR OPERATIONAL AMPLIFIER - An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level. | 2015-12-24 |
20150372652 | MULTISTAGE AMPLIFIER - Provided is a multistage amplifier that can achieve both utilizing in a broad bandwidth and suppressing gain reduction. The multistage amplifier includes a plurality of differential amplifiers which are connected in series; and a direct-current component limiter that cuts off a direct-current component of input signals, in which the direct-current component limiter is disposed between the plurality of differential amplifiers, and in which a transistor size of a first differential amplifier which is disposed immediately after the direct-current component limiter is equal to or greater than a transistor size of a second differential amplifier which is disposed two stages before the direct-current component limiter. | 2015-12-24 |
20150372653 | LEVEL ADJUSTING CIRCUIT, DIGITAL SOUND PROCESSOR, AUDIO AMP INTEGRATED CIRCUIT, ELECTRONIC APPARATUS AND METHOD OF AUTOMATICALLY ADJUSTING LEVEL OF AUDIO SIGNAL - Level adjusting circuit for adjusting level of input audio signal, includes: N filters, N being integer of two or more; N dynamic range compression (DRC) circuits corresponding to N filters; adder; (N−1) band pass filters corresponding to crossover frequencies of N filters; and (N−1) gain correcting units corresponding to (N−1) band pass filters. Each filter receives and passes input audio signal through its respective set band. i | 2015-12-24 |
20150372654 | SYSTEM AND METHOD FOR DYNAMICALLY MIXING AUDIO SIGNALS - A system and method for dynamically mixing audio signals may calculate a signal amplitude for each of two or more audio signals. The signal amplitude may be the absolute value of the audio signal. A signal sum may be calculated using each of the two or more signal amplitudes. Each of the two or more signal amplitudes may be smoothed. The signal sum may be smoothed. The smoothing may be a filter or a leaky integrator. A respective mixing gain may be calculated for each of the two or more audio signals using a respective ratio of each of the two or more smoothed signal amplitudes and the smoothed signal sum. Each of the two or more audio signals may be gain adjusted responsive to the respective mixing gain. Each of the two or more gain adjusted audio signals may be mixed to create an output signal. | 2015-12-24 |
20150372655 | Filter Component - A filter component includes a housing body. A first and at least one second busbar each have a first end section, and a second end section, between which in each case a center section is arranged. The end sections of the busbars each have connections for connecting electrical conductors to the filter component. The first and second end section and the center section of the first busbar are arranged in a first plane and the first and second end section and the center section of the at least one second busbar are arranged in a second plane, which is different from the first plane. | 2015-12-24 |
20150372656 | Electronic Device With Adjustable Wireless Circuitry - An electronic device may be provided with wireless circuitry. Control circuitry may be used to adjust the wireless circuitry. The wireless circuitry may include antennas that are tuned, adjustable impedance matching circuitry, antenna port selection circuitry, and adjustable transceiver circuitry. Wireless circuit adjustments may be made by ascertaining a current usage scenario for the electronic device based on sensor data, information from cellular base station equipment or other external equipment, signal-to-noise ratio information or other signal information, antenna impedance measurements, and other information about the operation of the electronic device. | 2015-12-24 |
20150372657 | Switchable Signal Routing Circuit - A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports. | 2015-12-24 |
20150372658 | LOW-INSERTION-LOSS PIEZOELECTRIC ACOUSTIC WAVE BAND-PASS FILTER AND REALIZATION METHOD THEREOF - A low-insertion-loss piezoelectric acoustic wave band-pass filter and a realization method thereof are disclosed. The realization method includes: using one first kind of piezoelectric acoustic wave resonator to constitute a series branch; using one second kind of piezoelectric acoustic wave resonator to constitute a parallel branch with a ground terminal; connecting any end of the series branch with a non-ground terminal of the parallel branch to form an acoustic wave band-pass filter unit; and cascading a plurality of acoustic wave band-pass filter units; wherein an impedance value at a series resonant frequency of the first kind of piezoelectric acoustic wave resonator is less than that of the second kind of piezoelectric acoustic wave resonator; and an impedance value at a parallel resonant frequency of the first kind of piezoelectric acoustic wave resonators is less than that of the second kind of piezoelectric acoustic wave resonator. | 2015-12-24 |
20150372659 | ELASTIC WAVE DEVICE - An elastic wave device is configured such that a first surface acoustic wave chip including a piezoelectric substrate is mounted on a package board, a center of the first surface acoustic wave chip is shifted from a center of the package board when viewed from above, and a crystal Z-axis orientation of the piezoelectric substrate of the first surface acoustic wave chip is slanted to extend toward an outer side portion from a central portion of the package board as it progresses toward an upper surface from a lower surface of the piezoelectric substrate. | 2015-12-24 |
20150372660 | SWITCHABLE FILTERS AND DESIGN STRUCTURES - Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes. | 2015-12-24 |
20150372661 | ACOUSTIC WAVE DEVICE - An acoustic wave device is provided with a low-frequency side filter having a low-frequency side passband, a high-frequency side filter having a high-frequency side passband, and first and second balanced terminals. The low-frequency side filter is connected to a first unbalanced terminal. The low-frequency side passband is a frequency band from a first minimum frequency to a first maximum frequency. The high-frequency side filter is connected to a second unbalanced terminal. The high-frequency side passband is a frequency band from a second minimum frequency to a second maximum frequency. The low-frequency side filter includes a first longitudinally-coupled acoustic wave resonator and a first one-terminal pair acoustic wave resonator connected in series to the first longitudinally-coupled acoustic wave resonator. An antiresonant frequency of the first one-terminal pair acoustic wave resonator is set to be higher than the first maximum frequency and lower than the second minimum frequency. | 2015-12-24 |
20150372662 | WIRELESS CHARGER RECEIVER-SIDE COMMUNICATION INTERFERENCE ELIMINATION - Embodiments of an apparatus are disclosed. In an embodiment, a power receiver unit is disclosed. The power receiver unit includes a power pick-up unit, a communication modulator, and a filter. The power pick-up unit receives a wireless power signal. The communication modulator applies a modulation to the received wireless power signal. The filter suppresses a load signal from a load of the wireless charge receiver to prevent interference with the modulation. | 2015-12-24 |
20150372663 | Impedance Adjusting Device - The present invention is an impedance adjusting device and includes a power output port, a ground terminal, a capacitor assembly including at least one capacitor, and a power output port. The power input port is electronically connected to a power converting circuit of a switching power supply, and the capacitor is electronically connected between the power input port and the ground terminal. The capacitor is connected in parallel to an output capacitor of the power converting circuit to stabilize an impedance of the switching power supply when an audio signal is played at different frequencies. Therefore the audio signal can be played without distortions. | 2015-12-24 |
20150372664 | APPARATUS AND METHODS FOR SWITCH-COUPLED OSCILLATORS - Apparatus and methods for switch-coupled oscillators are disclosed. In certain implementations, an oscillator system includes a primary oscillator, one or more auxiliary oscillators, one or more switching circuits, and an oscillator control circuit. The oscillator control circuit can be used to control the one or more switching circuits to selectively couple the primary oscillator to all or a portion of the one or more auxiliary oscillators. The oscillator control circuit can also disable any auxiliary oscillators that are decoupled from the primary oscillator to reduce power consumption. By selecting a number of auxiliary oscillators to couple to the primary oscillator, the oscillator system can have a configurable phase noise versus power consumption profile. | 2015-12-24 |
20150372665 | QUADRATURE LC TANK DIGITALLY CONTROLLED RING OSCILLATOR - A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on. | 2015-12-24 |
20150372666 | INTEGRATED CIRCUIT - An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage. | 2015-12-24 |
20150372667 | SIGNAL CROSSING DETECTION - Various aspects of the present disclosure are directed to detecting crossings such as zero crossings that can pose problems to circuit operation. In accordance with an example embodiment, two or more circuits are implemented for detecting signal crossings of an electrical signal during respective time cycles, such that at least one of the circuits is operating to detect such a crossing at all times. Each circuit undergoes a reset condition, which is controlled to ensure that at least one circuit remains operating for detecting zero crossing. | 2015-12-24 |
20150372668 | COMPARATOR CONTROL CIRCUIT - A comparator control circuit includes a current source, a first input unit, a second input unit, switches, and a ground terminal. The current source generates an input current. The input current is divided into a first current flowing through the first input unit and a second current flowing through the second input unit. The first input unit receives a signal voltage. The second input unit receives a reference voltage. The first input unit and second input unit are coupled to the current source. The switches include a first switch and a second switch. The second switch has a control voltage. The ground terminal is coupled to the switches. When the first input unit is at high-level, the first switch is switched off and second switch is switched off by the control voltage to stop the second current flowing from the second input unit to the ground terminal. | 2015-12-24 |
20150372669 | Pulse Frequency Modulation Circuit and Power Adapter - Disclosed are a pulse frequency modulation circuit and a power adapter. The pulse frequency modulation circuit includes a first multiplier, a second multiplier, a third multiplier, a divider and an adder sequentially and electrically connected to one another. The second multiplier includes an output terminal connected to an input terminal of the divider, a first input terminal, and a second input terminal connected to an input terminal circuit of the adder. To prevent the uncertain timing of the critical operating status of the time control circuit detected by the conventional zero-crossing detection method, the pulse frequency modulation circuit and power adapter adopt the pulse frequency modulation circuit for computation and output a control signal to control the OFF/ON time of a transistor in the power adapter, so as to control the timing of the operating status of the power adapter precisely. | 2015-12-24 |
20150372670 | Circuit and Method for Detection of Failure of the Driver Signal for Parallel Electronic Switches - There is described a method for driving paralleled electronic switches via a drive signal processing circuit ( | 2015-12-24 |
20150372671 | SWITCHING ELEMENT DRIVING CIRCUIT - A switching element driving circuit includes a current detection unit that outputs a driving stop signal based on a level of current flowing through the switching element, and first and second control elements each connected to a control terminal of the switching element. A comparator controls the first control element based on a result of comparison of an output voltage of the driving circuit main unit with a first reference voltage. A differential amplifier drives the second control element in accordance with a voltage difference between the output voltage of the driving circuit main unit and a second reference so as to maintain the output voltage equal to the second reference voltage. An operation stopping unit stops the comparator and the differential amplifier to drive the first and second control elements, respectively, in response to the driving stop signal. | 2015-12-24 |
20150372672 | POWER DEVICE DRIVE CIRCUIT - A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device. | 2015-12-24 |
20150372673 | PASSIVE DRIVE CONTROL CIRCUIT FOR AC CURRENT - A circuit that may control current to a load without generating a large amount of electromagnetic interference on main lines of an AC power supply for the load and circuit. Control may be effected with silicon controlled rectifiers (SCRs). For instance, the circuit may implement passive triggering using a capacitor between the anode and the gate of an SCR. By using a sufficiently large capacitor, gate current may be applied during a zero crossing of a waveform of the AC power supply in a passive manner without a need to store energy prior to the zero crossing. The circuit may synchronize SCR triggering with a voltage variation in a clean manner, that is, without generating electromagnetic interference. The circuit may be used with an in-line thermostat. However, the circuit may be used in other ways. | 2015-12-24 |
20150372674 | Circuit For Canceling Errors Caused By Parasitic And Device-Intrinsic Resistances In Temperature Dependent Integrated Circuits - In one embodiment, a circuit includes at least one transistor with a base and collector being electrically connected to a ground, and at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter. A sum of the currents A and C are substantially equivalent to a sum of the currents B and D, or a sum of the currents A and D are substantially equivalent to a sum of the currents B and C. The circuit outputs first, second, third, and fourth voltage potentials between the emitter and the base during application of the currents A, B, C, and D, respectively. | 2015-12-24 |
20150372675 | METHOD OF SWITCHING A SEMICONDUCTOR DEVICE - There is provided a method of switching on a semiconductor device. The semiconductor device includes gate, collector and emitter terminals. The method includes the steps of: (i) applying, upon receipt of a switch-on signal, a voltage to the gate terminal of the semiconductor device to decrease a collector-emitter voltage of the semiconductor device to a first predetermined voltage plateau level, and maintaining that voltage to the gate terminal of the semiconductor device for a predetermined time period; (ii) after the predetermined time period, controlling the voltage applied to the gate terminal of the semiconductor device to change the collector-emitter voltage at varying ramp-rates until the collector-emitter voltage reaches a predetermined voltage level; and (iii) controlling the voltage applied to the gate terminal of the semiconductor device to maintain the collector-emitter voltage at the predetermined voltage level. | 2015-12-24 |
20150372676 | GALVANICALLY ISOLATED SWITCH SYSTEM - A galvanically isolated switch system and method comprising a plurality of switches having at least one terminal in series electrical connection, at least one control input electrically connected to at least one of the plurality of switches, wherein the at least one control input is isolated from direct current voltages and at least one passive component connected across the plurality of switches. | 2015-12-24 |
20150372677 | DUAL-RAIL ENCODING - Embodiments may include a method, system and apparatus for providing for encoded dual-rail signal communications in asynchronous circuitry. A dual rail signal pair is received. The dual rail signal pair comprises a first value indicative of a first wait state, a second value indicative of a logic value of a first bit, a third value indicative of a second wait state and a first logic value of a second bit, and/or a fourth value indicative of second wait state and a second logic value of said second bit. | 2015-12-24 |
20150372678 | ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION - A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau. | 2015-12-24 |
20150372679 | PVT Compensation Scheme for Output Buffers - In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit. | 2015-12-24 |
20150372680 | Level-Shifting Device - A voltage level shifting device for driving a capacitive load has an input terminal for receiving a first input signal switchable between a first logic state corresponding to a first reference voltage and a second logic state corresponding to a second reference voltage, and an output terminal for supplying an output signal switchable between a first logic state corresponding to a third reference voltage and a second logic state corresponding to a fourth reference voltage. The device also has a first electronic circuit that is activated following a commutation of the first input signal from the first reference voltage to the second reference voltage for fixing the output terminal to the fourth reference voltage. The device further has a second electronic circuit that is activated following a commutation of the first input signal from the second reference voltage to the first reference voltage. | 2015-12-24 |
20150372681 | SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION IN A DATA ACQUISITION SYSTEM - A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error. | 2015-12-24 |
20150372682 | SAMPLED ANALOG LOOP FILTER FOR PHASE LOCKED LOOPS - An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter. | 2015-12-24 |
20150372683 | DLL CIRCUIT AND SEMICONDUCTOR DEVICE - In accordance with disclosed embodiments, a DLL circuit includes a variable frequency division circuit that uses a variable frequency division ratio to frequency-divide a first clock signal to generate first and second frequency-divided clock signals, a grain size change circuit that changes the count width in synchronization with the first frequency-divided clock signal, a counter circuit that updates the count value in accordance with the count width in synchronization with the second frequency-divided clock signal, and a variable delay circuit that delays the first clock signal on the basis of a delay amount that is in accordance with the count value, thereby generating a second clock signal. When the relationship in magnitude between the phase difference between the first and second clock signals and a predetermined value becomes inverse just after the updating of the count value, the grain size change circuit changes the count width, and the variable frequency division circuit sets the frequency division ratio of the second frequency-divided clock signal being greater than that of the first frequency-divided clock signal. | 2015-12-24 |
20150372684 | APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A DIGITAL DLL WITH CLOCK STOP/START TOLERANCE, APPARATUS AND METHOD FOR ROBUST CLOCK EDGE PLACEMENT, AND APPARATUS AND METHOD FOR CLOCK OFFSET TUNING - Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output. | 2015-12-24 |
20150372685 | SEMICONDUCTOR DEVICE INCLUDING OSCILLATOR - According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits. | 2015-12-24 |
20150372686 | MICROFABRICATED ATOMIC CLOCKS (MFAC) & MAGNETOMETERS (MFAM):SELF-CONDENSING SILICON VAPOR CELL CAVITY STRUCTURE - A microfabricated atomic clock (mfac) or magnetometer (mfam) vapor cell utilizing a method of forming a self-condensing silicon vapor cell cavity structure for the atomic clock or magnetometer. | 2015-12-24 |
20150372687 | QUASI-LINEAR SPIN TORQUE NANO-OSCILLATORS - Techniques, systems, and devices are disclosed for implementing a quasi-linear spin-torque nano-oscillator based on exertion of a spin-transfer torque on the local magnetic moments in the magnetic layer and precession of the magnetic moments in the magnetic layer within a spin valve. Examples of spin-torque nano-oscillators (STNOs) are disclosed to use spin polarized currents to excite nano magnets that undergo persistent oscillations at RF or microwave frequencies. The spin currents are applied in a non-uniform manner to both excite the nano magnets into oscillations and generate dynamic damping at large amplitude as a feedback to reduce the nonlinearity associated with mixing amplitude and phase fluctuations. | 2015-12-24 |
20150372688 | AD CONVERSION APPARATUS, SOLID-STATE IMAGING APPARATUS, AND IMAGING SYSTEM - Provided is an AD conversion apparatus including: a reference signal generating circuit configured to output a first reference signal and a second reference signal, whose voltages change with time; a comparison circuit configured to perform a comparison between a voltage of the analog signal and the voltage of the first reference signal; a control circuit configured to generate and output digital data based on the comparison; a digital-to-analog converter configured to generate, using the second reference signal, a signal whose voltage changes with time from a comparison base voltage, the comparison base voltage being based on the digital data, and configured to output the signal to the comparison circuit; and a counter configured to generate a count value by measuring an elapsed time. The comparison circuit is further configured to perform a comparison between the voltage of the analog signal and the signal output from the digital-to-analog converter. | 2015-12-24 |
20150372689 | THRESHOLD CORRECTION METHOD FOR MULTI-VOLTAGE THRESHOLD SAMPLING DIGITIZATION DEVICE - A threshold correction method is for a multi-voltage threshold sampling digitization device. The method includes: generating a triangular wave, and measuring the slope k1 of the rising edge part and the slope k2 of the falling edge part of the waveform of the triangular wave and the peak value amplitude Vpeak thereof, the width DOT of the part of the pulse higher than an actual working threshold Vt being represented as DOT(Vt)=(Vpeak−Vt)/k1−(Vpeak−Vt)/k2; setting n groups of threshold pairs; calculating a threshold under an actual working state using the measured pulse width DOT according to a formula; and establishing a threshold correction function according to a corresponding relationship between actual working state thresholds and reference voltages set practically, and then correcting a set threshold according to the function. | 2015-12-24 |
20150372690 | CIRCUIT, A TIME-TO-DIGITAL CONVERTER, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER AND A TRANSCEIVER - A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values. | 2015-12-24 |
20150372691 | SYSTEM AND METHOD FOR MULTI CHANNEL SAMPLING SAR ADC - A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation. | 2015-12-24 |
20150372692 | GENERATING A CODE ALPHABET OF SYMBOLS TO GENERATE CODEWORDS FOR WORDS USED WITH A PROGRAM - Provided are a computer program product, system, and method for generating a code alphabet for use by a deployed program to determine codewords for words. A first code alphabet has a first number of symbols that provide variable length codings of the words. A second code alphabet is generated having a second number of symbols formed by merging the symbols in the first code alphabet, wherein the second code alphabet comprises the code alphabet used by the deployed program. | 2015-12-24 |
20150372693 | ENCODING OF PLAIN ASCII DATA STREAMS - A pair of adjacent characters in a plain ASCII data stream is examined for a condition that the pair contains a consonant followed by one of a set of characters, or a vowel followed by one of the set of characters. The set of characters is selected only from vowels and the space character. If the condition is satisfied, the pair is encoded as a corresponding extended ASCII code. If the condition is not satisfied, the first character of the pair is emitted as a corresponding plain ASCII code, and a next pair is formed with the second character of the (previous) pair as the first character and a next character of the plain ASCII stream as the second character. The next pair as well as further pairs are examined for the condition and correspondingly processed. Compression of the plain ASCII data stream is thereby achieved. | 2015-12-24 |
20150372694 | METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING A LOW-DENSITY PARITY CHECK CODE - A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups, determining an order of the plurality of groups to be shortened, according to a code rate, determining a length of information bits to be obtained by shortening the plurality of groups, shortening the plurality of groups on a group basis in the determined order, based on the determined length of the information bits, and LDPC-encoding shortened information bits. | 2015-12-24 |
20150372695 | METHOD AND APPARATUS OF LDPC DECODER WITH LOWER ERROR FLOOR - A method of error correction using low density parity check (LDPC) codes is disclosed. A communications device receives a codeword and detects one or more bit errors in the received codeword using an LDPC code. The device then generates a corrected codeword based, at least in part, on a set of unsatisfied check nodes of the LDPC code. The device may determine that the one or more bit errors are associated with an absorption set of the LDPC code. The device may also determine a plurality of candidate codewords based on the set of unsatisfied check node and select the corrected codeword from the plurality of candidate codewords. Each of the plurality of candidate codewords may represent a valid codeword associated with the LDPC code. | 2015-12-24 |
20150372696 | Arrangement and Method for Decoding a Data Word with the Aid of a Reed-Muller Code - An arrangement is provided for decoding a data word with the aid of a Reed-Muller code, which consists of the following components: (1) N input terminals, (2) a first level of E<>D. | 2015-12-24 |
20150372697 | ON-DIE ERROR DETECTION AND CORRECTION DURING MULTI-STEP PROGRAMMING - An apparatus having a memory and a controller is disclosed. The memory is configured to (i) program a protected lower unit in a lower page of a location, (ii) generate a corrected lower unit by correcting the protected lower unit using a first error correction code and (iii) program a protected upper unit in an upper page of the location based on the corrected lower unit. The controller is configured to generate the protected upper unit by encoding an upper write data item using a second error correction code. The controller is on a separate die as the memory. | 2015-12-24 |
20150372698 | SOFTWARE PROGRAMMABLE CELLULAR RADIO ARCHITECTURE FOR TELEMATICS AND INFOTAINMENT - A cellular radio architecture for a vehicle that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a triplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the triplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the triplexer. | 2015-12-24 |
20150372699 | HIGH OVERSAMPLING RATIO DYNAMIC ELEMENT MATCHING SCHEME FOR HIGH DYNAMIC RANGE DIGITAL TO RF DATA CONVERSION FOR CELLULAR COMMUNICATIONS - An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal. | 2015-12-24 |
20150372700 | SOFTWARE PROGRAMMABLE, MULTI-SEGMENT CAPTURE BANDWIDTH, DELTA-SIGMA MODULATORS FOR CELLULAR COMMUNICATIONS - A cellular radio architecture for a vehicle that includes a triplexer coupled to an antenna structure and including three signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the triplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter. | 2015-12-24 |
20150372701 | MODULATION CIRCUIT OF DIGITAL TRANSMITTER, DIGITAL TRANSMITTER, AND SIGNAL MODULATION METHOD - The present invention relates to a modulation circuit of a digital transmitter, a digital transmitter, and a signal modulation method. The modulation circuit includes: a first synchronizing circuit and a digital modulator, where the first synchronizing circuit separately perform phase delay on a first local-frequency signal or a second local-frequency signal to obtain corresponding delay signals, and perform phase adjustment on a digital baseband signal by using the delay signals, to generate a first adjusted signal and a second adjusted signal; and the digital modulator modulates the first adjusted signal by using the first local-frequency signal, to generate a first radio-frequency signal, and modulates the second adjusted signal by using the second local-frequency signal, to generate a second radio-frequency signal. | 2015-12-24 |
20150372702 | FILTERS FOR A FREQUENCY BAND - An apparatus includes a first filter tuned to a sub-band of a frequency band and a second filter tuned to the frequency band. The first filter is configured to be coupled to a receiver based on a first mode. The second filter is configured to be coupled to the receiver based on a second mode. | 2015-12-24 |
20150372703 | WIRELESS COMMUNICATION APPARATUS, ANALYSIS APPARATUS, ANALYSIS METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM ON WHICH PROGRAM HAS BEEN STORED - Provided are a wireless communication apparatus, an analysis apparatus, an analysis method and a non-transitory computer readable medium on which a program has been stored, wherein a threshold value to be used for determining whether received radio waves are noise or not can be determined independently of an operator's capability. A reception means receives radio waves. A threshold value determination means determines, on the basis of a number of intersections between a variation curve of radio wave intensity relative to the frequencies of the radio waves received by the reception means and a first line indicating a given radio wave intensity, a threshold value of radio wave intensity to be used for determining whether the received radio waves are noise or not. | 2015-12-24 |
20150372704 | RECEPTION DEVICE AND ELECTRONIC APPARATUS - There is provided a reception device including first and second reception circuits configured to receive transmission signals, a first oscillation circuit configured to generate a differential signal having a predetermined frequency on the basis of an oscillation signal acquired from a connected crystal oscillator, and to supply the generated differential signal to the first reception circuit as a reference frequency signal, and a second oscillation circuit configured to be supplied with an oscillation signal having one of phases in the differential signal acquired by the first oscillation circuit, to generate a differential signal having a predetermined frequency on the basis of the supplied oscillation signal, and to supply the generated differential signal to the second reception circuit as a reference frequency signal. | 2015-12-24 |
20150372705 | HOLDING AID TO TYPE ON A TOUCH SENSITIVE SCREEN FOR A MOBILE PHONE, PERSONAL, HAND-HELD, TABLET-SHAPED, WEARABLE DEVICES AND METHODS OF USE - The object of this invention is a holding aid or apparatus H (FIG. | 2015-12-24 |
20150372706 | SHORT-RANGE WIRELESS COMMUNICATION APPARATUS - A short-range wireless communication apparatus is disclosed. The short-range wireless communication apparatus comprises: multiple connection devices and a control device. The connection devices are capable of simultaneously connecting multiple communication interfaces to a communication counterparty apparatus to enable sound data transfer. When the control device determines that, in cases where the communication interfaces are communicably connected, there arises a request to start outputting the sound data transferred by one of the communication interfaces, the control device disconnects another one of the communication interfaces while keeping the one of the communication interfaces connected and causes a sound data output device to output the sound data transferred from the communication counterparty apparatus by the one of the communication interfaces. | 2015-12-24 |
20150372707 | MILLIMETER WAVE WIRELESS COMMUNICATION BETWEEN COMPUTING SYSTEM AND DOCKING STATION - A system includes at least one computer; at least one dock which engages the computer, and at least first and second millimeter wave transceivers which transmit information between the computer and the dock. The first transceiver sends signals having a first polarization and the second transceiver sends signals having a second polarization different from the first polarization. | 2015-12-24 |
20150372708 | COVER FOR PACKAGING AND SUPPORTING TABLET COMPUTER - A cover for packaging and supporting a tablet computer has a lower casing for protecting a tablet computer; an upper cover rotatably connected to the lower casing for protecting the screen of the tablet computer from damage; the upper cover being formed with at least one foldable line area for folding the upper cover along the foldable line area wherein the upper cover is used as a cover and a supporter; the upper cover rotates along the lower casing with an angle greater than 180 degrees; the lower casing is folded along the foldable line areas so as to be formed as a supporter of the lower casing for supporting the tablet computer therein. Thus the computer can stand; and, the angle between the upper cover and the lower casing is adjustable so as to control the standing height of the tablet computer. | 2015-12-24 |
20150372709 | CONCURRENCY-MODE SCAN SCHEDULING FOR WIRELESS DEVICES - A wireless device operates as both a station and one or more access points. In the wireless device, a scan window of a specified duration is requested to start at a first time, to scan for access points external to the wireless device in accordance with operation of the wireless device as a station. It is determined that a beacon scheduled for transmission or reception at a second time conflicts with the requested scan window. In response, the beacon is transmitted or received at the second time and at least a portion of the scan window is delayed until after the beacon has been transmitted or received. | 2015-12-24 |
20150372710 | REVERSIBLE TDD TRANSCEIVER - A radio transceiver, particularly for use in a time division duplex system, has two reversible transceiver chains, each containing a respective radio frequency mixer; and an intermediate frequency generator, for receiving a baseband signal containing data for transmission, and for generating signals at two different intermediate frequencies modulated with said data. In a receive mode, each transceiver chain receives a respective signal at a respective radio frequency, and the respective radio frequency mixer downconverts the respective signal to a respective intermediate frequency. In transmit mode, one of said signals at the two different intermediate frequencies modulated with said data is passed to the respective radio frequency mixer for upconversion to the respective RF frequency. An AIS transponder includes such a radio transceiver. Miniaturization is helped by reusing certain circuit areas for both transmit and receive. | 2015-12-24 |
20150372711 | DATA COMPRESSION METHOD, DATA RESTORATION METHOD, APPARATUSES, AND SYSTEM - The present invention relates to a data compression method, a data restoration method, apparatuses, and a system. The data compression method includes: acquiring a first digital signal; acquiring a first compressed signal by performing down-sampling processing on the first digital signal, where a sampling frequency of the first compressed signal is not less than a frequency threshold, and the frequency threshold is twice a baseband cut-off frequency of the first digital signal; and sending the first compressed signal by using a transmission format based on the common public radio interface CPRI protocol. Frequency decrease is performed before data is transmitted by using the CPRI protocol, so as to reduce an amount of data to be transmitted by using a CPRI, and improve data transmission efficiency, or, in other words, increase a quantity of RRUs or BBUs that can be supported on per CPRI. | 2015-12-24 |
20150372712 | ASYMMETRICAL FORWARD/REVERSE TRANSMISSION BANDWIDTH - A wireless communications system employs code-division multiple access information transmission techniques where the uplink and downlink transmission bandwidths are unequal. The higher bandwidth is an integer multiple of the lower bandwidth. The present system requires a base station and a subscriber unit to have two pseudo-random code generators which can be clocked separately. Alignment of the uplink and downlink pseudo-random spreading codes is achieved by truncating the code sequence for the lower speed link at the conclusion of a complete code sequence for the higher speed link. | 2015-12-24 |
20150372713 | METHOD FOR SELF-ADAPTIVELY DEMODULATING QUASI-ORTHOGONAL SIGNALS, DEMODULATION UNIT AND RADIO SIGNAL RECEIVER - A method for decoding a data symbol carried by a signal received by a receiver of a communication system, the data symbol being modulated by a spread code sequence selected from a plurality of spread code sequences being quasi-orthogonal to each other to differentiate the symbol from other data symbols, and being received as a set of modulation bits, the method including a step of correlating the modulated data symbol received with each of the plurality of spread code sequences, and the correlating step is preceded by a step of sub-sampling the modulated data symbol received to mask one or more of the modulation bits therein, such that the step of correlating the sub-sampled data symbol received is carried out only for the non-masked modulation bits. It extends to a demodulation unit configured for the implementation of this method, and to a receiver integrating such a unit. | 2015-12-24 |
20150372714 | METHOD AND RECEIVER FOR RECEIVING A BINARY OFFSET CARRIER COMPOSITE SIGNAL - A data processor selects a set of BOC correlations in accordance with a BOC correlation function for the sampling period if the primary amplitude exceeds or equals the secondary amplitude for the sampling period. The data processor selects a set of QBOC correlations in accordance with a QBOC correlation function for the sampling period if the secondary amplitude exceeds the primary amplitude for the sampling period. The data processor uses either the BOC correlation function or the QBOC correlation function, whichever with greater amplitude, at each sampling period to provide an aggregate correlation function that supports unambiguous code acquisition of the received signal. | 2015-12-24 |
20150372715 | ROBUST TIME SHIFT TRACKING UWB RECEIVER - A robust time shift tracking UWB receiver. After translating in baseband by a quadrature demodulator, the received UWB pulsed signal is integrated on successive time windows, and then sampled. The complex samples are then correlated with a coding sequence from the transmitter and then transmitted on the one hand to a phase estimator and a demodulating/detecting module. The latter estimates the symbol emitted and provides it to the estimator which removes the modulation effect for estimating, at each time-symbol, the phase of the complex samples. A phase rotation follow-up module determines a compensated phase rotation and a non-compensated phase rotation from a reference instant. Controlling means deduce from the non-compensated phase rotation a time offset to be applied to the integration windows. | 2015-12-24 |
20150372716 | METHOD FOR SETTING FREQUENCY CHANNELS IN A MULTI-HOP WIRELESS MESH NETWORK - A method for setting frequency channels in a multi-hop wireless mesh network including a plurality of nodes. Each node hops on frequency channels, with a hop period, according to a frequency channels hopping sequence. All data packets transmitted by the nodes have a duration strictly longer than the hop period. When a given node of the plurality of nodes is in a first transmit mode in order to transmit a data packet, it carries out steps of: selecting a transmit frequency channel as a function of the frequency channels hopping sequence; and transmitting the data packet using, for the entire duration of the data packet, the selected transmit frequency channel. | 2015-12-24 |
20150372717 | SLOTTED MESSAGE ACCESS PROTOCOL FOR POWERLINE COMMUNICATION NETWORKS - A slotted message access protocol can be implemented for transmitting messages in a communication network. A beacon period may be divided into multiple communication slots. A master device may register a client device and provide registration information to allow the client device to operate in the communication network. The registration information may be determined based, at least in part, on a location of the client device in the communication network. As part of the registration information, contention-free communication slots may be assigned for use by the client device. Contention-based communication slots may also be assigned to a group of client devices. Messages may also be segmented depending on whether the message is transmitted in a contention-free or a contention-based communication slot. Furthermore, a relay device may be designated to retransmit a message (received from an original transmitting device) during a communication slot assigned to the original transmitting device. | 2015-12-24 |
20150372718 | VARIABLE INPUT IMPEDANCE FOR POWERLINE COMMUNICATIONS - A powerline communication (PLC) device can receive a PLC signal transmitted through a powerline medium. The PLC device can compare a destination address of the PLC signal to a device address associated with the PLC device. The input impedance of the PLC device can be configured to an impedance value that is different from an impedance of the powerline medium when the destination address does not match the device address. The input impedance of the PLC device can be returned to an initial value when a PLC message included in the PLC signal is no longer received. | 2015-12-24 |
20150372719 | BUSINESS CONTACT INFORMATION EXCHANGING APPARATUS AND METHOD - A plaque including an embedded near field communication (NFC) chip is provided. The plaque may be formed to rest on a user's desk. The NFC chip includes information such as the user's name, business address, email address, phone number and the like. A customer may tap their smart device on the plaque to receive information that is typically on a business card. | 2015-12-24 |
20150372720 | SECURE NEAR FIELD COMMUNICATION (NFC) HANDSHAKE - Technologies are presented for securing NFC exchange through movement of at least one of the communicating devices. In some examples, a first device, utilizing a communication module and a processor, may transmit an initial NFC handshake signal as the first device is being moved relative to a second device. The second device, utilizing a communication module, two or more antennae, and a processor, may receive the initial NFC handshake signal from the first device. Each device may record a movement of the first device. The second device may transmit a message to the first device that includes a recording of the movement at the second device and a temporary secret. Once the first device determines that the movement recorded at the second device matches the movement recorded at the first device, the first device may use the temporary secret to encrypt further communication with the second device. | 2015-12-24 |
20150372721 | Configuring User Equipment to Display Information Through a Cover Window - A cover apparatus for a user equipment includes a front surface connected to a user equipment and positioned to cover and prevent user viewing of a first portion of a display device. The front surface has a window providing user viewing of a second portion of the display device while the front surface covers the first portion of the display device. The cover apparatus further includes a NFC tag circuit configured to become powered by inductive coupling to signals emitted by a NFC reader within the user equipment to temporarily operate to transmit cover configuration data to the NFC reader within the user equipment. The cover configuration data provides information to an application executed by a processor of the user equipment to determine a location of the window in the front surface and to configure information displayed in the second portion of the display device. | 2015-12-24 |
20150372722 | DOPPLER FREQUENCY SHIFT COMPENSATION FOR WIRELESS COMMUNICATION - Technologies and implementations for Doppler frequency shift compensation are generally disclosed. | 2015-12-24 |
20150372723 | METHOD AND APPARATUS FOR MITIGATING FEEDBACK IN A DIGITAL RADIO RECEIVER - Embodiments of an acoustic feedback suppressor determine the energy in each of a plurality of frequency bands of frames of an audio signal. The energy in each of the plurality of frequency bands is compared to characteristic of human voice to determine that a present frame contains content that is not likely human voice and exhibits a characteristic of feedback. Upon determining that feedback is occurring, an adaptive gain reduction is applied to the band in which feedback is suspected to be occurring. | 2015-12-24 |
20150372724 | METHOD AND APPARATUS FOR CONFIGURING COORDINATED MULTI-POINT MEASUREMENT SET - Method and an apparatus for configuring a coordinated multi-point measurement set. An embodiment of the present invention provides a method at a neighboring base station side ( | 2015-12-24 |
20150372725 | POWER SENSING IN WIRELESS SYSTEM - Representative implementations of devices and techniques provide transmit power detection for an antenna of a wireless system having two or more transmit antennas. A correlation is reduced between a transmit signal of the antenna and signals from other antennas. | 2015-12-24 |
20150372726 | ITERATIVE INTERFERENCE ALIGNMENT (IA) METHOD AND APPARATUS FOR PERFORMING DOWNLINK MULTI-USER MULTIPLE-INPUT AND MULTIPLE-OUTPUT (DL MU-MIMO) COMMUNICATION - Provided is an iterative interference alignment (IA) method and apparatus for performing a downlink multi-user multiple-input and multiple-output (DL MU-MIMO), including transmitting, to a user terminal, a transmission beamforming vector generated arbitrarily, receiving, from the user terminal, a reception beamforming vector calculated to minimize interference based on the transmission beamforming vector, and updating the transmission beamforming vector based on the reception beamforming vector, the iterative IA method may further include calculating a transmission beamforming vector space minimizing interference of an inter-basic service set based on the reception beamforming vector, calculating a transmission beamforming matrix minimizing interference of an intra-basic service set, based on the reception beamforming vector, and updating the transmission beamforming vector based on the transmission beamforming matrix and the transmission beamforming vector space. | 2015-12-24 |
20150372727 | JOINT PRECODER AND RECEIVER DESIGN FOR MU-MIMO DOWNLINK - Various communication systems may benefit from joint precoder and receiver designs for multi-user multiple-input and multiple-output. For example, machine-type communication in long term evolution communication systems may benefit from such designs. A method can include determining channel status information of a current connection. The method can also include indicating the channel status information to a transmitter. The method can further include receiving weight values for a first receiver filter, in response to the channel status information. The method can also include defining the first receiver filter based on the weight values. The method can further include determining effective channel status information of a current connection, and interference from other transmitters. The method can also include defining a second receiver filter based on the weight values, the effective channel status information of the current connection, and the interference. | 2015-12-24 |
20150372728 | OFDM SIGNAL COMPRESSION - Methods and apparatuses for fronthaul signal compression and decompression. An apparatus for fronthaul signal compression includes a receiver, signal processing circuitry, and a fronthaul interface. The receiver is configured to receive one or more signals comprising complex samples. The signal processing circuitry is configured to construct vectors representing at least a portion of the complex samples; map the vectors to codeword indices in a vector quantization codebook; and process the codeword indices into an output signal. The fronthaul interface is configured to transmit the output signal via a fronthaul communication link of a wireless network. The vectors may be constructed according to the selected vectorization method. The vector quantization codebook may be selected from a set of vector quantization codebooks generated based on training signals and signaled. | 2015-12-24 |
20150372729 | TERMINAL APPARATUS, BASE STATION APPARATUS, AND METHOD FOR SHARING CODEBOOK IN COMMUNICATION SYSTEM - A communication system, a terminal apparatus, a base station apparatus, and a method for sharing a codebook are provided that make it possible to improve system capacity by using precoding according to a cell environment. In a communication system in which beam directivity control is performed by precoding using a codebook that is common between a base station ( | 2015-12-24 |
20150372730 | Beam Information Exchange between Base Stations - A base station receives a message comprising at least one index identifying a subset of a second plurality of beamforming codewords. Each of the second plurality of beamforming codewords is identifiable by an index presented by a number of bits. The number of bits is greater than or equal to log | 2015-12-24 |
20150372731 | Method for Determining a Codebook, Information Feedback Method and Devices Thereof - A method for determining a codebook, information feedback method and devices thereof. For precoding of a differential dual codebook, the method includes: providing N1 codewords in a second codebook, so that complex codewords obtained by a product of codewords in the second codebook and a first codebook satisfy corresponding antenna configuration(s), where, N1 is greater than or equal to 16. Or for precoding of a GoB dual codebook, the method includes: codewords in a first codebook being: | 2015-12-24 |
20150372732 | EFFICIENT FEEDBACK TRANSMISSION METHOD IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM AND DEVICE FOR SAME - The present invention relates to a method by which a terminal feeds back channel state information for downlink transmission in a wireless communication system supporting multiple antennas. More specifically, the present invention comprises a step of transmitting a first precoding matrix index (PMI) and a second PMI for each sub-band, wherein a precoding matrix preferred by the terminal is instructed to combine the first PMI and the second PMI, and a precoding codebook in which a portion of a plurality of bits forming the second PMI is additionally used to form the first PMI is applied. | 2015-12-24 |
20150372733 | METHOD FOR EFFICIENTLY TRANSMITTING SIGNAL IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME - The present invention relates to a method for a transmitting end efficiently transmitting a signal in a wireless communication system supporting a multi-antenna and an apparatus for same. More particularly, the method comprises a step of transmitting a downlink signal based on a precoding matrix (W) for an antenna comprising a plurality of antenna elements aligned perpendicularly, wherein the precoding matrix (W) corresponds to a codebook configured so that phase increase is limited with respect to a plurality of precoding vector values populating a same column. | 2015-12-24 |
20150372734 | METHOD FOR TRANSMITTING SOUNDING REFERENCE SIGNAL IN MULTIPLE ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR - A method for transmitting sounding reference signals by a user equipment (UE) in a wireless communication system, and the UE therefore are discussed. The method according to one embodiment includes configuring an initial cyclic shift (CS) value and an initial comb value via a higher layer; and setting a comb value for at least one antenna port according to an Equation A. The method according to the embodiment further includes transmitting the sounding reference signals using the comb value via at least one antenna port. | 2015-12-24 |
20150372735 | Proximity Activated Antenna Switch System and Method Therefor - A state of a detection signal received from a proximity detector is determined. The first proximity detector is incorporated with a primary antenna at an information handling system. The proximity detector can assert the detection signal in response to detecting that an object external to the information handling system is located close to the proximity detector. A second antenna is coupled to a wireless communication circuit at the information handling system if the detection signal is asserted. | 2015-12-24 |