52nd week of 2020 patent applcation highlights part 62 |
Patent application number | Title | Published |
20200403002 | 3-DIMENSIONAL NOR MEMORY ARRAY ARCHITECTURE AND METHODS FOR FABRICATION THEREOF - A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack | 2020-12-24 |
20200403003 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars. | 2020-12-24 |
20200403004 | THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATING METHOD THEREOF - Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island. | 2020-12-24 |
20200403005 | MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC SUPPORT PILLARS AND METHODS FOR MAKING THE SAME - A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support opening. The support pillar structure lacks a semiconductor material portion which is in contact with the semiconductor material layer. | 2020-12-24 |
20200403006 | Device Disaggregation For Improved Performance - The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer. | 2020-12-24 |
20200403007 | SUBSTRATE-LESS FINFET DIODE ARCHITECTURES WITH BACKSIDE METAL CONTACT AND SUBFIN REGIONS - Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts. | 2020-12-24 |
20200403008 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING SAME - An array substrate and a method of manufacturing the same are provided. By setting a gate driver on array (GOA) signal area above a GOA driving circuit area, space occupied by a GOA circuit area is reduced, thereby reducing a frame of a display device, and further increasing a screen ratio of the display device. | 2020-12-24 |
20200403009 | Flexible Display Device - A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device. | 2020-12-24 |
20200403010 | DISPLAY DEVICE - The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal. | 2020-12-24 |
20200403011 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor and a method for manufacturing the same, and a display device including the same are disclosed, in which a P type semiconductor characteristic is realized using an active layer that includes a Sn based oxide. The thin film transistor comprises an active layer that includes an Sn(II)O based oxide; a metal oxide layer being in contact with one surface of the active layer; a gate electrode overlapped with the active layer; a gate insulating film provided between the gate electrode and the active layer; a source electrode being in contact with a first side of the active layer; and a drain electrode being in contact with a second side of the active layer. | 2020-12-24 |
20200403012 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present invention provides a display panel and a manufacturing method thereof. The display panel comprises an array substrate provided with a first inclined plane at an edge of one side of the array substrate; a color filter substrate disposed on one side surface of the array substrate; the color filter substrate provided with a second inclined plane at an edge of one side of the color filter substrate, and the second inclined plane on a same plane with the first inclined plane; and a chip on film bonded to the first inclined plane and the second inclined plane. A manufacturing method of the display panel comprises an array substrate providing step, a color filter substrate disposing step, a cutting step and a bonding step. The technical effect of the present invention is reducing the thickness of the bottom frame of the display panel and increasing the screen ratio. | 2020-12-24 |
20200403013 | OPTOELECTRONIC DEVICE ARRANGED AS A MULTI-SPECTRAL LIGHT SENSOR HAVING A PHOTODIODE ARRAY WITH ALIGNED LIGHT BLOCKING LAYERS AND N-WELL REGIONS - An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band. | 2020-12-24 |
20200403014 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - An image sensor includes a substrate including a plurality of pixel regions and having a trench between the pixel regions, a photoelectric conversion part in the substrate of each of the pixel regions, and a device isolation pattern in the trench. The device isolation pattern defines an air gap. The device isolation pattern has an intermediate portion and an upper portion narrower than the intermediate portion. | 2020-12-24 |
20200403015 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side. | 2020-12-24 |
20200403016 | IMAGING DEVICE AND ELECTRONIC DEVICE - A highly sensitive imaging device that can perform imaging even under a low illuminance condition is provided. One electrode of a photoelectric conversion element is electrically connected to one of a source electrode and a drain electrode of a first transistor and one of a source electrode and a drain electrode of a third transistor. The other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor. The other electrode of the photoelectric conversion element is electrically connected to a first wiring. A gate electrode of the first transistor is electrically connected to a second wiring. When a potential supplied to the first wiring is HVDD, the highest value of a potential supplied to the second wiring is lower than HVDD. | 2020-12-24 |
20200403017 | INTEGRATED PHOTOSENSITIVE MODULE, PHOTOSENSITIVE ASSEMBLY, CAMERA MODULE AND PREPARATION METHOD THEREFOR - Disclosed is a photosensitive module ( | 2020-12-24 |
20200403018 | TEXTURE RECOGNITION ASSEMBLY AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS - A texture recognition assembly, a method of manufacturing the same, and a display apparatus are disclosed. The texture recognition assembly includes a photosensitive sensing layer, a texture contact layer, and a filter film layer disposed at a side of the photosensitive sensing layer proximate to the texture contact layer. The filter film layer is configured to filter visible light with a wavelength greater than or equal to λ. A value of λ is greater than or equal to 600 nm. | 2020-12-24 |
20200403019 | SEMICONDUCTOR APPARATUS AND EQUIPMENT - A semiconductor apparatus according to the present invention includes: a semiconductor component including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to a first cell and a second cell, a second row pad connected to a row wiring connected to a third cell and a fourth cell, and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad crosses a straight line connecting the second row pad and the column pad. | 2020-12-24 |
20200403020 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked. | 2020-12-24 |
20200403021 | SOLID-STATE IMAGE-CAPTURING ELEMENT AND ELECTRONIC DEVICE - The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode. | 2020-12-24 |
20200403022 | IMAGE SENSOR COMPRISING ENTANGLED PIXEL - A depth sensor includes a first pixel including a plurality of first photo transistors each receiving a first photo gate signal, a second pixel including a plurality of second photo transistors each receiving a second photo gate signal, a third pixel including a plurality of third photo transistors each receiving a third photo gate signal, a fourth pixel including a plurality of fourth photo transistors each receiving a fourth photo gate signal, and a photoelectric conversion element shared by first to fourth photo transistors of the plurality of first to fourth photo transistors. | 2020-12-24 |
20200403023 | WAVELENGTH TUNABLE NARROW BAND FILTER - Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer. | 2020-12-24 |
20200403024 | Biometric Sensor and Methods Thereof - A method of fabricating a sensing apparatus is disclosed. The method includes providing a substrate that includes a plurality of image sensors, forming an optical filtering film on the substrate, and forming a collimator on the optical filtering film. The method further includes forming a blocking layer on the collimator and forming an illumination layer on the blocking layer. The illumination layer is configured to illuminate an object placed above the illumination layer. The image sensors are configured to detect a portion of light reflected from the object. | 2020-12-24 |
20200403025 | IMAGE SENSOR - An image sensor and a method of manufacturing thereof are provided. The image sensor includes a substrate, a grid structure, and color filters. The substrate includes a pixel separation structure defining pixel regions, and a sub-pixel regions for each pixel region. The grid structure is disposed on the substrate and includes first fence segments provided between the sub-pixel regions, and second fence segments provided between neighboring pixel regions. The grid structure defines openings corresponding respectively to the sub-pixel regions. The color filters are disposed in the openings defined by the grid structure. Each of the color filters has a flat top surface and the flat top surface of each color filter is parallel to a bottom surface thereof. | 2020-12-24 |
20200403026 | SYSTEMS AND METHODS FOR COAXIAL MULTI-COLOR LED - A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. In some embodiments, each LED structure is connected to a pixel driver and a shared P-electrode. The LED structures are bonded together through bonding layers. In some embodiments, reflection layers are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness. | 2020-12-24 |
20200403027 | COMPONENT WITH ELECTRICALLY CONDUCTIVE CONVERTER LAYER - A component may include a semiconductor body and a converter layer. The converter layer may have phosphor particles and an electrically conductive matrix material where the phosphor particles are embedded in the matrix material. The converter layer may be arranged on the semiconductor body and may have a plurality of sublayers that are spatially set apart from one another and can be electrically contacted individually. The semiconductor body may have an active zone for producing electromagnetic radiation where the sublayers of the converter layer are designed for local electrical contacting of the active zone. | 2020-12-24 |
20200403028 | DISPLAY DEVICE, DISPLAY MODULE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF DISPLAY DEVICE - One embodiment of the present invention is a display device including a first insulating layer, a second insulating layer, a first transistor, a second transistor, a first light-emitting diode, a second light-emitting diode, and a color conversion layer. The first insulating layer is over the first transistor and the second transistor. The first light-emitting diode and the second light-emitting diode are over the first insulating layer. The color conversion layer is over the second light-emitting diode. The color conversion layer is configured to convert light emitted from the second light-emitting diode into a light having a longer wavelength. The first transistor and the second transistor each include a metal oxide layer and a gate electrode. The metal oxide layer includes a channel formation region. A top surface of the gate electrode is level or substantially level with a top surface of the second insulating layer. | 2020-12-24 |
20200403029 | DISPLAY DEVICE - A display device includes a substrate; a first electrode and a second electrode arranged to be spaced apart from each other on the substrate; a first insulating layer on the substrate; a light emitting element on the first insulating layer, located between the first electrode and the second electrode, and including a first end portion and a second end portion; a third electrode on the substrate and electrically connected to the first electrode and the first end portion; a fourth electrode on the substrate and electrically connected to the second electrode and the second end portion; a second insulating layer on the substrate and covering the light emitting element, the third electrode, and the fourth electrode; and a light diffusion layer on the second insulating layer and including a light diffusion particle. | 2020-12-24 |
20200403030 | DISPLAY DEVICE - A display device is provided. The display device includes a first electrode including a first electrode surface extending in a first direction and a second electrode surface connected to one end of the first electrode surface and extending in a second direction that is different from the first direction, a second electrode including a third electrode surface extending in the first direction and spaced apart from the first electrode surface and facing the first electrode surface, and a fourth electrode surface extending in the second direction and spaced apart from the second electrode surface and facing the second electrode surface, and at least one light emitting element between the first electrode and the second electrode and including a first light emitting element between the first electrode surface and the third electrode surface and a second light emitting element between the second electrode surface and the fourth electrode surface. | 2020-12-24 |
20200403031 | DEVICES AND SYSTEMS INCORPORATING ENERGY HARVESTING COMPONENTS/DEVICES AS AUTONOMOUS ENERGY SOURCES AND AS ENERGY SUPPLEMENTATION, AND METHODS FOR PRODUCING DEVICES AND SYSTEMS INCORPORATING ENERGY HARVESTING COMPONENTS/DEVICES - An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output. | 2020-12-24 |
20200403032 | MRAM INTEGRATION WITH BEOL INTERCONNECT INCLUDING TOP VIA - A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad. | 2020-12-24 |
20200403033 | VERTICALLY STACKED MEMORY ELEMENTS WITH AIR GAP - A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines. | 2020-12-24 |
20200403034 | STACKED RESISTIVE MEMORY WITH INDIVIDUAL SWITCH CONTROL - A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device. | 2020-12-24 |
20200403035 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell and a first select transistor. The memory cell includes: a variable resistance memory region; a first semiconductor layer being in contact with the variable resistance memory region; a first insulating layer being in contact with the first semiconductor layer; and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes: a second semiconductor layer; a second insulating layer being in contact with the second semiconductor layer; and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer. | 2020-12-24 |
20200403036 | Electrostatic Discharge Protection Devices Using Carbon-Based Diodes - The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers. | 2020-12-24 |
20200403037 | LIGHT EMITTING DEVICE AND DISPLAY APPARATUS INCLUDING THE LIGHT EMITTING DEVICE - Provided a light emitting device including a first metal reflection layer including a phase modulation surface configured to magnetically resonate incident light, a color conversion layer provided on the phase modulation surface of the first metal reflection layer and including a photoluminescent material, a first electrode provided on the color conversion layer opposite to the first metal reflection layer, a white organic light emitting layer provided on the first electrode opposite to the color conversion layer, and a second electrode provided on the white organic light emitting layer opposite to the first electrode. | 2020-12-24 |
20200403038 | ELECTROLUMINESCENCE DISPLAY HAVING MICRO-LENS LAYER - The present disclosure relates to an electroluminescence display having micro-lens layer. The electroluminescence display according to the present disclosure comprises: a lower substrate having a light emitting layer at middle portions; an upper substrate facing the upper substrate; a dam disposed at circumferences of the lower substrate and surrounding the light emitting layer; a filling layer filling space surrounded by the dam and covering the light emitting layer; a micro-lens layer disposed on the inner surface of the upper substrate; a color filter disposed as corresponding to the light emitting layer under the micro-lens layer; and a black matrix disposed at a side of the color filters under the micro-lens layer. | 2020-12-24 |
20200403039 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE DISPLAY DEVICE - A display device includes a display member including a substrate and a plurality of light-emitting elements disposed on the substrate, a sensing member disposed on the display member, and a polarizing member disposed on the sensing member. The sensing member includes a sensing insulating layer and a sensing conductive layer disposed on the sensing insulating layer. The polarizing member includes a polarizing layer and a polarizing adhesive layer disposed between the polarizing layer and the sensing conductive layer. The polarizing adhesive layer is in contact with the sensing conductive layer. | 2020-12-24 |
20200403040 | DISPLAY APPARATUS - A display apparatus includes: a display panel comprising a transmission area, a display area, and a middle area that includes at least one groove and is located between the transmission area and the display area; an input sensing layer stacked on the display panel, wherein a metal layer that overlaps the at least one groove in a plan view is in one of the display panel and the input sensing layer. | 2020-12-24 |
20200403041 | FOLDABLE DISPLAY DEVICE - A display device includes a flexible display module and provides a display surface on which an image is displayed. The flexible display module includes a display panel including a light-emitting device and a sensor unit disposed on the display panel. The sensor unit senses pressure applied to the flexible display module in a folded-in mode in which the flexible display module is folded such that a portion of the display surface faces another portion of the display surface. | 2020-12-24 |
20200403042 | PIXEL STRUCTURE, DISPLAY PANEL AND DISPLAY APPARATUS - The present disclosure provides a pixel structure, a display panel and a display apparatus. The pixel structure according to an embodiment of the present disclosure includes a pixel structure including: a plurality of pixel units. Each of the plurality of pixel units includes a plurality of sub-pixels, each of the plurality of sub-pixels is divided into at least two target sub-pixels, and a separation region is provided between two adjacent target sub-pixels. | 2020-12-24 |
20200403043 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate, a display panel, and a display device. The array substrate includes a substrate; a first electrode layer formed on the substrate; a light emitting layer formed on the first electrode layer and including a first light emitting area and a second light emitting area, the first light emitting area including a plurality of first light emitting blocks, the second light emitting area including a plurality of second light emitting blocks, and the first light emitting blocks and the second light emitting blocks formed by the same process; and a second electrode layer formed on the light emitting layer; where the first electrode layer includes a plurality of first electrodes corresponding to the first light emitting area, each of the first electrodes corresponds to a plurality of the first light emitting blocks, the first light emitting blocks on the same first electrode have the same color, and the first light emitting area is a transparent area, and the second light emitting area is a non-transparent area. | 2020-12-24 |
20200403044 | DISPLAY PANEL - A display panel includes a pixel arrangement structure. The pixel arrangement structure includes a plurality of first pixel rows and a plurality of second pixel rows arranged alternately. Each of the first pixel rows comprises a plurality of first pixels arranged at intervals, and each of the second pixel rows comprises a plurality of second pixels and a plurality of third pixels arranged alternately and at intervals. A shape of the first pixel comprises a shape formed by an arc. Each of the second pixel and the third pixel comprises a plurality of concave arcs and a plurality of convex arcs, the plurality of concave arcs and the plurality of convex arcs of the second pixel are alternately connected and form a closed figure, and the plurality of concave arcs and the plurality of convex arcs of the third pixel are alternately connected and form a closed figure. | 2020-12-24 |
20200403045 | Display Panel and Display Device - Provided are a display panel and a display device. After deposition of a thin-film transistor layer and a display layer in which emitting devices are disposed, a sensing layer including a piezoelectric material is disposed under the thin-film transistor layer to facilitate implementation of a display panel having built-in piezoelectric devices. Further, as thin-film transistors for ultrasonic sensing and thin-film transistors for display driving are disposed in different layers, a display panel capable of ultrasonic sensing in an active area may be provided without affecting a display resolution or implementation of display pixels. | 2020-12-24 |
20200403046 | ORGANIC LIGHT EMITTING DIODE DISPLAY MODULE, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE - Organic light emitting diode display module includes a substrate, a flat layer formed on the substrate, an anode layer formed on the flat layer and within the second through hole, a pixel definition layer formed on the flat layer and the anode layer, a light-emitting layer and a cathode layer formed within third layer through hole and on anode layer. A lead and a power cable are formed on the substrate. The cathode layer is formed on the pixel definition layer, light-emitting layer and lead. The cathode layer includes wire blocks arranged at intervals. The wire blocks includes a bent conductive wire, and both ends of the conductive wire are coupled to the lead and the power cable respectively. The present disclosure also discloses a manufacturing method of the display module and an electronic device. | 2020-12-24 |
20200403047 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display apparatus includes: a substrate including a display area in which thin film transistors and display devices electrically connected to the thin film transistors are arranged and a first non-display area outside the display area; a through portion vertically penetrating the substrate; a second non-display area between the through portion and the display area; and an encapsulation layer on the display devices and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially stacked. The first inorganic encapsulation layer and the second inorganic encapsulation layer extend to the through portion and directly contact each other in the second non-display area, and the first inorganic encapsulation layer directly contacts another inorganic layer thereunder in the second non-display area. | 2020-12-24 |
20200403048 | TRANSPARENT OLED SUBSTRATE, DISPLAY PANEL AND OLED SUBSTRATE - The present disclosure provides a transparent OLED substrate, a display panel, and an OLED substrate. The transparent OLED substrate includes: a base substrate; a first electrode layer formed over the base substrate; a pixel defining layer formed over the first electrode layer, the pixel defining layer including a plurality of pixel defining holes penetrating the pixel defining layer to the first electrode layer, and an exposed area of the first electrode layer is equal to an area of the pixel defining hole; a light emitting layer formed over the pixel defining layer and including organic light emitting blocks; a second electrode layer formed over the light emitting layer; wherein each of the pixel defining holes corresponds to a plurality of the organic light emitting blocks. | 2020-12-24 |
20200403049 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer which covers the semiconductor layer, a first conductive layer disposed on the first insulating layer, a second insulating layer which covers the first conductive layer, a second conductive layer disposed on the second insulating layer, a third insulating layer which covers the second conductive layer, a third conductive layer disposed on the third insulating layer, a first organic layer which covers the third conductive layer, and a fourth conductive layer disposed on the first organic layer, where the fourth conductive layer includes a lower layer, a middle layer, and an upper layer, and the lower layer is disposed between the first organic layer and the middle layer, and includes a transparent conductive oxidization film. | 2020-12-24 |
20200403050 | DISPLAY PANEL - A display panel includes: a substrate including a first area, a second area, and a third area; a stacked structure corresponding to a plurality of display elements in the second area, the stacked structure including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a plurality of grooves in the third area, wherein the stacked structure includes at least one organic material layer that is disconnected by the plurality of grooves, at least one groove of the plurality of grooves is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers. | 2020-12-24 |
20200403051 | Display Panel and Organic Light-Emitting Diode Display Device Using the Same - A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines. | 2020-12-24 |
20200403052 | DISPLAY APPARATUS - A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor. | 2020-12-24 |
20200403053 | DISPLAY APPARATUS - A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor. | 2020-12-24 |
20200403054 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device including a lower substrate having a display area and a pad area, a display structure disposed in the display area of the lower substrate, an upper substrate disposed on the display structure in the display area, and facing the lower substrate, pad electrodes disposed in the pad area of the lower substrate and spaced apart from each other in a first direction parallel to a top surface of the lower substrate, a conductive film member including conductive balls disposed on the pad electrodes and having a first area overlapping the pad electrodes and a second area not overlapping the pad electrodes, and a film package disposed on the conductive film member and including bump electrodes overlapping the first area of the conductive film member, in which the shape of the conductive balls disposed in the first area is different from those disposed in the second area. | 2020-12-24 |
20200403055 | ELECTRONIC DEVICE INCLUDING DISPLAY HAVING IRREGULAR PATTERN FORMED THEREON - An electronic device according to certain embodiments, comprises a sensor module configured to emit or detect light; and a display disposed above the sensor module, the display comprising a first area corresponding to a location of the sensor module and a second area which is a remaining area other than the first area, wherein the display comprises: a pixel layer comprising pixels; an electrode layer disposed beneath the pixel layer, the electrode layer comprising electrodes electrically connected to the pixels; conductive patterns electrically connected to the pixels and the electrodes; and nonconductive patterns between the pixels, wherein the conductive patterns are spaced apart from each other, at different intervals in the first area, and wherein the nonconductive patterns are spaced apart from each other, at different intervals in the first area. | 2020-12-24 |
20200403056 | DISPLAY APPARATUS - A display apparatus includes: a substrate comprising a display area and a non-display area; and a pad on the non-display area, wherein the pad comprises: a first conductive layer comprising, in a plan view, a plurality of bent portions and a plurality of connection portions connecting the plurality of bent portions with each other, the connection portions alternately extending in a first direction and a second direction opposite to the first direction; a second conductive layer on the first conductive layer and overlapping at least part of the first conductive layer; and a third conductive layer on the second conductive layer and overlapping the second conductive layer. | 2020-12-24 |
20200403057 | DISPLAY PANEL - A display panel including a substrate having a first area, a display area, and an intermediate area between the first area and the display area; a plurality of data lines extending in a first direction in the display area; and a data distributor including switches electrically connected to the plurality of data lines. The plurality of data lines include a first data line and a second data line, and each of the first data line and the second data line bypasses an edge of the first area in the intermediate area, and a bypass portion of the first data line and a bypass portion of the second data line overlap each other in the intermediate area. | 2020-12-24 |
20200403058 | DISPLAY DEVICE - A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines. | 2020-12-24 |
20200403059 | DISPLAY APPARATUS - A display apparatus includes a substrate, a driving thin-film transistor arranged on the substrate and including a driving semiconductor layer and a driving gate electrode, a first scanning line arranged on the first substrate and which extends in a first direction, a data line which extends in a second direction that intersects with the first direction, a node connection line arranged in the same layer as the first scanning line, and a shielding conductive layer arranged between the data line and the node connection line and disposed in the same layer as the driving gate electrode, where an end of the node connection line is connected to the driving gate electrode through a first node contact hole. | 2020-12-24 |
20200403060 | PIXEL DEFINING STRUCTURE, DISPLAY PANEL, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE - This disclosure relates to a pixel defining structure, a display panel, a method of manufacturing the same, and a display device. The pixel defining structure includes: a first pixel defining layer with a first opening, located on a substrate, wherein the first pixel defining layer includes a first portion formed by a first hydrophilic-hydrophobic material and a second portion formed by a second hydrophilic-hydrophobic material, projections of the first portion and the second portion on a surface of the substrate are substantially not overlapped, a side surface of the first pixel defining layer facing the first opening includes a first side surface formed by the first hydrophilic-hydrophobic material and a second side surface formed by the second hydrophilic-hydrophobic material, and the first hydrophilic-hydrophobic material has a different hydrophilicity and hydrophobicity from that of the second hydrophilic-hydrophobic material. | 2020-12-24 |
20200403061 | METHOD AND STRUCTURE FOR DUAL SHEET RESISTANCE TRIMMABLE THIN FILM RESISTORS - In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer. | 2020-12-24 |
20200403062 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion. | 2020-12-24 |
20200403063 | CAPACITOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided. | 2020-12-24 |
20200403064 | Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof - Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same. | 2020-12-24 |
20200403065 | VERTICAL FET WITH ASYMMETRIC THRESHOLD VOLTAGE AND CHANNEL THICKNESSES - An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm. | 2020-12-24 |
20200403066 | SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, first base regions of the second conductivity type, second base regions of the second conductivity type, gate insulating films, gate electrodes, a first electrode, a second electrode, and trenches. Between the trenches, the first base regions are in contact with the second semiconductor layer. The second base regions are provided at positions facing the trenches in a depth direction, respectively, and have a first surface facing the second electrode and a second surface facing the first electrode, where a curvature of the first surface is smaller than a curvature of the second surface. | 2020-12-24 |
20200403067 | TRANSITION-METAL OXIDES-COATED HYDROGEN-TERMINATED DIAMOND SURFACE AND USES THEREOF - The present invention provides a conducting material comprising a carbon-based material selected from a diamond or an insulating diamond-like carbon, having a hydrogen-terminated surface and a layer of tungsten trioxide, rhenium trioxide, or chromium oxide coating said hydrogen-terminated surface. Such conducting materials are useful in the fabrication of electronic components, electrodes, sensors, diodes, field effect transistors, and field emission electron sources. | 2020-12-24 |
20200403068 | A METHOD OF MAKING A GRAPHENE TRANSISTOR AND DEVICES - A chemically-doped graphene transistor comprising a plurality of graphene layers and having a first doped region separated from a second doped region by a third doped region, wherein the first and second doped regions are of an opposite doping type to the third doped region, and wherein each of the first, second and third doped regions each comprise a separate electrical contact. | 2020-12-24 |
20200403069 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10 | 2020-12-24 |
20200403070 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode. | 2020-12-24 |
20200403071 | METHOD FOR TESTING A HIGH VOLTAGE TRANSISTOR WITH A FIELD PLATE - In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain. | 2020-12-24 |
20200403072 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other. | 2020-12-24 |
20200403073 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device, in a memory cell of a split-gate type MONOS memory formed on a fin, a drain region is formed in an epitaxial layer on the fin, and a source region is formed in the fin, and a silicide layer is formed on an upper surface of the fin in which the source region is formed. | 2020-12-24 |
20200403074 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body. | 2020-12-24 |
20200403075 | FABRICATION OF GATE ALL AROUND DEVICE - A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer. | 2020-12-24 |
20200403076 | THIN FILM TRANSISTORS WITH OFFSET SOURCE AND DRAIN STRUCTURES AND PROCESS FOR FORMING SUCH - A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel. | 2020-12-24 |
20200403077 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure. | 2020-12-24 |
20200403078 | Gate Structure and Patterning Method for Multiple Threshold Voltages - A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another. | 2020-12-24 |
20200403079 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate. | 2020-12-24 |
20200403080 | Memory Cells and Integrated Structures - A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO | 2020-12-24 |
20200403081 | RECESSED GATE OXIDE ON THE SIDEWALL OF GATE TRENCH - Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below). | 2020-12-24 |
20200403082 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon. | 2020-12-24 |
20200403083 | SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF - A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure. | 2020-12-24 |
20200403084 | FinFET with Dummy Fins and Methods of Making the Same - A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer. | 2020-12-24 |
20200403085 | Gate Spacer Structure of FinFET Device - A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess. | 2020-12-24 |
20200403086 | FIN STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR HAVING TWO-DIMENSIONAL SHAPE IN PLAN VIEW - A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure. | 2020-12-24 |
20200403087 | VERTICAL FIELD EFFECT TRANSISTOR DEVICE HAVING PROTRUDED SHALLOW TRENCH ISOLATION AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures. | 2020-12-24 |
20200403088 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base. | 2020-12-24 |
20200403089 | SEMICONDUCTOR DEVICE - A semiconductor device includes a collector layer of a first conductive type, a drift layer of a second conductive type, an accumulation region of the second conductive type, a base region of the first conductive type, emitter regions of the second conductive type, a first gate electrode in contact with the emitter regions via first gate insulating film, a second gate electrode facing the first gate electrode via the base region, and being in contact with the emitter regions via second gate insulating film, a first resistive section electrically connected to the first gate electrode, a second resistive section having a larger resistance than does the first resistive section, and electrically connected to the second gate electrode, and a gate electrode pad electrically connected to the first and second resistive sections. | 2020-12-24 |
20200403090 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias. | 2020-12-24 |
20200403091 | GATE-SINKING PHEMTS HAVING EXTREMELY UNIFORM PINCH-OFF/THRESHOLD VOLTAGE - A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer. | 2020-12-24 |
20200403092 | GATE STACK DESIGN FOR GAN E-MODE TRANSISTOR PERFORMANCE - A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high-performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer. | 2020-12-24 |
20200403093 | APPARATUS AND METHOD OF MODULATING THRESHOLD VOLTAGE FOR FIN FIELD EFFECT TRANSISTOR (FINFET) AND NANOSHEET FET - Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC. | 2020-12-24 |
20200403094 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a gate stack, an air spacer, a first spacer, a second spacer, a sacrificial layer, and a contact plug. The gate stack is on the semiconductor substrate. The air spacer is around the gate stack. The first spacer is around the air spacer. The second spacer is on the air spacer and the first spacer. The sacrificial layer is on the gate stack, and an etching selectivity between the second spacer and the sacrificial layer is in a range from about 10 to about 30. The contact plug lands on the second spacer and the gate stack. | 2020-12-24 |
20200403095 | MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer. | 2020-12-24 |
20200403096 | INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface. | 2020-12-24 |
20200403097 | METHOD OF FORMING ISOLATION DIELECTRICS FOR STACKED FIELD EFFECT TRANSISTORS (FETS) - A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer. | 2020-12-24 |
20200403098 | STRAINED STRUCTURE OF A SEMICONDUCTOR DEVICE - A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D. | 2020-12-24 |
20200403099 | TRANSISTORS WITH UNIFORM SOURCE/DRAIN EPITAXY - A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed. | 2020-12-24 |
20200403100 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets. | 2020-12-24 |
20200403101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with high on-state current is provided. | 2020-12-24 |