52nd week of 2019 patent applcation highlights part 56 |
Patent application number | Title | Published |
20190393164 | PACKAGE SUBSTRATES HAVING AN ELECTROMAGNETIC BANDGAP STRUCTURE AND SEMICONDUCTOR PACKAGES EMPLOYING THE PACKAGE SUBSTRATES - A package substrate includes a core layer including a first surface and a second surface, which are opposite to each other. The package substrate also includes a power plane interconnection layer disposed on the first surface of the core layer and a ground plane interconnection layer disposed on the second surface of the core layer. The package substrate additionally includes an electromagnetic (EM) bandgap structure disposed in the core layer and electrically coupled between the power plane interconnection layer and the ground plane interconnection layer. The EM bandgap structure includes an EM bandgap via protruding from a portion of the power plane interconnection layer toward the ground plane interconnection layer. The EM bandgap structure further includes an EM bandgap cylindrical structure extending from a portion of the ground plane interconnection layer toward the power plane interconnection layer and surrounding a side surface of the EM bandgap via. | 2019-12-26 |
20190393165 | ULTRA-LOW PROFILE PACKAGE SHIELDING TECHNIQUE USING MAGNETIC AND CONDUCTIVE LAYERS FOR INTEGRATED SWITCHING VOLTAGE REGULATOR - Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield. | 2019-12-26 |
20190393166 | RADIO-FREQUENCY MODULE - A radio-frequency module having high design flexibility of a shield with less likelihood of variation in shielding characteristics is provided. A radio-frequency module includes a multilayer circuit board, a component mounted on a top surface of the multilayer circuit board, and a plurality of metal pins having a bent shape such that both end portions can be connected to the top surface of the multilayer circuit board. Each of the plurality of metal pins is provided upright on the top surface of the multilayer circuit board in a state where both end portions are connected to the top surface of the multilayer circuit board, and is arranged near the component to make up a shield member. | 2019-12-26 |
20190393167 | APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE - Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell. | 2019-12-26 |
20190393168 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad. | 2019-12-26 |
20190393169 | SEMICONDUCTOR DEVICE - The semiconductor device SD | 2019-12-26 |
20190393170 | GUARD RING STRUCTURE FOR AN INTEGRATED CIRCUIT - A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed. | 2019-12-26 |
20190393171 | SEMICONDUCTOR STRUCTURE HAVING MULTIPLE DIELECTRIC WAVEGUIDE CHANNELS AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first dielectric waveguide, a second dielectric waveguide, a first inter-level dielectric (ILD) material, a first transmitter coupling structure and a second transmitter coupling structure. The first and second dielectric waveguides are disposed one over the other. The first dielectric waveguide is configured to guide a first electromagnetic signal. The second dielectric waveguide is configured to guide a second electromagnetic signal. The first and second electromagnetic signals have different frequencies. The first ILD material is disposed between the first and second dielectric waveguides. The first transmitter coupling structure is configured to couple a first driver signal generated by a transmitter die to the first dielectric waveguide, and accordingly produce the first electromagnetic signal. The second transmitter coupling structure is configured to couple a second driver signal generated by the transmitter die to the second dielectric waveguide, and accordingly produce the second electromagnetic signal. | 2019-12-26 |
20190393172 | RFIC HAVING COAXIAL INTERCONNECT AND MOLDED LAYER - Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package. | 2019-12-26 |
20190393173 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SAME - Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder. | 2019-12-26 |
20190393174 | ELECTRONIC DEVICE COMPRISING A DISCRETE TRANSISTOR ASSEMBLED ON A PRINTED CIRCUIT BOARD - An electronic device including: a discrete transistor including a semiconductor chip encapsulated in a package made of an insulating material leaving access to a first pad of connection to a first conduction terminal of the transistor; and a printed circuit board ( | 2019-12-26 |
20190393175 | DISCRETE ELECTRONIC COMPONENT COMPRISING A TRANSISTOR - The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board. | 2019-12-26 |
20190393176 | METHODS FOR ENHANCING ADHESION OF THREE-DIMENIONAL STRUCTURES TO SUBSTRATES, AND RELATED ASSEMBLIES AND SYSTEMS - Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed. | 2019-12-26 |
20190393177 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. | 2019-12-26 |
20190393178 | SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES - An electroless nickel, electroless palladium, electroless tin stack and. associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process. | 2019-12-26 |
20190393179 | PRE-CONDUCTIVE ARRAY DISPOSED ON TARGET CIRCUIT SUBSTRATE AND CONDUCTIVE STRUCTURE ARRAY THEREOF - A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array. | 2019-12-26 |
20190393180 | HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE - Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. | 2019-12-26 |
20190393181 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: applying a bonding resin composition on a semiconductor chip supporting member, the bonding resin composition containing a thermosetting resin and silver microparticles having an average particle size of 10 to 200 nm, the silver microparticles having a protective layer made of an organic compound on surfaces thereof; a semi-sintering step of heating the applied bonding resin composition at a temperature that is lower than a reaction starting temperature of the thermosetting resin and is equal to or more than 50° C. to bring the silver microparticles into a semi-sintered state; and a bonding step including: placing a semiconductor chip on the bonding resin composition containing the silver microparticles in a semi-sintered state, heating at a temperature higher than the reaction starting temperature of the thermosetting resin in a pressure-free state, and bonding the semiconductor chip to the semiconductor chip supporting member. | 2019-12-26 |
20190393182 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer. | 2019-12-26 |
20190393183 | PACKAGE ARCHITECTURE WITH IMPROVED VIA DRILL PROCESS AND METHOD FOR FORMING SUCH PACKAGE - Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties. | 2019-12-26 |
20190393184 | POWER MODULE AND POWER CONVERSION APPARATUS - A semiconductor element, a substrate on which the semiconductor element is mounted, a connecting portion formed constituted by an arrangement of a plurality of wirings, a casing in which the substrate is disposed on a side of a bottom surface thereof and the semiconductor element and the connecting portion are accommodated therein, and an insulating sealing material filled in the casing, are provided. The plurality of wirings constituting the connecting portion are aligned in a loop shape in a same direction, and each height thereof is arranged such that each of the wiring has a height which is gradually increased one after another toward one direction in the arrangement. | 2019-12-26 |
20190393185 | BONDER - A bonder includes a first chuck unit | 2019-12-26 |
20190393186 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5. | 2019-12-26 |
20190393187 | METHOD FOR PRODUCING AN ELECTRIC CIRCUIT - The invention relates to a method ( | 2019-12-26 |
20190393188 | METALLIC SINTERED BONDING BODY AND DIE BONDING METHOD - A metal sintered bonding body bonds a substrate and a die. In the metal sintered bonding body, at least a center part and corner part of a rectangular region where the metal sintered bonding body faces the die have a low-porosity region whose porosity is lower than an average porosity of the rectangular region. The low-porosity region is located within a strip-shaped region whose central lines are diagonal lines of the rectangular region. | 2019-12-26 |
20190393189 | Semiconductor Device and Method - In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap. | 2019-12-26 |
20190393190 | Systems and methods for releveled bump planes for chiplets - An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization. | 2019-12-26 |
20190393191 | PACKAGES OF STACKING INTEGRATED CIRCUITS - Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed. | 2019-12-26 |
20190393192 | THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES USING JUMPING DROPS VAPOR CHAMBERS - An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another. | 2019-12-26 |
20190393193 | THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES USING JUMPING DROPS VAPOR CHAMBERS - An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another. | 2019-12-26 |
20190393194 | 3DIC STRUCTURE WITH PROTECTIVE STRUCTURE AND METHOD OF FABRICATING THE SAME AND PACKAGE - Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure. | 2019-12-26 |
20190393195 | Device and Method for UBM/RDL Routing - An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad. | 2019-12-26 |
20190393196 | VERTICALLY STACKED MULTICHIP MODULES - In a general aspect, a method for producing a circuit assembly can include coupling a first side of a first semiconductor die with a first side of a first substrate and a first side of a second substrate, the first substrate having a first electrically isolated metal layer disposed on a second side. The method can also include coupling a first side of a second semiconductor die with a second side of the second substrate and a first side of a third substrate, the third substrate having a second electrically isolated metal layer disposed on a second side. The method can further include coupling at least one conductive connector between the second substrate and the third substrate, the at least one conductive connector electrically coupling the second substrate with the third substrate. | 2019-12-26 |
20190393197 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein. | 2019-12-26 |
20190393198 | METHOD OF MANUFACTURING DISPLAY DEVICE - A method of manufacturing a display apparatus according to an exemplary embodiment includes the steps of forming a plurality of light emitting diode chips on a first manufacturing substrate, coupling the plurality of the light emitting diode chips onto a second manufacturing substrate, separating the first manufacturing substrate from the plurality of the light emitting diode chips, and transferring the plurality of light emitting diode chips coupled onto the second manufacturing substrate to a substrate including first and second substrate electrodes. | 2019-12-26 |
20190393199 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a plurality of light emitting elements disposed in a light-emitting region on the substrate, at least one first wiring part surrounding the light-emitting region, at least one second wiring part, together with the at least one first wiring part, demarcating the light-emitting region into a plurality of demarcated regions, a first wall formed along and covering the at least one first wiring part to surround the light-emitting region, at least one second wall formed along and covering corresponding one or more of the at least one second wiring part, and a light-transmissive member containing a wavelength converting material, covering an entire light-emitting region. | 2019-12-26 |
20190393200 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball. | 2019-12-26 |
20190393201 | DEVICE AND METHODS FOR THE TRANSFER OF CHIPS FROM A SOURCE SUBSTRATE ONTO A DESTINATION SUBSTRATE - A device for the transfer of chips from a source substrate onto a destination substrate, including: a source substrate having a lower surface and an upper surface; and a plurality of elementary chips arranged on the upper surface of the source substrate, wherein each elementary chip is suspended above the source substrate by at least one breakable mechanical fastener, said at least one breakable mechanical fastener having a lower surface fastened to the upper surface of the source substrate and an upper surface fastened to the lower surface of the chip. | 2019-12-26 |
20190393202 | DISPLAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure provides display substrate and a fabrication method thereof, a display panel and a display device. The display substrate has a plurality of pixel regions, and includes an anode, a light-emitting layer and a cathode in each pixel region. In each pixel region, the light-emitting layer includes a plurality of light-emitting units spaced apart from each other, both the anode and the cathode are conductive layers each having an integral structure, and the plurality of light-emitting units are connected to the anode and the cathode, respectively. | 2019-12-26 |
20190393203 | HIGH-FREQUENCY MODULE - A high-frequency module includes a mounting substrate, electronic components, a sealing resin, and land conductors. The mounting substrate includes a front surface, a rear surface, and a side surface. The land conductors are provided on the rear surface. The electronic components are mounted on the front surface of the mounting substrate. A distance between the mounting surface of the land conductor near the side surface and the rear surface of the mounting substrate is larger than a distance between the mounting surface of the land conductor closer to the center than the land conductor near the side surface and the rear surface of the mounting substrate. | 2019-12-26 |
20190393204 | Eliminating defects in stacks - Representative implementations of devices and techniques eliminate defects in die-to-die, die-to-wafer, and wafer-to-wafer stacks. In various implementations, the devices and techniques herein disclosed geographically isolate and eliminate one or more regions in a stack that is affected by one or more defects in the stack. Die/wafer stack devices are architected to have redundancy across vertical die columns in control, signaling, and in power supplies. | 2019-12-26 |
20190393205 | INTEGRATED CIRCUIT INCLUDING MULTI-HEIGHT STANDARD CELL AND METHOD OF DESIGNING THE SAME - An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line. | 2019-12-26 |
20190393206 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction. | 2019-12-26 |
20190393207 | ROUTING FOR THREE-DIMENSIONAL INTEGRATED STRUCTURES - A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components. | 2019-12-26 |
20190393208 | SEMICONDUCTOR STRUCTURES - A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type. | 2019-12-26 |
20190393209 | ELECTROSTATIC DISCHARGE DEVICES WITH REDUCED CAPACITANCE - The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region. | 2019-12-26 |
20190393210 | IMPLANTS TO ENLARGE SCHOTTKY DIODE CROSS-SECTIONAL AREA FOR LATERAL CURRENT CONDUCTION - A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction. | 2019-12-26 |
20190393211 | IMPLANTED SUBSTRATE CONTACT FOR IN-PROCESS CHARGING CONTROL - A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode. | 2019-12-26 |
20190393212 | METAL RESISTORS INTEGRATED INTO POLY-OPEN-CHEMICAL-MECHANICAL-POLISHING (POC) MODULE AND METHOD OF PRODUCTION THEREOF - A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures. | 2019-12-26 |
20190393213 | THREE-DIMENSIONAL CIRCUIT STRUCTURE - A three-dimensional (3D) circuit structure includes a 3D insulating substrate having at least one circuit forming zone and at least one exposed contact forming zone; at least one circuit pattern portion provided on the 3D insulating substrate and having at least one circuit trace layout layer located in the circuit forming zone and at least one exposed contact located in the exposed contact forming zone and connected to the circuit trace layout layer; and an insulating encapsulation member covering at least the circuit forming zone and the circuit trace layout layer. With the insulating encapsulation member, the circuit trace layout layer is waterproof, dustproof, scratch-resistant, peeling-proof, secure for use, and compliant with safety codes of electrical insulation, enabling the 3D circuit structure in use to have stable electrical characteristics. | 2019-12-26 |
20190393214 | ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES - Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed. | 2019-12-26 |
20190393215 | METHOD FOR MANUFACTURING MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS - A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD. | 2019-12-26 |
20190393216 | Integrated Circuit Packages and Methods of Forming Same - An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening. | 2019-12-26 |
20190393217 | PACKAGE-EMBEDDED THIN-FILM CAPACITORS, PACKAGE-INTEGRAL MAGNETIC INDUCTORS, AND METHODS OF ASSEMBLING SAME - Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate. | 2019-12-26 |
20190393218 | BIDIRECTIONAL SWITCH HAVING BACK TO BACK FIELD EFFECT TRANSISTORS - A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET. | 2019-12-26 |
20190393219 | Semiconductor Structures and Methods of Forming the Same - Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region. | 2019-12-26 |
20190393220 | FINFETS HAVING ELECTRICALLY INSULATING DIFFUSION BREAK REGIONS THEREIN AND METHODS OF FORMING SAME - A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer. A level of a lower surface of the third portion is higher than a level of a lower end of each of the first portion and the second portion and is lower than a level of an upper surface of the first gate structure. | 2019-12-26 |
20190393221 | CUT INSIDE REPLACEMENT METAL GATE TRENCH TO MITIGATE N-P PROXIMITY EFFECT - The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut. | 2019-12-26 |
20190393222 | 4F2 DRAM CELL USING VERTICAL THIN FILM TRANSISTOR - Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region. | 2019-12-26 |
20190393223 | VERTICAL SHARED GATE THIN-FILM TRANSISTOR-BASED CHARGE STORAGE MEMORY - A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit. | 2019-12-26 |
20190393224 | EMBEDDED MEMORY EMPLOYING SELF-ALIGNED TOP-GATED THIN FILM TRANSISTORS - Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint. | 2019-12-26 |
20190393225 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench. | 2019-12-26 |
20190393226 | DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURING, WRITING AND READING THE SAME - A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line. | 2019-12-26 |
20190393227 | Integrated Arrangements of Pull-Up Transistors and Pull-Down Transistors, and Integrated Static Memory - Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level. | 2019-12-26 |
20190393228 | SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS - A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided. | 2019-12-26 |
20190393229 | TRENCH GATE HIGH VOLTAGE TRANSISTOR FOR EMBEDDED MEMORY - Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved. | 2019-12-26 |
20190393230 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function. | 2019-12-26 |
20190393231 | FUSE-ARRAY ELEMENT - A device includes a fuse-array mat including a plurality of fuse-array elements. Each fuse-array element includes a fuse comprising a fuse line having less than or equal to 50% of a dimension of the fuse line disposed over an active area of the fuse-array element, wherein the fuse is configured to be activated to indicate a fuse state of the fuse of two possible fuse states of the fuse. Additionally, each fuse-array element includes an access device comprising a gate line having more than 50% of a dimension of the gate line disposed over the active area of the fuse-array element. | 2019-12-26 |
20190393232 | MEMORY DEVICES BASED ON CAPACITORS WITH BUILT-IN ELECTRIC FIELD - Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed. | 2019-12-26 |
20190393233 | PORT CONTROL - A locator of a surgical port of a surgical robot system, the surgical robot system comprising an instrument attached to a robot arm, the instrument having an instrument shaft able to pass through the surgical port to a surgical site, the locator comprising: an interface configured to couple to the surgical port; a mechanism configured to permit relative linear and/or rotational motion of the interface and the instrument shaft; and a controller comprising a processor operable to estimate the position of a part of the robot arm, the controller configured to control the mechanism in dependence on the estimated position of the part of the robot arm such that as the robot arm retracts the instrument from the patient, the locator moves the port away from the robot arm and provides a reaction force to keep the port in place. | 2019-12-26 |
20190393234 | METHOD TO IMPROVE FILL-IN WINDOW FOR EMBEDDED MEMORY - Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved. | 2019-12-26 |
20190393235 | MASK DESIGN FOR EMBEDDED MEMORY - Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region. | 2019-12-26 |
20190393236 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first member spreading along a first direction and a second direction, a stacked body provided on a third-direction side when viewed from the first member, and a second member provided inside the first member and exposed at a surface of the first member on the third-direction side. A configuration of an end portion in the first direction of the stacked body is a staircase configuration having terraces formed every conductive film. The second member is made from a material different from a material of the first member. The second member is totally disposed in a region opposing a total length of an end edge of the stacked body on the first-direction side, and not disposed in an outer region of the stacked body on the second-direction side. | 2019-12-26 |
20190393237 | VERTICALLY-INTEGRATED 3-DIMENSIONAL FLASH MEMORY FOR HIGH RELIABLE FLASH MEMORY AND FABRICATION METHOD THEREOF - Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer. | 2019-12-26 |
20190393238 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure. | 2019-12-26 |
20190393239 | VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern. | 2019-12-26 |
20190393240 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE INCLUDING A PENETRATION REGION PASSING THROUGH A GATE ELECTRODE - A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region. | 2019-12-26 |
20190393241 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance. | 2019-12-26 |
20190393242 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials. | 2019-12-26 |
20190393243 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING VERTICAL STRUCTURES WITH VARIED SPACING - A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column. | 2019-12-26 |
20190393244 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE - An array substrate and a manufacturing method thereof, a display panel and a driving method thereof, and a display device are provided in the present disclosure, in the field of displays. The array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel units defined by the gate lines and the data lines in cross arrangement. The plurality of pixel units are arranged in an array. Each of the pixel units includes a thin film transistor. Each row of pixel units are connected to one corresponding gate line. Each row of pixel units comprise a plurality of pixel unit groups. Each pixel unit group comprises two pixel units of adjacent columns that are connected to one data line. Thin film transistors of the two pixel units in the pixel unit group are transistors of different types. When the array substrate reduces the number of the date lines by a half, there is no need to design two gate lines for one row of pixel units. Thus the number of the gate lines is reduced, and an aperture opening ratio of the TFT-LCD increases. | 2019-12-26 |
20190393245 | Array Substrate, Electronic Paper Display Panel, Drive Method Thereof, and Display Device - In an array substrate, an electronic paper display panel and a drive method thereof, and a display device, a display area includes multiple sub-display areas. A plurality of scanning lines in each sub-display area are electrically insulated from each other, corresponding scanning lines in different sub-display areas are electrically connected to each other and display time of each sub-display area is controlled through control signal lines. When a control chip and a flexible circuit board are employed, only a small number of control chips and/or flexible circuit boards, or even only one control chip and/or one flexible circuit board, may drive multiple sub-display areas to display pictures. | 2019-12-26 |
20190393246 | DISPLAY PANEL - A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width. | 2019-12-26 |
20190393247 | DISPLAY PANEL AND DISPLAY DEVICE WITH SAME - A display panel includes: a first substrate including a display region and a wiring region disposed in the periphery of the display region, in which the wiring region has a fanout region; a second substrate arranged opposite to the first substrate; a transmission wiring circuit electrically coupled between a driving assembly and a plurality of signal lines; and an isolation layer disposed in a position of the second substrate relative to the position of the fanout region, in which an electrode layer is provided on the surface of the insulation layer, and the electrode layer is electrically coupled to a voltage line of a common electrode and the transmission wiring circuit to form a capacitor. | 2019-12-26 |
20190393248 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an SOI substrate having an active region and an element isolation region adjacent to the active region, and including a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer, a trench formed in the element isolation region, and penetrating the semiconductor layer and the insulating layer so as to reach the support substrate, an element isolation insulating film embedded in the trench, the element isolation insulating film being made of silicon oxide film, a gate electrode formed on the semiconductor layer in the active region via a gate insulating film, a sidewall film formed on both sides of the gate electrode in cross-section view, the sidewall film being comprised of a first film made of silicon oxide film, and a second film made of silicon nitride film. | 2019-12-26 |
20190393249 | STACKED THIN FILM TRANSISTORS - Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed. | 2019-12-26 |
20190393250 | DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR - A display panel includes a substrate and a plurality of thin film transistors arranged on the substrate in a matrix. The display panel further includes a photoresist layer and a shading layer, which are arranged between each of the thin film transistors and the substrate; each of the thin film transistors includes a conductive channel corresponding to the photoresist layer and the shading layer; the photoresist layer is more adjacent to the substrate than the shading layer; the shading layer is operated to reflect light transmitted from the substrate to prevent the light from being transmitted to the conductive channel; and the photoresist layer is operated to refract the light transmitted from the substrate and transmit the refracted light unidirectionally along a light outlet direction of the display panel. | 2019-12-26 |
20190393251 | ANTI-REFLECTIVE LAYERS IN SEMICONDUCTOR DEVICES - A Complementary Metal Oxide Semiconductor, CMOS, device for radiation detection. The CMOS device includes a semiconductor diffusion layer having a photodetector region for receiving incident light, and a polysilicon layer having a patterned structure in a region at least partially overlapping the photodetector region. The structure includes a plurality of features being perforations extending through the polysilicon layer or columns of polysilicon, wherein the perforations are filled with, or the columns are surrounded by, a dielectric material. | 2019-12-26 |
20190393252 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a photoelectric converter including a plurality of light receiving elements arranged along one direction in correspondence with each color of received light/each light receiving element generating an electric charge corresponding to an amount of received light, an electric charge storage unit including a plurality of capacitors storing the electric charges generated by the respective light receiving elements, and a signal processing unit configured to process each of the electric charges stored by the plurality of capacitors as a signal. The electric charge storage unit is disposed so as to oppose the signal processing unit across the photoelectric converter. | 2019-12-26 |
20190393253 | IMAGE SENSOR - An image sensor including a plurality of pixels, each pixel including a photogate detector coupled to a readout circuit via a first conductive transfer gate, wherein the photogate detector and the first transfer gate are formed inside and on top of a first semiconductor substrate, and the readout circuit is formed inside and on top of a second semiconductor substrate arranged on the first substrate, the sensor being intended to be illuminated on the side of the surface of the first substrate opposite to the second substrate. | 2019-12-26 |
20190393254 | ENCAPSULATION STRUCTURE FOR IMAGE SENSOR CHIP AND METHOD FOR MANUFACTURING THE SAME - An encapsulation structure to protect an image sensor chip at all times includes a printed circuit board, an image sensor chip, a protecting structure, and a package portion. The image sensor chip is mounted on the printed circuit board and the protecting structure is mounted on the image sensor chip. The protecting structure comprises a filter sheet. The package portion is entirely opaque and is formed on the printed circuit board, wrapping side wall of the printed circuit board, side wall of the protecting structure, and a portion of surface of the filter sheet which is away from the image sensor chip. | 2019-12-26 |
20190393255 | GLOBAL SHUTTER CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME - A global shutter CMOS image sensor includes a photodiode, a floating diffusion region, and a storage diode disposed in the upper portion of the substrate. The storage diode is disposed between the photodiode and the floating diffusion region. A first transfer gate is disposed on the substrate between the photodiode and the storage node. A second transfer gate is disposed on the substrate between the storage diode and the floating diffusion region. A first dielectric layer is disposed on the substrate and covers the first transfer gate and the second transfer gate. A light-shielding layer is disposed on the first dielectric layer. A light pipe is disposed through the light-shielding layer and a portion of the first dielectric layer, and is correspondingly disposed above the photodiode. The light pipe has a higher refractive index than the first dielectric layer. | 2019-12-26 |
20190393256 | PHOTODETECTOR AND FABRICATION METHOD, AND IMAGING SENSOR - Photodetectors and fabrication methods thereof and imaging sensors are provided. An exemplary photodetector includes a first substrate formed with pixel circuits and common electrode connection members and first wiring boards electrically connected to the corresponding pixel circuits; and a second substrate formed with pixel units and isolation wall members isolating pixel units. Each isolation wall member includes a conductive member and a sidewall; second wiring boards are formed on a front surface of the second substrate; the second wiring boards are electrically connected to first terminals of the pixel units; a transparent electrode layer is formed on a back surface of the second substrate; and a second terminal of each pixel unit is electrically connected to the transparent electrode layer. The second wiring boards are bonded and electrically connected to the first wiring boards and the transparent electrode layer is electrically connected to the common electrode connection members. | 2019-12-26 |
20190393257 | BACKSIDE ILLUMINATION IMAGE SENSORS - Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV. | 2019-12-26 |
20190393258 | ELECTRONIC DEVICE PACKAGE AND FABRICATING METHOD THEREOF - Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof. | 2019-12-26 |
20190393259 | IMAGING DEVICE - An imaging device includes: a first pixel and a second pixel that are arranged along a first direction and each include a photoelectric converter, a charge accumulator, a first transistor one of a source and a drain of which is connected to the charge accumulator, and a second transistor a gate of which is connected to the charge accumulator; a first line and a second line that each extend along the first direction; a first voltage supply circuit configured to generate a voltage between a first voltage turning on the first transistor of the first pixel and a second voltage turning off the first transistor of the first pixel; and a second voltage supply circuit configured to generate a voltage between a fourth voltage turning on the first transistor of the second pixel and a fifth voltage turning off the first transistor of the second pixel. | 2019-12-26 |
20190393260 | PIXEL HAVING TWO SEMICONDUCTOR LAYERS, IMAGE SENSOR INCLUDING THE PIXEL, AND IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR - An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially | 2019-12-26 |
20190393261 | IMAGING DEVICE AND ELECTRONIC APPARATUS - Provided is an imaging device including: a pixel region including a first photoelectric converter; an outside-pixel region including a second photoelectric converter coupled to a predetermined electric potential; and a circuit substrate having one surface on which the first photoelectric converter and the second photoelectric converter are provided, and including a peripheral circuit electrically coupled to the first photoelectric converter. | 2019-12-26 |
20190393262 | IMAGE SENSOR STRUCTURE - An image sensor structure includes a substrate, a first infrared filter, a second infrared filter, a planarization layer, a color filter and a third infrared filter. The substrate has a first sensing region for detecting visible light and a second sensing region neighboring the first sensing region for detecting infrared light. The first infrared filter is disposed on the first sensing region. The second infrared filter is disposed on the second sensing region and neighbors the first infrared filter. The second infrared filter defines one or more openings for penetrating incident light. The planarization layer is over the first infrared filter and the second infrared filter, and fills the one or more openings. The color filter is on the planarization layer and vertically above the first sensing region. The third infrared filter is on the planarization layer and is vertically above the second sensing region. | 2019-12-26 |
20190393263 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a first substrate. The semiconductor device also includes a first light-emitting diode on the first substrate. The semiconductor device further includes a first insulating layer on the first substrate and adjacent to the first light-emitting diode. In addition, the semiconductor device includes an adhesive structure on the first insulating layer. The adhesive structure includes a first side facing the first light-emitting diode and a second side opposite to the first side. The semiconductor device also includes a second substrate disposed on the adhesive structure. The semiconductor device further includes an optical structure in contact with at least one of the first side and the second side. | 2019-12-26 |