52nd week of 2018 patent applcation highlights part 67 |
Patent application number | Title | Published |
20180374918 | SEMICONDUCTOR DEVICE - A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H | 2018-12-27 |
20180374919 | Method of Manufacturing a Superjunction Semiconductor Device - In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic. | 2018-12-27 |
20180374920 | NANOCRYSTALS WITH HIGH EXTINCTION COEFFICIENTS AND METHODS OF MAKING AND USING SUCH NANOCRYSTALS - A population of bright and stable nanocrystals is provided. The nanocrystals include a semiconductor core and a thick semiconductor shell and can exhibit high extinction coefficients, high quantum yields, and limited or no detectable blinking. | 2018-12-27 |
20180374921 | Semiconductor Wafer - In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas. | 2018-12-27 |
20180374922 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer. | 2018-12-27 |
20180374923 | Semiconductor Structure and Manufacturing Method Thereof - A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer. | 2018-12-27 |
20180374924 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin. | 2018-12-27 |
20180374925 | TRENCH GATE STRUCTURE AND MANUFACTURING METHOD THEREFOR - A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate ( | 2018-12-27 |
20180374926 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor. | 2018-12-27 |
20180374927 | TRANSISTOR WITH DUAL-GATE SPACER - Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as | 2018-12-27 |
20180374928 | DIELECTRIC METAL OXIDE CAP FOR CHANNEL CONTAINING GERMANIUM - Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed. | 2018-12-27 |
20180374929 | FERROELECTRIC MEMORY DEVICES - A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer. | 2018-12-27 |
20180374930 | NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION - A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate. | 2018-12-27 |
20180374931 | SEMICONDUCTOR COMPONENT HAVING AN ESD PROTECTION DEVICE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode. | 2018-12-27 |
20180374932 | GATE TIE-DOWN ENABLEMENT WITH INNER SPACER - A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers. | 2018-12-27 |
20180374933 | FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR (VERTICAL FINFET) WITH A SELF-ALIGNED GATE AND FIN EDGES - A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D | 2018-12-27 |
20180374934 | METHOD FOR MAKING THIN FILM TRANSISTOR - A method of making thin film transistor including: forming a gate electrode, forming a gate insulating layer on the gate electrode; locating a semiconductor layer on the gate insulating layer; placing stripe-shaped masks on the semiconductor layer, wherein the thickness of the stripe-shaped masks is H, the spacing distance between the stripe-shaped masks is L; depositing a first conductive film layer along a first direction, the thickness of the first conductive film layer is D, a first angle between the first direction and a direction along the thickness of the stripe-shaped masks is θ | 2018-12-27 |
20180374935 | SELF-ALIGNED FINFET FORMATION - A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin. | 2018-12-27 |
20180374936 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH CONTACT OVER SOURCE/DRAIN STRUCTURE - Methods for manufacturing semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer by using an etching solvent. In addition, the etching solvent includes (a) a first component and (b) a second component. The first component includes an acid, and the second component includes propylene carbonate (PC), ethylene carbonate (EC), diethyl carbonate (DEC), or a combination thereof. | 2018-12-27 |
20180374937 | FIELD EFFECT TRANSISTORS HAVING A FIN - Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions. | 2018-12-27 |
20180374938 | SEMICONDUCTOR CIRCUIT USING POSITIVE FEEDBACK FIELD EFFECT TRANSISTOR FOR EMULATING NEURON FIRING PROCESS - Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET. | 2018-12-27 |
20180374939 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to the present invention has a super junction structure, and includes a low-resistance semiconductor layer, an n−-type column region, p−-type column regions, a base region, trenches, gate insulation films, gate electrodes, source regions, interlayer insulation films, contact holes, metal plugs, p+-type diffusion regions, a source electrode and a gate pad electrode. An active element part includes an n−-type column region between a predetermined p−-type column region disposed closest to a gate pad part and a predetermined n−-type column region disposed closest to the gate pad part among the n−-type column regions which are in contact with the trenches. The present invention provides a power semiconductor device which can satisfy a demand for reduction in cost and downsizing of electronic equipment, can lower ON resistance while maintaining a high withstand voltage, and can possess a large breakdown resistance. | 2018-12-27 |
20180374940 | SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION AND GRADED GATE DIELECTRIC - Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack. | 2018-12-27 |
20180374941 | Method of Controlling Wafer Bow in a Type III-V Semiconductor Device - A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer. | 2018-12-27 |
20180374942 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to third electrodes, and first to third semiconductor regions. The third electrode is separated from the second electrode in a first direction. The first semiconductor region includes a first partial region separated from the first electrode, a second partial region separated from the second electrode, and a third partial region separated from the third electrode. The second semiconductor region includes a fourth partial region positioned between the first electrode and the first partial region, a fifth partial region positioned between the second electrode and the second partial region, and a sixth partial region positioned between the third electrode and the third partial region. The third semiconductor region includes a seventh partial region positioned between the second electrode and the fifth partial region and an eighth partial region positioned between the third electrode and the sixth partial region. | 2018-12-27 |
20180374943 | SEMICONDUCTOR DEVICES HAVING A PLURALITY OF UNIT CELL TRANSISTORS THAT HAVE SMOOTHED TURN-ON BEHAVIOR AND IMPROVED LINEARITY - A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts. | 2018-12-27 |
20180374944 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS FOR FABRICATING THE SAME - A high electron mobility transistor (HEMT) and method of producing the same are provided. The HEMT includes a barrier layer formed on a GaN layer. The HEMT also includes a ZrO | 2018-12-27 |
20180374945 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer. | 2018-12-27 |
20180374946 | METHODS OF FORMING A BULK FIELD EFFECT TRANSISTOR (FET) WITH SUB-SOURCE/DRAIN ISOLATION LAYERS AND THE RESULTING STRUCTURES - Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage. | 2018-12-27 |
20180374947 | DIODE, SEMICONDUCTOR DEVICE, AND MOSFET - Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction. | 2018-12-27 |
20180374948 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a contact trench is provided. The semiconductor device including: a semiconductor substrate; a drift region of the first conductivity type provided on an upper surface side of the semiconductor substrate; a base region of the second conductivity type provided above the drift region; a source region of the first conductivity type provided above the base region; two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region; a contact trench provided in direct contact with the source region between adjacent trench portions; and a contact layer of the second conductivity type provided below the contact trench, is provided. A peak of a doping concentration of the contact layer is positioned shallower than a position of a lower end of the source region. | 2018-12-27 |
20180374949 | METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY - A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask. | 2018-12-27 |
20180374950 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first electrode in a semiconductor layer, an insulating film on the semiconductor layer, covering the first electrode, a first pad on the insulating film, a second pad on the first insulating film, spaced from the first pad, and a contact through the first insulating film and electrically connecting the second pad to the first electrode. The first electrode has a first portion below the first pad and a second portion below the second pad. The first portion has recessed shape on its upper surface. The second portion has an upper surface in which any difference in height between its central portion and its adjacent end portions is less than the difference in height between a central portion of the first portion and the adjacent end portions of the first portion. | 2018-12-27 |
20180374951 | CRYSTALLIZED SILICON CARBON REPLACEMENT MATERIAL FOR NMOS SOURCE/DRAIN REGIONS - Tensile strain is applied to a channel region of a transistor by depositing an amorphous Si | 2018-12-27 |
20180374952 | HEMT GaN DEVICE WITH A NON-UNIFORM LATERAL TWO DIMENSIONAL ELECTRON GAS PROFILE AND METHOD OF MANUFACTURING THE SAME - A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain, wherein a two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain, wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain, and wherein the 2DEG decreases in density in the drift region between the gate and the drain. | 2018-12-27 |
20180374953 | METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL - A metal oxide thin film transistor includes: a substrate; a metal oxide semiconductor layer disposed on the substrate, and including a semiconductor body layer, and a source electrode contact layer and a drain electrode contact layer located at both ends of the semiconductor body layer, respectively; a gate insulating layer disposed on the semiconductor body layer; a gate electrode disposed on the gate insulating layer; a first passivation layer disposed on the gate electrode, the source electrode contact layer and the drain electrode contact layer, and having a first via hole and a second via hole exposing the source electrode contact layer and the drain electrode contact layer respectively; and a source electrode and a drain electrode disposed on the first passivation layer, the source electrode and the drain electrode contacting the source electrode contact layer and the drain electrode contact layer through the first and second via hole, respectively. | 2018-12-27 |
20180374954 | THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME, DISPLAY SUBSTRATE, DISPLAY APPARATUS - The present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display apparatus, and belongs to the field of display technology. The method includes: forming a metal oxide semiconductor pattern comprising first and second metal oxide semiconductor layers, the second metal oxide semiconductor layer being above the first metal oxide semiconductor layer; depositing a source-drain metal layer on the metal oxide semiconductor pattern; etching the source-drain metal layer and the second metal oxide semiconductor layer to form source and drain electrodes and an active layer of the thin film transistor. The active layer is obtained after removing the second metal oxide semiconductor layer between the source and drain electrodes using a first etchant, and the first etchant has a higher etching rate on the second metal oxide semiconductor layer than on the first metal oxide semiconductor layer. | 2018-12-27 |
20180374955 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a circuit including a first TFT ( | 2018-12-27 |
20180374956 | THIN-FILM TRANSISTOR INCLUDING OXIDE SEMICONDUCTOR LAYER, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS INCLUDING THE SAME - A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25. | 2018-12-27 |
20180374957 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND DISPLAY MODULE - A semiconductor device including a transistor and a wiring electrically connected to the transistor each of which has excellent electrical characteristics because of specific structures thereover is provided. A first conductive film, a first insulating film over the first conductive film, a second conductive film over the first insulating film, a second insulating film over the second conductive film, a third conductive film electrically connected to the first conductive film through an opening provided in the first insulating film and the second insulating film, and a third insulating film over the third conductive film are provided. The third conductive film includes indium, tin, and oxygen, and the third insulating film includes silicon and nitrogen and the number of ammonia molecules released from the third insulating film is less than or equal to 1×10 | 2018-12-27 |
20180374958 | Semiconductor Device Including Wrap Around Contact and Method of Forming the Semiconductor Device - A semiconductor device includes a plurality of semiconductor layers formed on a plurality of fin structures, an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, a gate structure formed on the plurality of semiconductor layers, and a wrap around contact formed on the epitaxial layer. | 2018-12-27 |
20180374959 | OXIDE SEMICONDUCTOR COMPOUND, SEMICONDUCTOR ELEMENT PROVIDED WITH LAYER OF OXIDE SEMICONDUCTOR COMPOUND, AND LAMINATED BODY - An oxide semiconductor compound includes gallium; and oxygen. An optical band gap is 3.4 eV or more. An electron Hall mobility obtained by performing a Hall measurement at a temperature of 300 K is 3 cm | 2018-12-27 |
20180374960 | TFT SUBSTRATE AND METHOD FOR MAKING SAME - A high-performance TFT substrate ( | 2018-12-27 |
20180374961 | VERTICAL MEMORY DEVICE - A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes. | 2018-12-27 |
20180374962 | TWO-DIMENSIONAL ELECTROSTRICTIVE FIELD EFFECT TRANSISTOR (2D-EFET) - A device and method for manufacturing a two-dimensional electrostrictive field effect transistor having a substrate, a source, a drain, and a channel disposed between the source and the drain. The channel is a two-dimensional layered material and a gate proximate the channel. The gate has a column of an electrostrictive or piezoelectric or ferroelectric material, wherein an electrical input to the gate produces an elongation of the column that applies a force or mechanical stress on the channel and reduces a bandgap of two-dimensional material such that the two-dimensional electrostrictive field effect transistor operates with a subthreshold slope that is less than 60 mV/decade. | 2018-12-27 |
20180374963 | TRANSCAP DEVICE ARCHITECTURE WITH REDUCED CONTROL VOLTAGE AND IMPROVED QUALITY FACTOR - Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region. | 2018-12-27 |
20180374964 | SEMICONDUCTOR DEVICE, MOS CAPACITOR, AND MANUFACTURING METHODS THEREFOR - This application relates to the technical field of semiconductors, and discloses a semiconductor device, an MOS capacitor, and manufacturing methods therefor. Forms of a method for manufacturing the device may include: providing a substrate structure, including: a first fin and a second fin that are on the substrate and that are separated; a first pseudo gate structure on the first fin, including a first pseudo gate dielectric layer and a first pseudo gate thereon; a second pseudo gate structure on the second fin, including a second pseudo gate dielectric layer and a second pseudo gate thereon; and an interlayer dielectric layer around the first pseudo gate structure and the second pseudo gate structure, an upper surface of the interlayer dielectric layer is approximately flush with upper surfaces of the first pseudo gate and the second pseudo gate; removing a portion of the first pseudo gate to form a first recess, and removing the second pseudo gate structure to form a second recess, where an upper surface of a remaining portion of the first pseudo gate is higher than an upper surface of the first pseudo gate dielectric layer that is at a top portion of the first fin; and forming a first metal gate stack structure in the first recess, and forming a second metal gate stack structure in the second recess. | 2018-12-27 |
20180374965 | Novel DC Power Conversion Circuit - The inventive technology, in certain embodiments, may be generally described as a solar power generation system with a converter, which may potentially include two or more sub-converters, established intermediately of one or more strings of solar panels. Particular embodiments may involve sweet spot operation in order to achieve improvements in efficiency, and bucking of open circuit voltages by the converter in order that more panels may be placed on an individual string or substring, reducing the number of strings required for a given design, and achieving overall system and array manufacture savings. | 2018-12-27 |
20180374966 | Integrated Photovoltaic Panel Circuitry - A photovoltaic module is presented, which may include a photovoltaic panel and a converter circuit having a primary input connected to the photovoltaic panel and a secondary output galvanically isolated from the primary input. The primary input may be connectible to multiple input terminals within a junction box and at least one of the input terminals may be electrically connected to a ground. The photovoltaic module may include multiple interconnected photovoltaic cells connected electrically to multiple connectors (for example bus-bars). The photovoltaic module may include input terminals operable for connecting to the connectors and an isolated converter circuit. The isolated converter circuit may include a primary input connected to the input terminals and a secondary output galvanically isolated from the primary input. | 2018-12-27 |
20180374967 | MODE CONVERTER AND QUADRANT PHOTODIODE FOR SENSING OPTICAL CAVITY MODE MISMATCH - A new technique for sensing optical cavity mode mismatch using a mode converter formed from a cylindrical lens mode converting telescope, radio frequency quadrant photodiodes (RFQPDs), and a heterodyne detection scheme. The telescope allows the conversion of the Laguerre-Gauss basis to the Hermite-Gauss (HG) basis, which can be measured with quadrant photodiodes. Conversion to the HG basis is performed optically, measurement of mode mismatched signals is performed with the RFQPDs, and a feedback error signal is obtained with heterodyne detection. | 2018-12-27 |
20180374968 | PLASMON-ENHANCED BELOW BANDGAP PHOTOCONDUCTIVE TERAHERTZ GENERATION AND DETECTION - Disclosed are systems and methods for improving applications involving the generation and detection of electromagnetic radiation at terahertz (THz) frequencies. Embodiments of the systems and methods include the fabrication and use of plasmonic devices that enhance light-matter interaction at the nanometer scale by extreme focusing with nanostructured metals. This plasmonic enhancement is used to produce high efficiency THz photoconductive switches that combine the benefits of low-temperature grown GaAs while using mature 1.55 μm femtosecond lasers operating with photon energy below the GaAs band-gap. | 2018-12-27 |
20180374969 | Silicon-Germanium Photoelectric Detection Apparatus Based on On-Chip Mode Converter - An on-chip mode converter-based silicon-germanium photoelectric detection apparatus comprises an insulating substrate, an optical coupler, an on-chip mode converter and a multi-mode silicon-germanium photoelectric detector. The optical coupler, the converter and the photoelectric detector are sequentially connected and all fixed on silicon wafers of the insulating substrate. An incident fundamental mode optical signal is transmitted to the optical coupler through a single-mode fiber, enters the converter via the optical coupled. The converter converts the fundamental mode optical signal into a multi-mode optical field and enters the photoelectric detector, which converts the multi-mode optical field into an electrical signal. Heavily germanium-doped region are located in areas with relatively weak distributed light intensity of the multi-mode optical field. The absorption loss of the heavily germanium-doped region and third through-holes on the optical field is dramatically reduced and the responsiveness of the apparatus can be improved effectively. | 2018-12-27 |
20180374970 | LIGHT RECEIVING/EMITTING ELEMENT, SOLAR CELL, OPTICAL SENSOR, LIGHT EMITTING DIODE, AND SURFACE EMITTING LASER ELEMENT - A light receiving/emitting element | 2018-12-27 |
20180374971 | SOLUTION PROCESS FOR SILVER-CONTAINING CHALCOGENIDE LAYER DEPOSITION - A method of preparing a Ag | 2018-12-27 |
20180374972 | CHARGE EXTRACTION DEVICES, SYSTEMS, AND METHODS - A composite film structure having a first absorbing layer comprising a first material, a second absorbing layer comprising a second material, and a first collector layer disposed between the first absorbing layer and the second absorbing layer, wherein the first absorbing layer has a thickness that is less than a diffusion length of a photocarrier of the first material, and wherein the second absorbing layer has a thickness that is less than a diffusion length of a photocarrier of the second material. | 2018-12-27 |
20180374973 | SOLAR CELL STACK - Solar cell stack comprising III-V semiconductor layers, which includes a first subcell having a first band gap and a first lattice constant and which includes a second subcell having a second band gap and a second lattice constant, and which includes an intermediate layer sequence disposed between the two solar cells. The intermediate layer sequence including a first barrier layer and a first tunnel diode and a second barrier layer, and the layers being arranged in the specified order. The tunnel diode includes a degenerate n+ layer having a third lattice constant and a degenerate p+ layer having a fourth lattice constant, the fourth lattice constant being smaller than the third lattice constant, and the first band gap being smaller than the second band gap, and the p+ layer having a different material composition than the n+ layer. | 2018-12-27 |
20180374974 | ENCAPSULANT MATERIAL FOR PHOTOVOLTAIC MODULES AND METHOD OF PREPARING THE SAME - An encapsulant material for a photovoltaic module. The encapsulant material includes: between 30 and 50 parts by weight of fiber cloth and between 50 and 70 parts by weight of acrylic powder coating. The fiber cloth is made of fiber material. The acrylic powder coating includes an acrylic resin, a curing agent, and an additive. The acrylic powder coating is uniformly coated on the fiber cloth. A method of preparing the encapsulant material includes: uniformly coating the acrylic powder coating on the fiber cloth, thermally bonding the acrylic powder coating and the fiber cloth using pressure and heat, and piecewise cutting the thermally bonded acrylic powder coating and the fiber cloth. | 2018-12-27 |
20180374975 | COMPOSITIONS FOR UV SEQUESTRATION AND METHODS OF USE - Embodiments are directed to compositions comprising photoluminescent elements (e.g., quantum dots) that absorb UV radiation and emit longer wavelength non-ultraviolet radiation (luminescent down shifting), effectively sequestering the UV radiation. In certain aspects the photoluminescent elements are dispersed on or in a material. In a further aspect the material is transparent to light. In one respect the photoluminescent elements are dispersed in a transparent film. | 2018-12-27 |
20180374976 | SOLAR CELL HAVING A PLURALITY OF ABSORBERS CONNECTED TO ONE ANOTHER BY MEANS OF CHARGE-CARRIER-SELECTIVE CONTACTS - A tandem solar cell structure is described with the following features:
| 2018-12-27 |
20180374977 | Hybrid tandem solar cell - A tandem solar cell includes a top solar cell and a bottom solar cell. The top solar cell and the bottom solar cell each have a respective front surface and a rear surface, with the respective front surfaces being adapted for facing a radiation source during use. The top solar cell is arranged with its rear surface overlying the front surface of the bottom solar cell. The top solar cell includes a photovoltaic absorber layer with a bandgap greater than that of crystalline silicon. The bottom solar cell includes a crystalline silicon substrate. On at least a portion of the front surface of the bottom solar cell a passivating layer stack is disposed which includes a thin dielectric film and a secondary layer of either selective carrier extracting material or polysilicon. The thin dielectric film is arranged between the silicon substrate and the secondary layer. | 2018-12-27 |
20180374978 | SILICON RESISTOR SILICON PHOTOMULTIPLIER - A semiconductor device, silicon photomultiplier, and sensor are described. The disclosed semiconductor device is disclosed to include a substrate, a photosensitive area provided on the substrate, the photosensitive area corresponding to an area in which an electrical signal is generated in response to light impacting the photosensitive area, at least one trench substantially surrounding the photosensitive area, the at least one trench extending at least partially into the substrate, and a resistor confined by the at least one trench and in electrical communication with the active area such that the resistor is configured to carry electrical signals generated by the photosensitive area to a metal contact. | 2018-12-27 |
20180374979 | PHOTODETECTION ELEMENT INCLUDING PHOTOELECTRIC CONVERSION STRUCTURE AND AVALANCHE STRUCTURE - A photodetection element includes: a photoelectric conversion structure that contains a first material having an absorption coefficient higher than an absorption coefficient of monocrystalline silicon for light of a first wavelength, for which monocrystalline silicon exhibits absorption, and generates positive and negative charges by absorbing a photon; and an avalanche structure that includes a monocrystalline silicon layer, in which avalanche multiplication occurs as a result of injection of at least one selected from the group consisting of the positive and negative charges from the photoelectric conversion structure. The first material includes at least one selected from the group consisting of an organic semiconductor, a semiconductor-type carbon nanotube, and a semiconductor quantum dot. | 2018-12-27 |
20180374980 | METHOD FOR MANUFACTURING ULTRAVIOLET PHOTODETECTOR BASED ON Ga2O3 MATERIAL - A method for manufacturing an ultraviolet photodetector based on Ga | 2018-12-27 |
20180374981 | Metamaterial Thermal Pixel for Limited Bandwidth Electromagnetic Sourcing and Detection - A metamaterial pixel providing an electromagnetic emitter and/or en electromagnetic detector operating within a limited bandwidth. The metamaterial pixel is comprised of plasmonic elements arranged within a periodic photonic crystal array providing an electromagnetic emitter and/or an electromagnetic detector adapted in embodiments for operation at selected bandwidths within the wavelength range of visible out to a millimeter. Performance of the pixel in applications is enhanced with nanowires structured to enhance phononic scattering providing a reduction in thermal conductivity. In embodiments multiple pixels are adapted to provide a spectrometer for analyzing thermal radiation or electromagnetic reflection from a remote media. In other embodiments emitter and detector pixels are adapted to provide an absorptive spectrophotometer. In other embodiments one or more of metamaterial pixels are adapted as the transmitter and/or receiver within a communication system. In a preferred embodiment the pixel is fabricated using a silicon SOI starting wafer. | 2018-12-27 |
20180374982 | OPTOCOUPLER - An optocoupler having a transmitter unit and a receiver unit being electrically isolated from each other and optically coupled with each other and integrated into a shared housing. The receiver unit includes an energy source that has a first electrical contact and a second electrical contact. The transmitter unit includes at least one first transmitter diode having a first optical wavelength and a second transmitter diode having a second optical wavelength. The first optical wavelength differing from the second optical wavelength by a difference wavelength, and the energy source of the receiving unit including two partial sources. The energy source being designed as a current source or as a voltage source, and the first partial source including a first semiconductor diode, and the second partial source including a second semiconductor diode. Each partial source having multiple semiconductor layers for each partial source being arranged in the shape of a stack. | 2018-12-27 |
20180374983 | METHOD OF MANUFACTURING A SPAD CELL - A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area. | 2018-12-27 |
20180374984 | METHODS OF FORMING INTERDIGITATED BACK CONTACT LAYERS - Methods of forming interdigitated back contact (IBC) layers are provided. According to an aspect of the invention, a first layer having alternating regions of n-type amorphous hydrogenated silicon and p-type amorphous hydrogenated silicon is formed on a second layer of intrinsic amorphous hydrogenated silicon. The first layer and the second layer are then annealed, such that dopants from the first layer diffuse into the second layer, and the first layer and the second layer crystallize into polysilicon. | 2018-12-27 |
20180374985 | METHOD OF FORMING A LIGHT-EMITTING DEVICE - The present disclosure provides a method of forming a light-emitting device comprising: providing a growth substrate having a front side and a rear side; forming a sacrificial layer on the front side of the growth substrate; forming a protective structure on the sacrificial layer; forming a light-emitting structure on the protective structure, wherein the light-emitting structure emits a first peak wavelength; providing a carrier; joining the carrier and the light-emitting structure; and transforming the sacrificial layer by irradiating a laser beam from the rear side to separate the growth substrate from the light-emitting structure, wherein the laser beam emits a second peak wavelength, and wherein the protective structure reflects the second peak wavelength away from the light-emitting structure. | 2018-12-27 |
20180374986 | Heterostructure with Sacrificial Layer - Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device. | 2018-12-27 |
20180374987 | MICRO-LED TRANSFER METHOD AND MANUFACTURING METHOD - A micro-LED transfer method and a manufacturing method are disclosed. The micro-LED transfer method comprises: coating a sacrificial layer on a carrier substrate, wherein micro-LEDs are bonded on the carrier substrate through a first bonding layer (S | 2018-12-27 |
20180374988 | Monolithically Integrated InGaN/GaN Quantum Nanowire Devices - InGaN/GaN quantum layer nanowire light emitting diodes are fabricated into a single cluster capable of exhibiting a wide spectral output range. The nanowires having InGaN/GaN quantum layers formed of quantum dots are tuned to different output wavelengths using different nanowire diameters, for example, to achieve a full spectral output range covering the entire visible spectrum for display applications. The entire cluster is formed using a monolithically integrated fabrication technique that employs a single-step selective area epitaxy growth. | 2018-12-27 |
20180374989 | LED PANEL - An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells. | 2018-12-27 |
20180374990 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device includes a substrate having a top surface, wherein the top surface includes a first portion and a second portion; a first semiconductor stack including a first upper surface and a first side wall, wherein the first semiconductor stack is on the first portion; a second semiconductor stack including a second upper surface and a second side wall, wherein the second semiconductor stack is on the first upper surface, and wherein the second side wall is devoid of connecting the first side wall; a plurality of first concavo-convex structures on the first portion; and a plurality of second concavo-convex structures on the second portion; wherein the first side wall and the second portion of the top surface form an acute angle α between thereof; and wherein the second concavo-convex structures have smaller size than that of the first concavo-convex structures. | 2018-12-27 |
20180374991 | LED SIDEWALL PROCESSING TO MITIGATE NON-RADIATIVE RECOMBINATION - LEDs and methods of forming LEDs with various structural configurations to mitigate non-radiative recombination at the LED sidewalls are described. The various configurations described include combinations of LED sidewall surface diffusion with pillar structure, modulated doping profiles to form an n-p superlattice along the LED sidewalls, and selectively etched cladding layers to create entry points for shallow doping or regrowth layers. | 2018-12-27 |
20180374992 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device comprises an epitaxial structure comprising an main light-extraction surface, a lower surface opposite to the main light-extraction surface, a side surface connecting the main light-extraction surface and the lower surface, a first portion and a second portion between the main light-extraction surface and the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion and, in a cross-sectional view, the second portion comprises a first width near the main light-extraction surface and second width near the lower surface, and the first width is smaller than the second width. | 2018-12-27 |
20180374993 | TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE - Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device. | 2018-12-27 |
20180374994 | Light-Emitting Diode Chip, and Method for Manufacturing a Light-Emitting Diode Chip - A light-emitting diode chip and a method for manufacturing a light-emitting diode chip are disclosed. In an embodiment a light-emitting diode chip includes an epitaxial semiconductor layer sequence having an active zone configured to generate electromagnetic radiation during operation and a passivation layer comprising statically fixed electrical charge carriers, wherein the passivation layer is located on a side surface of the semiconductor layer sequence covering at least the active zone. | 2018-12-27 |
20180374995 | Light Emitting Device that is Highly Reliable, Thin and is not Damaged by External Local Pressure and Electronic Device - An object is to provide a highly reliable light emitting device which is thin and is not damaged by external local pressure. Further, another object is to manufacture a light emitting device with a high yield by preventing defects of a shape and characteristics due to external stress in a manufacture process. A light emitting element is sealed between a first structure body in which a fibrous body is impregnated with an organic resin and a second structure body in which a fibrous body is impregnated with an organic resin, whereby a highly reliable light emitting device which is thin and has intensity can be provided. Further, a light emitting device can be manufactured with a high yield by preventing defects of a shape and characteristics in a manufacture process. | 2018-12-27 |
20180374996 | ASSEMBLY INCLUDING A CARRIER HAVING A GLASS MATERIAL AND AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An assembly includes a carrier including a glass material, including at least one recess, wherein at least one optoelectronic semiconductor component is arranged in the at least one recess of the carrier, and at least one surface of the semiconductor component connects to the carrier via a melted surface including glass. | 2018-12-27 |
20180374997 | PACKAGE SUPPORT STRUCTURE AND LIGHT EMITTING DEVICE INCLUDING SAME - The present invention provides a package support structure and a light emitting device including same. The package support structure includes: a housing which comprises a light emitting surface, a backlight surface, a bottom surface and a groove; a conductive support which is partially covered by the housing and includes a first lead and a second lead that are separated from each other, where each of the first lead and the second lead includes an electrode portion and a bent portion, the electrode portion is exposed from the housing through the groove, and the bent portion extends outward from the electrode portion beyond the housing and bends toward the bottom surface of the housing; where one of the first lead and the second lead further includes a heat radiation portion, the heat radiation portion extend outward from the electrode portion and is exposed from the backlight surface of the housing. The package support structure provided in the present invention achieves the effect of reducing an upper piece error and the purpose of effectively removing the heat energy. | 2018-12-27 |
20180374998 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting unit, a light transmissive layer and an encapsulant. The light emitting unit includes a substrate, an epitaxial structure layer disposed on the substrate, and a first electrode and a second electrode disposed on the same side of the epitaxial structure layer, respectively. The light emitting unit is disposed on the light transmissive layer and at least a part of the first electrode and a part of the second electrode are exposed by the light transmissive layer. The encapsulant encapsulates the light emitting unit and at least exposes a part of the first electrode and a part of the second electrode. Each of the first electrode and the second electrode extends outward from the epitaxial structure layer, and covers at least a part of an upper surface of the encapsulant, respectively. | 2018-12-27 |
20180374999 | CONTROLLING OFF-STATE APPEARANCE OF A LIGHT EMITTING DEVICE - Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented. | 2018-12-27 |
20180375000 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device in accordance with one exemplary embodiment comprises at least one main light emitting unit including a light emitting diode chip and a wavelength converter to emit white light, wherein the light emitting diode chip comprises an ultraviolet chip, a violet chip, or a blue chip, and is adjustable to emit light corresponding to a spectral power distribution of morning sunlight, light corresponding to a spectral power distribution of afternoon sunlight, and light corresponding to a spectral power distribution of evening sunlight. | 2018-12-27 |
20180375001 | LIGHT SOURCE DEVICE AND PROJECTION DEVICE - A light source device includes: a semiconductor light emitting device which emits laser light; a wavelength conversion component which emits fluorescence by being irradiated with the laser light emitted from the semiconductor light emitting device as excitation light; and a photodetector on which a portion of light emitted from the wavelength conversion component is incident. The photodetector is disposed at a location off a light path of usable radiation light which is emitted from the wavelength conversion component to a space and used as illumination light. | 2018-12-27 |
20180375002 | CONVERSION ELEMENT AND RADIATION-EMITTING SEMICONDUCTOR DEVICE COMPRISING A CONVERSION ELEMENT OF SAID TYPE - Disclosed is a conversion element ( | 2018-12-27 |
20180375003 | LED LAMP WITH SLOW DECAY RED PHOSPHOR RESULTING IN CCT VARIATION WITH LIGHT OUTPUT - The invention provides a lighting device ( | 2018-12-27 |
20180375004 | LIGHT EMITTING DEVICE AND LEAD FRAME WITH RESIN - A light emitting device includes a resin package having a rectangular shape in a top view and two short-side lateral surfaces and two long-side lateral surfaces. The two short-side lateral surfaces include a first external surface and a second external surface located on an opposite side from the first external surface. The two long-side lateral surfaces include a third external surface and a fourth external lateral surface located on an opposite side from the third external lateral surface. The lead is not exposed on the third external lateral surface nor the fourth external lateral surface. The first lead is exposed at the first external lateral surface and the second external lateral surface, respectively flush with the resin member at the first external lateral surface and the second external lateral surface. The second lead is exposed at the second external lateral surface, flush with the resin part at the second external lateral surface. | 2018-12-27 |
20180375005 | LIGHT-EMITTING DEVICE PACKAGE - A light-emitting device package according to an embodiment may include a body; N (herein, N denotes a positive integer of 5 or more) upper pads disposed on the body to be spaced apart from each other; N-1 light-emitting device chips respectively arranged on N-1 upper pads among the N upper pads; and a plurality of first wires for electrically connecting the N-1 light-emitting device chips and the N upper pads to each other by at least one of a plurality of wiring structures. | 2018-12-27 |
20180375006 | SEMICONDUCTOR LIGHT SOURCE - A light source may comprise a thermally conductive frame comprising a base and a faceted portion extending from the base. The faceted portion may comprise a plurality of facets spaced circumferentially thereabout. Additionally, a hollow passageway may extend through the base and axially through the faceted portion. A plurality of LED chips may be arranged on the plurality of facets to provide an emission of light in an arc of 360 degrees. | 2018-12-27 |
20180375007 | POWER GENERATION BRICK - A power generating brick includes a brick body with a through hole provided along a vertical direction, a thermoelectric unit disposed in the through hole and having a heat collecting assembly, a thermoelectric power generation sheet and a heat sink. The heat sink is disposed at the lower end of the through hole, the thermoelectric power generation sheet is disposed on the heat sink, the heat collecting assembly is disposed on the thermoelectric power generation sheet so as to generate electrical energy from a temperature difference between the cold and hot sides of the thermoelectric power generation sheet, and output electrical energy via wires connected to the positive and negative electrodes of the thermoelectric power generation sheet. | 2018-12-27 |
20180375008 | METHOD OF FORMING ELECTRODES ON ELECTROCALORIC FILM - A method of making an electrocaloric element includes forming conductive layers on opposing surfaces of a film comprising an electrocaloric material to form an electrocaloric element, wherein the forming of the conductive layers includes one or more of: vapor deposition of the conductive layers under reduced pressure for a duration of time, wherein the duration of time under reduced pressure is less than 240 minutes; vapor deposition of the conductive layers under reduced pressure for a duration of time, wherein the duration of time of exposure to conductive material deposition is less than 240 minutes; vapor deposition of the conductive layers under reduced pressure, wherein the reduced pressure is 10 torr to 500 torr; or maintaining the film at a temperature of less than or equal to 200° C. during forming of the conductive layers. | 2018-12-27 |
20180375009 | PIEZOELECTRIC JETTING SYSTEM AND METHOD - A system and method for jetting a viscous material includes an electronic controller and a jetting dispenser operatively coupled with the electronic controller. The jetting dispenser includes an outlet orifice and a piezoelectric actuator operatively coupled with a movable shaft. The jetting dispenser is under control of the electronic controller for causing said piezoelectric actuator to move the shaft and jet an amount of the viscous material from the outlet orifice. The electronic controller sends a waveform to the piezoelectric actuator to optimize control of the jetting operation. | 2018-12-27 |
20180375010 | MULTILAYER PIEZOELECTRIC ELEMENT, PIEZOELECTRIC VIBRATION APPARATUS, AND ELECTRONIC DEVICE - In an embodiment, a multilayer piezoelectric element includes a multilayer piezoelectric body and multiple internal electrodes. The multilayer piezoelectric body has a pair of principal faces in a first-axis direction, a pair of end faces in a second-axis direction crossing at right angles with the first-axis direction and defining the longitudinal direction, and a pair of side faces in a third-axis direction crossing at right angles with the first-axis direction and second-axis direction. The multiple internal electrodes are placed inside the multilayer piezoelectric body and stacked in the first-axis direction. Among the multiple internal electrodes, a center internal electrode placed at the center part of the multilayer piezoelectric body is such that its first cross-sectional shape, as viewed from the third-axis direction, has undulations greater than the undulations of the second cross-sectional shape of the center internal electrode as viewed from the second-axis direction. | 2018-12-27 |
20180375011 | METHOD FOR PRODUCING A PIEZOELECTRIC RESONATOR ELEMENT AND METHOD FOR PRODUCING A PIEZOELECTRIC DEVICE USING THE PIEZOELECTRIC RESONATOR ELEMENT - A crystal resonator element | 2018-12-27 |
20180375012 | Vibrator Element, Vibrator, Oscillator, Electronic Apparatus, And Vehicle - A vibrator element includes a substrate that performs thickness-shear vibration, wherein an outer shape of the substrate in a plan view has a first side and a second side arranged in a first direction along a direction of the thickness-shear vibration and extending along a second direction crossing the first direction, a third side and a fourth side arranged in the second direction and extending in the first direction, a first connecting portion connecting the first side and the third side, and a second connecting portion connecting the first side and the fourth side, the first connecting portion and the second connecting portion are located inside of a region surrounded by the first side, the second side, the third side, the fourth side, and extension lines of these sides in the plan view, and the substrate has broken-off portions projecting from the first connecting portion and the second connecting portion. | 2018-12-27 |
20180375013 | Piezoelectric Transformer - A piezoelectric transformer is disclosed. In an embodiment a piezoelectric transformer includes an input region and an output region, wherein the input region is configured to convert an AC voltage into a mechanical oscillation, wherein the output region is configured to convert a mechanical oscillation into an electrical voltage, wherein the piezoelectric transformer includes a longest edge and a shortest edge, and wherein the longest edge includes a length that is twenty times a length of the shortest edge or less. | 2018-12-27 |
20180375014 | METHOD FOR THE PRODUCTION OF A SINGLE-CRYSTAL FILM, IN PARTICULAR PIEZOELETRIC - A method of manufacturing a monocrystalline layer comprises the following successive steps: providing a donor substrate comprising a piezoelectric material of composition ABO | 2018-12-27 |
20180375015 | MAGNETIC MEMORY - A magnetic memory includes magnetoresistance effect elements, each of which includes a first ferromagnetic metal layer in which a magnetization direction is fixed, a second ferromagnetic metal layer for a magnetization direction to be changed, and a nonmagnetic layer provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer, a first wiring connected to the first ferromagnetic metal layer of at least one magnetoresistance effect element, spin-orbit torque wirings, each of which is connected to each of the second ferromagnetic metal layers of the magnetoresistance effect elements and extend in a direction intersecting a lamination direction of the magnetoresistance effect element, one first control element connected to the first wiring, one second control element connected to each of first connection points of the spin-orbit torque wirings, and first cell selection elements, each of which is connected to each of second connection points of the spin-orbit torque wirings. | 2018-12-27 |
20180375016 | MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a magnetic memory device includes a metal-containing layer, a first magnetic layer, a second magnetic layer, a first intermediate layer, a third magnetic layer, a fourth magnetic layer, a second intermediate layer, and a controller. The metal-containing layer includes first, second, third, fourth, and fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the first magnetic layer and a portion of the third portion. The first intermediate layer includes a portion provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the third magnetic layer and a portion of the fourth portion. The second intermediate layer includes a portion provided between the third and fourth magnetic layers. The controller is electrically connected with the first portion and the second portion. | 2018-12-27 |
20180375017 | MAGNETO-RESISTIVE CHIP PACKAGE INCLUDING SHIELDING STRUCTURE - In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part. | 2018-12-27 |