52nd week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170372862 | HOLLOW FUSE BODY WITH TRENCH - Provided herein are protection devices, such as fuses, including a set of trenches or pockets for retention of solder therein. In some embodiments, a fuse includes a body including a center portion extending between a first and second end portions. The first end portion includes a first trench formed in a first end surface, and the second end portion includes a second trench formed in a second end surface. The fuse may further include a first and second endcaps surrounding respective first and second end portions. The fuse may include a fusible element disposed within a central cavity of the body, the fusible element extending between the first end surface and the second end surface. In some embodiments, solder may be disposed within the first trench and the second trench, wherein the solder is in contact with the fusible element, the first endcap, or the second endcap. | 2017-12-28 |
20170372863 | CATHODE ASSEMBLY FOR USE IN X-RAY GENERATION - A cathode assembly design is provided that includes two flat emitters, a longer emitter filament and a shorter emitter filament. In one implementation the focal spot sizes produced by the long and short emitters overlap over a range. Thus, one emitter filament may be suitable for generating small and concentrated focal spot sizes while the other emitter filament is suitable for generating small and large focal spots sizes. | 2017-12-28 |
20170372864 | X-RAY TUBE DEVICE - According to one embodiment, an X-ray tube device includes an anode target including a target surface and a cathode including a plurality of electron generation sources configured to emit the electrons, a vacuum envelope configured to house the cathode and the anode target and internally sealed in a vacuum airtight manner, and a quadrupole magnetic-field generator configured to form a magnetic field by being supplied with a current from a power source, the quadrupole magnetic-field generator being installed on an outer side of the vacuum envelope and constituted of a quadrupole surrounding a periphery of electron orbits of the electrons emitted simultaneously from each of the plurality of electron generation sources. | 2017-12-28 |
20170372865 | X-RAY TUBE DEVICE - According to one embodiment, an X-ray tube device includes a cathode which emits an electron in a direction of an electron path, an anode target which faces the cathode and includes a target surface generating an X-ray, a vacuum envelope which accommodates the cathode and the anode target and is sealed in a vacuum-tight manner, and a quadrupole magnetic field generation unit which forms a magnetic field when direct current is supplied from an electric source, is eccentrically provided with respect to a straight line accordance with the electron path outside the vacuum envelope, and includes a quadrupole surrounding a circumference of a part of the electron path. | 2017-12-28 |
20170372866 | Methods and devices for measuring orbital angular momentum states of electrons - A device for measuring electron orbital angular momentum states in an electron microscope includes the following components aligned sequentially in the following order along an electron beam axis: a phase unwrapper (U) that is a first electrostatic refractive optical element comprising an electrode and a conductive plate, where the electrode is aligned perpendicular to the conductive plate; a first electron lens system (L | 2017-12-28 |
20170372867 | LEFT-RIGHT CANTED-COSINE-THETA MAGNETS - Disclosed herein are superconducting gantry magnets that include multiple quadrupole winding sections placed in sequence on a curve such that the effective current direction is reversed between sections. This produces alternating quadrupole field regions along the length of the bend whose individual integral strengths can be tuned by the location of the current polarity transitions. A simple transition scheme to reverse the current between sections can be implemented to allow for the use of one continuous winding and power supply. Dipole windings can be included in the superconducting gantry magnets so that the magnets produce superposed dipole and alternating quadrupole fields. The disclosed design for the windings and transition scheme to reverse current polarity can be implemented for higher order multipoles as well. | 2017-12-28 |
20170372868 | ATOM PROBE WITH VACUUM DIFFERENTIAL - In an atom probe having a vacuum chamber containing a specimen mount and a detector for receiving ions emitted from the specimen, a high vacuum subchamber is provided about the specimen mount, with an aperture in the subchamber allowing passage of emitted ions to the detector. The high vacuum subchamber may be pumped to higher vacuum (lower pressure) than the vacuum chamber, and so long as the pressure in the vacuum chamber is below about 10 | 2017-12-28 |
20170372869 | HEAT TRANSFER PLATE AND WRITING APPARATUS - A heat transfer plate according to the present embodiment includes a first heat transfer unit transferring heat generated in a member mounted on the first heat transfer unit, the heat being generated due to shaping or controlling of a beam generated by a light source in a decompressed atmosphere, a second heat transfer unit provided around the first heat transfer unit, and a plurality of third heat transfer units making the first heat transfer unit movable with respect to the second heat transfer unit, the plurality of third heat transfer units connecting the first and second heat transfer units. | 2017-12-28 |
20170372870 | Inductive Plasma Source - Methods and apparatus to provide efficient and scalable RF inductive plasma processing are disclosed. In some aspects, the coupling between an inductive RF energy applicator and plasma and/or the spatial definition of power transfer from the applicator are greatly enhanced. The disclosed methods and apparatus thereby achieve high electrical efficiency, reduce parasitic capacitive coupling, and/or enhance processing uniformity. Various embodiments comprise a plasma processing apparatus having a processing chamber bounded by walls, a substrate holder disposed in the processing chamber, and an inductive RF energy applicator external to a wall of the chamber. The inductive RF energy applicator comprises one or more radiofrequency inductive coupling elements (ICEs). Each inductive coupling element has a magnetic concentrator in close proximity to a thin dielectric window on the applicator wall. | 2017-12-28 |
20170372871 | CATHODIC ARC DEPOSITION APPARATUS AND METHOD - A coating method includes vaporizing a portion of a cathode to form a metallic plasma, and directing the metallic plasma toward the workpiece. A first magnetic field generator, disposed in a first electrically conductive portion of a first stinger cup, is operated to steer the electrical arc about at least one evaporative surface of the cathode. a second portion of the electrically conductive stinger cup is selectively contacted with the cathode, and the first portion of the first stinger cup is spaced from the second portion from by a thermally insulating layer therebetween. The thermally insulating layer is disposed directly between the first magnetic field generator and the cathode when the first stinger cup is in contact with the cathode. | 2017-12-28 |
20170372872 | UNIFORMITY CONTROL CIRCUIT FOR USE WITHIN AN IMPEDANCE MATCHING CIRCUIT - An impedance matching circuit (IMC) is described. The IMC includes a first circuit that includes a first plurality of tuning elements defined along a path. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The first circuit is coupled to an output. The IMC further includes a second circuit having a second plurality of tuning elements. The second circuit has an input coupled to a megahertz (MHz) RF generator and is coupled to the output. The IMC includes a uniformity control circuit (UCC) defined from at least one of the plurality of tuning elements of the first circuit. The UCC is connected serially along the path of the first circuit to define a capacitance that at least partially influences a radial uniformity profile in an etch rate produced by a plasma chamber. | 2017-12-28 |
20170372873 | PLASMA PROCESSING METHOD - A plasma processing method for performing a plasma process on a substrate in a plasma processing apparatus is provided. The plasma processing method comprises: a sampling-average-value calculating process of sampling voltage detection signals and electric current detection signals and calculating an average value of these signals during a first monitoring time; a moving-average-value calculating process of calculating a moving average value of the voltage detection signals and the electric current detection signals; a load impedance-measurement-value calculating process of calculating a measurement value of a load impedance with respect to a first high frequency power supply; and a reactance control process of controlling a reactance of a variable reactance element such that the measurement value of the load impedance is equal or approximate to a preset matching point corresponding to impedance on the side of the first high frequency power supply. | 2017-12-28 |
20170372874 | Bulk sintered solid solution ceramic which exhibits fracture toughness and halogen plasma resistance - A bulk, sintered solid solution-comprising ceramic article useful in semiconductor processing, which is resistant to erosion by halogen-containing plasmas and provides advantageous mechanical properties. The solid solution-comprising ceramic article is formed from a combination of yttrium oxide and zirconium oxide. The bulk, sintered solid solution-comprising article is formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 94 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 6 mole %. | 2017-12-28 |
20170372875 | PLASMA GENERATOR - Provided is a plasma generator for improving uniformity of plasma. The plasma generator which includes a pair of source electrode unit | 2017-12-28 |
20170372876 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of: (a) placing a semiconductor wafer over a stage provided in a chamber, the pressure in the inside of which is reduced by vacuum pumping; and (b) after the step (a), forming plasma in the chamber in a state where the semiconductor wafer is adsorbed and held by the stage, so that desired etching processing is performed on the semiconductor wafer. Herein, before the step (a), O | 2017-12-28 |
20170372877 | SUPPORT APPARATUS FOR PLASMA ADJUSTMENT, METHOD FOR ADJUSTING PLASMA, AND STORAGE MEDIUM - A support apparatus for plasma adjustment includes a storage part storing index value estimation data including data defining an amount of change in an index value between adjustment positions for each of the adjustment parts, the index value corresponding to electron density of plasma, an input part for inputting a measurement result of the index value obtained when plasma is generated and the adjustment positions of the adjustment parts, and a data processing part configured to estimate the index value for each of adjustment positions of the adjustment parts based on input items input to the input part and the estimation data and configured to select proper combinations of the adjustment positions of the adjustment parts based on combinations of the adjustment positions of the adjustment parts and estimated values of a plurality of index values in the circumferential direction corresponding to the respective combinations. | 2017-12-28 |
20170372878 | PLASMA PROCESSING APPARATUS AND OPERATIONAL METHOD THEREOF - A plasma processing apparatus includes: a detector configured to detect a change in an intensity of light emission from plasma formed inside a processing chamber; and a unit configured to adjust conditions for forming the plasma or processing a wafer arranged inside the processing chamber using an output from the detector, wherein the detector detects a signal of the intensity of light emission at plural time instants before an arbitrary time instant during processing, and wherein the adjusting unit removes the component of a temporal change of a long cycle of the intensity of light emission from this detected signal and detects the component of a short temporal change of the intensity of light emission, and adjusts the conditions for forming the plasma or processing a wafer arranged inside the processing chamber based on the short temporal change of the detected intensity of light emission. | 2017-12-28 |
20170372879 | TANTALUM SPUTTERING TARGET, AND PRODUCTION METHOD THEREFOR - Provided is a tantalum target, wherein, when a direction normal to a rolling surface (ND), which is a cross section perpendicular to a sputtering surface of a target, is observed via an electron backscatter diffraction pattern method, an area ratio of crystal grains of which a {100} plane is oriented in the ND is 30% or more. An object of the present invention is to provide a tantalum sputtering target in which a deposition rate can be appropriately controlled under high-power sputtering conditions. When sputter-deposition is performed using this kind of a tantalum target, it is possible to form a thin film having superior film thickness uniformity and improve the productivity of the thin film formation process, even for micro wiring. | 2017-12-28 |
20170372880 | ADJUSTABLE RETURN PATH MAGNET ASSEMBLY AND METHODS - The invention provides a sputter deposition assembly that includes a sputtering chamber, a sputtering target, and a magnet assembly. The magnet assembly includes a magnetic backing plate with a blind recess into which a moveable magnetic control body can be adjustably disposed. | 2017-12-28 |
20170372881 | Mass Spectrometer - A mass spectrometer is disclosed comprising a mass selective ion trap and a quadrupole rod set mass filter arranged downstream of the mass selective ion trap. Ions are mass selectively ejected from the ion trap in a substantially synchronised manner with the scanning of the mass filter in order to increase the duty cycle of the mass filter. | 2017-12-28 |
20170372882 | METHOD OF TANDEM MASS SPECTROMETRY - A method of tandem mass spectrometry is disclosed. A quasi-continuous stream of ions from an ion source ( | 2017-12-28 |
20170372883 | Ion Trap Mass Spectrometer - An apparatus | 2017-12-28 |
20170372884 | FORMATION OF EPITAXIAL LAYERS VIA DISLOCATION FILTERING - A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions. | 2017-12-28 |
20170372885 | MANUFACTURING PROCESS OF WAFER THINNING - A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness. | 2017-12-28 |
20170372886 | Deposition of SiN - Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment. | 2017-12-28 |
20170372887 | TRENCH FORMATION METHOD FOR RELEASING A SUBSTRATE FROM A SEMICONDUCTOR TEMPLATE - A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template. | 2017-12-28 |
20170372888 | SEMICONDUCTOR WAFER COMPRISING A MONOCRYSTALLINE GROUP-IIIA NITRIDE LAYER - Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride. | 2017-12-28 |
20170372889 | METHODS OF PRODUCING SEED CRYSTAL SUBSTRATES AND GROUP 13 ELEMENT NITRIDE CRYSTALS, AND SEED CRYSTAL SUBSTRATES - A seed crystal layer is provided on a supporting body. A laser light is irradiated from a side of the supporting body to provide an altered portion along an interface between the supporting body and seed crystal layer. The altered layer is composed of a nitride of a group 13 element and comprising a portion into which dislocation defects are introduced or an amorphous portion. | 2017-12-28 |
20170372890 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor to the substrate in a process chamber and exhausting the precursor from a first exhaust system; and supplying a reactant to the substrate in the process chamber and exhausting the reactant from a second exhaust system. In the forming of the film, when the precursor does not flow through the first exhaust system, a deactivator that is a material different from the reactant is directly supplied from a supply port provided in the first exhaust system into the first exhaust system. | 2017-12-28 |
20170372891 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. | 2017-12-28 |
20170372892 | Gap Filling Materials and Methods - In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure. | 2017-12-28 |
20170372893 | CLEANING APPARATUS AND SUBSTRATE PROCESSING APPARATUS - The cleaning apparatus includes multiple kinds of cleaning modules each configured to perform a cleaning processing of a substrate, a first accommodating section configured to accommodate the multiple kinds of cleaning modules therein, and a fluid supply section configured to supply a fluid to the cleaning modules accommodated in the first accommodating section through a pipe. Each of the multiple kinds of cleaning modules includes a pipe connection portion having a common connection position to be connected with the pipe. | 2017-12-28 |
20170372894 | Method of Manufacturing Semiconductor Device - Described herein is a technique capable of improving the productivity of manufacturing of a semiconductor device in a method of processing a film by repeating different processes. A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process vessel; (b) forming a first layer by supplying a first gas into the process vessel by a gas supply unit while maintaining the substrate at a first temperature by a temperature control unit; and (c) forming a second layer different from the first layer by supplying a second gas different from the first gas into the process vessel by the gas supply unit while maintaining the substrate at a second temperature different from the second temperature by the temperature control unit. | 2017-12-28 |
20170372895 | METHOD OF DENSIFYING FILMS IN SEMICONDUCTOR DEVICE - Methods of densifying films, cross-linking films, and controlling the stress of films are provided herein. Methods include forming a removable film on a substrate comprising a material to be densified, and annealing the substrate to transfer stress from the removable film to the material and thereby densify the material. Some methods involve depositing a tensile capping layer on the material to be densified on a substrate and annealing the substrate at a temperature greater than about 450° C. Some methods include clamping the substrate including the material to be densified to a shaped pedestal using an electrostatic chuck to apply compressive stress to the material to be densified. | 2017-12-28 |
20170372896 | TRANSPARENT NANOCRYSTALLINE DIAMOND COATINGS AND DEVICES - A method for coating a substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The plasma ball has a diameter. The plasma ball is disposed at a first distance from the substrate and the substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the substrate, and a diamond coating is deposited on the substrate. The diamond coating has a thickness. Furthermore, the diamond coating has an optical transparency of greater than about 80%. The diamond coating can include nanocrystalline diamond. The microwave plasma source can have a frequency of about 915 MHz. | 2017-12-28 |
20170372897 | High Rate Sputter Deposition of Alkali Metal-Containing Precursor Films Useful to Fabricate Chalcogenide Semiconductors - The present invention provides methods to sputter deposit films comprising alkali metal compounds. At least one target comprising one or more alkali metal compounds and at least one metallic component is sputtered to form one or more corresponding sputtered films. The at least one target has an atomic ratio of the alkali metal compound to the at least one metallic component in the range from 15:85 to 85:15. The sputtered film(s) incorporating such alkali metal compounds are incorporated into a precursor structure also comprising one or more chalcogenide precursor films. The precursor structure is heated in the presence of at least one chalcogen to form a chalcogenide semiconductor. The resultant chalcogenide semiconductor comprises up to 2 atomic percent of alkali metal content, wherein at least a major portion of the alkali metal content of the resultant chalcogenide semiconductor is derived from the sputtered film(s) incorporating the alkali metal compound(s). The chalcogenide semiconductors are useful in microelectronic devices, including solar cells. | 2017-12-28 |
20170372898 | Methods for the Continuous, Large-Scale Manufacture of Functional Nanostructures - A method for forming nanostructures including introducing a hollow shell into a reactor. The hollow shell has catalyst nanoparticles exposed on its interior surface. The method also includes introducing a precursor into the reactor to grow nanostructures from the interior surface of the hollow shell from the catalyst nanoparticles. | 2017-12-28 |
20170372899 | DIAMOND LIKE CARBON LAYER FORMED BY AN ELECTRON BEAM PLASMA PROCESS - Methods for forming a diamond like carbon layer with desired film density, mechanical strength and optical film properties are provided. In one embodiment, a method of forming a diamond like carbon layer includes generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, and forming a diamond like carbon layer on the surface of the substrate. The diamond like carbon layer is formed by an electron beam plasma process, wherein the diamond like carbon layer serves as a hardmask layer in an etching process in semiconductor applications. The diamond like carbon layer may be formed by bombarding a carbon containing electrode disposed in a processing chamber to generate a secondary electron beam in a gas mixture containing carbon to a surface of a substrate disposed in the processing chamber, and forming a diamond like carbon layer on the surface of the substrate from elements of the gas mixture. | 2017-12-28 |
20170372900 | Multi-Layer Mask and Method of Forming Same - A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed. | 2017-12-28 |
20170372901 | METHOD FOR PREPARING ELECTRODE - The present disclosure discloses a method for preparing electrode including: providing a substrate; forming a buffer layer on the substrate; forming a patterned photoresist on the surface of the buffer layer away from the substrate, the photoresist has a bottom surface and a top surface disposed opposite and a side connected between the bottom surface and the top surface, the bottom surface is bonded to the buffer layer; by dry etching, the portions of the photoresist not covered by the buffer layer is removed to form a receiving area; depositing a conductive film, the conductive film layer includes a waste material forming on the top surface and an electrode filling in the receiving area; and stripping the waste material and the photoresist. The yields of the method for preparing electrode of the present disclosure is high. | 2017-12-28 |
20170372902 | CRYSTAL PRODUCTION SYSTEMS AND METHODS - Mechanically fluidized systems and processes allow for efficient, cost-effective production of silicon coated particles having very low levels of contaminants such as metals and oxygen. These silicon coated particles are produced, conveyed, and formed into crystals in an environment maintained at a low oxygen level or a very low oxygen level and a low contaminant level or very low contaminant level to minimize the formation of silicon oxides and minimize the deposition of contaminants on the coated particles. Such high purity coated silicon particles may not require classification and may be used in whole or in part in the crystal production method. The crystal production method and the resultant high quality of the silicon boules produced are improved by the reduction or elimination of the silicon oxide layer and contaminants on the coated particles. | 2017-12-28 |
20170372903 | METHOD FOR DOPING SEMICONDUCTORS - The present invention relates to a process for the production of structured, highly efficient solar cells and of photovoltaic elements which have regions of different doping. The invention likewise relates to the solar cells having increased efficiency produced in this way. | 2017-12-28 |
20170372904 | METHOD FOR OBTAINING PATTERNS IN A LAYER - The invention relates in particular to a method for producing subsequent patterns in an underlying layer ( | 2017-12-28 |
20170372905 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - When a nitride semiconductor layer into which impurity ions have been implanted is subjected to annealing after a protective film is provided on the nitride semiconductor layer, vacancy defects may be disadvantageously prevented from escaping outside through the surface of the nitride semiconductor layer and disappearing. A manufacturing method of a semiconductor device including a nitride semiconductor layer is provided. The manufacturing method includes implanting impurities into the nitride semiconductor layer, performing a first annealing on the nitride semiconductor layer at a first temperature within an atmosphere of a nitrogen atom containing gas without providing a protective film on the nitride semiconductor layer, forming the protective film on the nitride semiconductor layer after the first annealing, and after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature. | 2017-12-28 |
20170372906 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate. | 2017-12-28 |
20170372907 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess. | 2017-12-28 |
20170372908 | CUTTING METHOD FOR CUTTING PROCESSING-TARGET OBJECT AND CUTTING APPARATUS THAT CUTS PROCESSING-TARGET OBJECT - There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses. | 2017-12-28 |
20170372909 | SINGLE OR MUTLI BLOCK MASK MANAGEMENT FOR SPACER HEIGHT AND DEFECT REDUCTION FOR BEOL - Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment. | 2017-12-28 |
20170372910 | REINFORCING STRUCTURE, VACUUM CHAMBER AND PLASMA PROCESSING APPARATUS - There is provided a reinforcing structure in which a plurality of beam members provided on a top surface of a cover of a vacuum chamber for performing predetermined processing on a substrate is combined to reinforce the cover. The reinforcing structure includes a ring-shaped portion formed by arranging beam members in a ring shape at a central region of the top surface of the cover, and a radial portion formed by radially extending beam members from the ring-shaped portion. | 2017-12-28 |
20170372911 | ION BEAM ETCHING UTILIZING CRYOGENIC WAFER TEMPERATURES - The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate. The disclosed embodiments may be used to achieve high quality anisotropic etching results. | 2017-12-28 |
20170372912 | Systems and Methods for Reverse Pulsing - Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber. | 2017-12-28 |
20170372913 | Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same - A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described. | 2017-12-28 |
20170372914 | Apparatus and Method for Processing Gas, and Storage Medium - An apparatus for processing a gas includes: a mounting part installed in a processing container and on which a substrate is mounted; a first gas flow path where a first gas is supplied from a first gas supply mechanism to an upstream portion of the first gas flow path, and a downstream portion of the first gas flow path is branched to form first branch paths; a second gas flow path where a second gas is supplied from a second gas supply mechanism to an upstream portion of the second gas flow path, and a downstream portion of the second gas flow path is branched to form second branch paths; an annular mixing chamber to which a discharge path is connected; and a gas discharge part discharging a mixture gas. | 2017-12-28 |
20170372915 | PLASMA ETCHING METHOD - The present invention is a plasma etching method comprising subjecting a silicon-containing film to plasma etching using a process gas, the process gas comprising a linear saturated fluorohydrocarbon compound represented by a formula (1), and a gaseous fluorine-containing compound (excluding the compound represented by the formula (1)) that functions as a fluorine radical source under plasma etching conditions, wherein x represents 3 or 4, y represents an integer from 5 to 9, and z represents an integer from 1 to 3. The present invention provides a plasma etching method that can selectively etch the silicon-containing film with respect to the mask, and form a hole or a trench having a good shape within a short time. | 2017-12-28 |
20170372916 | ETCHING PROCESS METHOD - An etching process method is provided that includes outputting a first high frequency power from a first high frequency power supply in a cryogenic temperature environment where the temperature of a substrate is controlled to be less than or equal to −35° C., supplying a sulfur fluoride-containing gas and a hydrogen-containing gas, generating a plasma from the supplied sulfur fluoride-containing gas and hydrogen-containing gas, and etching a laminated film made up of laminated layers of silicon-containing films having different compositions with the generated plasma. | 2017-12-28 |
20170372917 | PATTERN TRANSFER TECHNIQUE AND METHOD OF MANUFACTURING THE SAME - A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided. | 2017-12-28 |
20170372918 | Composition and Method Used for Chemical Mechanical Planarization of Metals - Compositions for use in CMP processing and methods of CMP processing. The composition utilizes low levels of particulate material, in combination with at least one amino acid, at least one oxidizer, and water to remove a metal layer such as one containing copper to a stop layer with high selectivity. | 2017-12-28 |
20170372919 | Flowable Amorphous Silicon Films For Gapfill Applications - Methods for seam-less gapfill comprising forming a flowable film by PECVD and curing the flowable film to solidify the film. The flowable film can be formed using a higher order silane and plasma. A UV cure, or other cure, can be used to solidify the flowable film. | 2017-12-28 |
20170372920 | WAFER LEVEL PACKAGING OF MICROBOLOMETER VACUUM PACKAGE ASSEMBLIES - An apparatus for the wafer level packaging (WLP) of micro-bolometer vacuum package assemblies (VPAs), in one embodiment, includes a wafer alignment and bonding chamber, a bolometer wafer chuck and a lid wafer chuck disposed within the chamber in vertically facing opposition to each other, means for creating a first ultra-high vacuum (UHV) environment within the chamber, means for heating and cooling the bolometer wafer chuck and the lid wafer chuck independently of each other, means for moving the lid wafer chuck in the vertical direction and relative to the bolometer wafer chuck, means for moving the bolometer wafer chuck translationally in two orthogonal directions in a horizontal plane and rotationally about a vertical axis normal to the horizontal plane, and means for aligning a fiducial on a bolometer wafer held by the bolometer wafer chuck with a fiducial on a lid wafer held by the lid wafer chuck. | 2017-12-28 |
20170372921 | SUBSTRATE TREATING METHOD - An upper end of a tubular member surrounding a common pipe line is closed by a lid member. The lid member has an opening formed therein for supplying liquids to adjacent the rotation center on the back surface of a wafer. Deionized water supplied at normal temperature to the interior of the tubular member, after serving to cool the common pipe line, flows out of a lower end of the tubular member. | 2017-12-28 |
20170372922 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - Provided is a substrate treating apparatus. The substrate treating apparatus comprises: a support unit provided to support the substrate and rotate the substrate; a treatment liquid nozzle for supplying the treatment liquid onto the substrate supported by the support unit; a pre-wet liquid nozzle for supplying a pre-wet liquid onto a substrate supported by the support unit; and a controller for controlling the treatment liquid nozzle and the pre-wet liquid nozzle, wherein the controller controls the treatment liquid nozzle and the pre-wet liquid nozzle to perform a pre-wet step for supplying the pre-wet liquid to the substrate, and then a treatment liquid supply step for supplying the treatment liquid to the substrate and supplying the pre-wet liquid to the substrate during the supplying the treatment liquid to the substrate. | 2017-12-28 |
20170372923 | FLOW PASSAGE STRUCTURE, INTAKE AND EXHAUST MEMBER, AND PROCESSING APPARATUS - A flow passage structure includes a member. The member includes a plurality of first openings, a plurality of second openings, a flow passage, and a plurality of joining and branching parts. The flow passage connects the first openings with the second openings. The joining and branching parts are provided in the flow passage and each have a plurality of first parts having respective first ends connected with each other and a plurality of second parts having respective second ends connected with each other. The second parts are closer to the second openings than the first parts are, in a path between the first opening and the second opening. The first ends are connected with the second ends in each joining and branching part. | 2017-12-28 |
20170372924 | SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS - A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure. | 2017-12-28 |
20170372925 | SYSTEM AND RELATED TECHNIQUES FOR HANDLING ALIGNED SUBSTRATE PAIRS - An industrial-scale system and method for handling precisely aligned and centered semiconductor substrate (e.g., wafer) pairs for substrate-to-substrate (e.g., wafer-to-wafer) aligning and bonding applications is provided. Some embodiments include an aligned substrate transport device having a frame member and a spacer assembly. The centered semiconductor substrate pairs may be positioned within a processing system using the aligned substrate transport device, optionally under robotic control. The centered semiconductor substrate pairs may be bonded together without the presence of the aligned substrate transport device in the bonding device. The bonding device may include a second spacer assembly which operates in concert with that of the aligned substrate transport device to perform a spacer hand-off between the substrates. A pin apparatus may be used to stake the substrates during the hand-off. | 2017-12-28 |
20170372926 | SUBSTRATE TREATING UNIT, BAKING APPARATUS INCLUDING THE SAME, AND SUBSTRATE TREATING METHOD USING BAKING APPARATUS - Disclosed is a heating unit that heats a substrate. The heating unit includes a housing providing a treatment space in the interior thereof, a heating plate supporting a substrate in the treatment space, a heating member provided in the heating plate and configured to heat-treat the substrate supported by the heating plate, an exhaust member configured to exhaust gas in an interior space of the housing, and an exterior gas supply part installed in the housing and configured to supply exterior gas into the treatment space, wherein the exterior gas supply part includes a plurality of inlets provided in the housing, and a plurality of flow rate adjusting members installed in the inlets, respectively, and configured to adjust flow rates of the exterior gas introduced into the inlets. | 2017-12-28 |
20170372927 | DIODES OFFERING ASYMMETRIC STABILITY DURING FLUIDIC ASSEMBLY - Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate. | 2017-12-28 |
20170372928 | SUBSTRATE PROCESSING SYSTEM AND TEMPERATURE CONTROL METHOD - Disclosed is a substrate processing system including a substrate processing apparatus; and a control device that controls the substrate processing apparatus. The substrate processing apparatus includes: a chamber; a placing table provided within the chamber; and heaters embedded in the placing table corresponding to division regions, respectively. The control device includes: a holding unit that holds a table for each of the division regions; a measuring unit that measures the resistance value of each of the heaters embedded in the placing table for each of the division regions; and a controller that estimates a temperature of each of the division regions corresponding to the resistance value of each of the heaters measured by the measuring unit with reference to the table for each of the division regions, and controls an electric power to be supplied to each of the heaters so that the estimated temperature becomes a target temperature. | 2017-12-28 |
20170372929 | MULTIPLE GASES PROVIDING METHOD AND MULTIPLE GASES PROVIDING APPARATUS - Provided is a method for multi-supplying gas, the method comprising: installing a control valve and an flow meter on each of a plurality of branch lines branched from a main supply line, in which one or more gases are supplied, and supplying the gas; and providing the gas by adjusting flow of the gas by a controller connected to each of the control valve and the flow meter, wherein the controller has a first control manner, which controls each of the control valves based on a rate of flow measured by the flow meter to required portion flow for each branch line, and the first control manner adjusts an open rate of the control valve if the rate of the measured flow to the required portion flow is not within a predetermined range, and a unit of adjusting the control valve increases or decreases according to a difference between the measured flow and the required portion flow. | 2017-12-28 |
20170372930 | Substrate Storage and Processing - The system, method and apparatus described relates generally to a device related to substrate storage and processing. In one example embodiment to methods, apparatus, and systems of a substrate storage and processing module improving upon existing devices used in one or more instances for substrate transportation, sorting, and cleaning. The single piece design system may contain and support substrates in a method, reducing strain on its contents by utilizing an innovative support system without the use of standard clamping techniques and, in this or other iterations, such stacking methods may minimize chaffing of surfaces. Thus the device is vastly improved in its ability to preserve pristine conditions of contained substrates. | 2017-12-28 |
20170372931 | HORIZONTAL SUBSTRATE CONTAINER WITH INTEGRAL CORNER SPRING FOR SUBSTRATE CONTAINMENT - A substrate container including substrate supports, such as concentric rings, adapted to receive substrates in a substrate stack. The container includes a base and a top cover to enclose the substrate stack. A latching mechanism is adapted to latch the top cover to the base and secure the substrate stack within the container. The latching mechanism includes resilient corner flanges on an outside portion of the container, the flanges acting as springs to exert a biasing force on the cover and on the substrate stack. The flanges hold the stack within the container while accommodating stack-up uncertainty caused by the accumulation of uncertainties due to component machining tolerances. In some embodiments, a gap is created between a side wall of the top cover and the base of the container to assure compression of the substrate stack. Deflection limiters may be implemented to prevent over-deflection of the flanges. | 2017-12-28 |
20170372932 | INTEGRATED CHIP DIE CARRIER EXCHANGER - The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated. | 2017-12-28 |
20170372933 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A substrate treating apparatus comprises: an alignment unit for aligning a substrate placed in a support unit in position; and a teaching unit for setting a transfer position for transferring the substrate onto the support unit of the transfer unit, wherein the teaching unit correcting a transfer position of the transfer unit based on a difference value between a first position of a substrate placed on a hand of the transfer unit when the transfer unit is transferring the substrate and a second position of a substrate placed on the hand of the transfer unit that picks up the substrate aligned to the support unit in position. | 2017-12-28 |
20170372934 | WAFER HOLDING APPARATUS AND BASEPLATE STRUCTURE - A wafer holding apparatus includes an electrostatic chuck configured to clamp an object, a baseplate made of aluminum and configured to support the electrostatic chuck, a water pathway portion disposed in contact with or inside the baseplate and made of a metal having higher corrosion resistance than aluminum, and a water pathway disposed inside the water pathway portion and having an entire wall surface thereof constituted by the water pathway portion, wherein the baseplate and the water pathway portion are directly bonded to each other. | 2017-12-28 |
20170372935 | METHOD OF COLLECTIVE FABRICATION OF 3D ELECTRONIC MODULES CONFIGURED TO OPERATE AT MORE THAN 1 GHZ - A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules. | 2017-12-28 |
20170372936 | THERMOSETTING ADHESIVE SHEET AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A thermosetting adhesive sheet and a method for manufacturing a semiconductor device capable of reducing warping of a semiconductor wafer are provided. The thermosetting adhesive sheet is to be applied to a grinding-side surface of a semiconductor wafer and cured before dicing and includes a polymer containing an elastomer, a (meth) acrylate containing more than 95% wt of a polyfunctional (meth) acrylate with respect to total (meth)acrylate content, an organic peroxide having a one-minute half-life temperature of 130° C. or lower, and a transparent filler. Thereby, the thermosetting adhesive sheet significantly shrinks and generates a stress opposing a warp direction of the semiconductor wafer, enabling the semiconductor wafer to be maintained in a flat state. | 2017-12-28 |
20170372937 | WORKPIECE HOLDER FOR A WET PROCESSING SYSTEM - Techniques herein provide a workpiece holder that can hold relatively flexible and thin workpieces for transport and electrochemical deposition while avoiding electroplating fluid wetting contacts or contact regions of a given workpiece. A workpiece holder frame holds a workpiece by gripping the workpiece on opposing sides of the workpiece. A flexure structure is used for clamping a given workpiece and for providing an electrical path for supplying a current to the workpiece. An elastomer covering provides sealing and insulation of the electrical flexure structure. The workpiece holder also provides tension to the workpiece to help hold the workpiece flat during processing. Each flexure structure can provide an independent electrical path to the workpiece surface. | 2017-12-28 |
20170372938 | WORKPIECE LOADER FOR A WET PROCESSING SYSTEM - Techniques herein provide a workpiece handling and loading apparatus for loading, unloading, and handling relatively flexible and thin substrates for transport and electrochemical deposition. Such a system assists with workpiece holder exchange between a delivery cartridge or magazine, and a workpiece holder. Embodiments include a workpiece handler configured to provide an air cushion to a given workpiece, and maneuvering to a given workpiece holder that can edge clamp the workpiece. | 2017-12-28 |
20170372939 | SENSOR ARRAY WITH ANTI-DIFFUSION REGION(S) TO EXTEND SHELF LIFE - The inventive concepts disclosed herein are generally directed to a sensor array device that has a prolonged shelf life but requires only a minimal amount of sample volume in order to test two or more analytes concurrently. In order to ensure the sensor array has a sufficient shelf life, anti-diffusion regions are positioned among the reaction wells in order to slow the processes of diffusion. The use of anti-diffusion regions, as described herein, can be used to optimize the number of sensors that can be fit into a sensor array designed for reduced sample liquid volumes (e.g., less than 100 μL) as well as extending the test strip's shelf life. | 2017-12-28 |
20170372940 | Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2017-12-28 |
20170372941 | Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2017-12-28 |
20170372942 | Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2017-12-28 |
20170372943 | Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2017-12-28 |
20170372944 | METHODS FOR FABRICATING TRENCH ISOLATION STRUCTURE - A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure. | 2017-12-28 |
20170372945 | Reduced Substrate Effects in Monolithically Integrated RF Circuits - A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate. | 2017-12-28 |
20170372946 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING AN ISOLATION REGION - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices. | 2017-12-28 |
20170372947 | CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS - Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density. | 2017-12-28 |
20170372948 | Interconnect Structure and Method - A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material. | 2017-12-28 |
20170372949 | TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT - Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner. | 2017-12-28 |
20170372950 | INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES - A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ | 2017-12-28 |
20170372951 | METHOD AND PROCESSING APPARATUS FOR PERFORMING PRE-TREATMENT TO FORM COPPER WIRING IN RECESS FORMED IN SUBSTRATE - There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate. | 2017-12-28 |
20170372952 | SUBSTRATE AND METHOD INCLUDING FORMING A VIA COMPRISING A CONDUCTIVE LINER LAYER AND CONDUCTIVE PLUG HAVING DIFFERENT MICROSTRUCTURES - In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures. | 2017-12-28 |
20170372953 | CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES - Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized. | 2017-12-28 |
20170372954 | REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES - A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided. | 2017-12-28 |
20170372955 | PROCESS OF FORMING SEMICONDUCTOR DEVICE HAVING INTERCONNECTION FORMED BY ELECTRO-PLATING - A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on the first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask retreating from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching. | 2017-12-28 |
20170372956 | SELF-ALIGNED CONTACT - A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and extends less than a width of the gate conductor. A self-aligned contact is formed adjacent to the sidewall spacer of the gate structure and is electrically isolated from the gate conductor by the partial dielectric cap and the sidewall spacer. | 2017-12-28 |
20170372957 | SELF-ALIGNED CONTACT - A method for fabricating self-aligned contacts includes forming a liner over a gate structure having a gate conductor and one sidewall spacer and etching an exposed gate conductor to form a recess extending less than a width of the gate conductor. A dielectric layer is conformally deposited to fill the recess between the liner and the one sidewall spacer to form a partial dielectric cap formed on the gate conductor. A self-aligned contact is formed adjacent to the one sidewall spacer of the gate structure that is electrically isolated from the gate conductor by the partial dielectric cap and the at least one sidewall spacer. | 2017-12-28 |
20170372958 | FILM-EDGE TOP ELECTRODE - In one example, an electronic device includes a layer of insulator on a substrate extending to a set of device elements. A first set of metal layers having a first thickness lithographically patterned and defined horizontally to the substrate on the layer of insulator. A second set of metal layers with a second thickness having a first portion defined horizontally to the substrate and patterned over and contacting the first set of metal layers, and a second portion defined vertically to the substrate and contacting the first portion and extending vertically through the layer of insulator to at least one device element and contacting the at least one device element with a width of the second thickness thereby creating at least one sub-lithographic film-edge top electrode. | 2017-12-28 |
20170372959 | GATE TIE-DOWN ENABLEMENT WITH INNER SPACER - A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact. | 2017-12-28 |
20170372960 | SELF-ALIGNED INTERCONNECTS FORMED USING SUBTRACTIVE TECHNIQUES - A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials. | 2017-12-28 |
20170372961 | VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES - Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions. | 2017-12-28 |