52nd week of 2016 patent applcation highlights part 56 |
Patent application number | Title | Published |
20160379768 | RELAY ARCHITECTURE FOR TRANSFERRING FROM REDUNDANT POWER SOURCES - Automatic transfer switching apparatus and systems include a switching device including an input line, a sensor, and a parallel assembly of a solid-state relay and latching relay electrically connected with the input line. The solid-state relay is used to short the latching relay such that the latching relay can be opened and/or closed in an unloaded state while the input line is energized. | 2016-12-29 |
20160379769 | LOCKING DEVICE FOR OPERATING MECHANISM OF GAS INSULATED SWITCHGEAR - In some embodiments, a locking device for an operating mechanism of a gas insulated switchgear, capable of locking or unlocking operations of an operating mechanism of disconnecting switches and earthing switches of the gas insulated switchgear. | 2016-12-29 |
20160379770 | HIGH THERMAL EFFICIENCY ELECTRIC SWITCH AND METHOD FOR INTERRUPTING ELECTRIC CURRENT - The present invention relates to an electric switch comprising a first switch assembly ( | 2016-12-29 |
20160379771 | ELECTRONIC DEVICE FOR CONTROLLING HIGH-VOLTAGE WITH MULTIPLE LOW-VOLTAGE SWITCHES - An electronic device is disclosed for controlling a high-voltage power source with multiple low-voltage switches. The electronic device includes a low-voltage DC power supply that allows for low-voltage wiring and components to be used to control the high-voltage power source using multiple low-voltage switches. The electronic device includes a single pulse generator that generates a pulse signal upon activation of any one of the multiple switches. The pulse signal activates a bistable circuit controller that is coupled the a high-voltage electronic switch to control high-voltage power to the load. | 2016-12-29 |
20160379772 | KEYBOARD COMPRISING MULTIPLE STABILIZED TILE-SHAPED KEYS - The keyboard having a plurality of plate-shaped keys which are connected to actuators stabilizes the keys by all the keys and all the actuators being connected to a bending-elastic but tension-resistant band-like membrane. | 2016-12-29 |
20160379773 | NOVEL CONDUCTING STRUCTURE AND CONDUCTING METHOD FOR UPPER SHEET AND LOWER SHEET OF FILM BUTTON CIRCUIT - A novel conducting structure and conducting method for an upper sheet and a lower sheet of a film button circuit. A first upper sheet conducting layer and a second upper sheet conducting layer are coated in sequence on an upper sheet conducting contact point. A first lower sheet conducting layer and a second lower sheet conducting layer are coated in sequence on a lower sheet conducting contact point. The first upper sheet conducting layer, the second upper sheet conducting layer, the second lower sheet conducting layer and the first lower sheet conducting layer are overlapped in sequence, thereby forming a composite conducting layer that is slightly greater than a back glue layer in thickness. The present invention can simplify assembly processes and can improve the production efficiency. | 2016-12-29 |
20160379774 | KEYFRAME MODULE FOR AN INPUT DEVICE - System and methods for providing a keyframe module for a input device are disclosed. In an embodiment, the input device includes a keyframe having a key opening, and a key disposed within the key opening. The key includes a keycap having a bottom surface, a plurality of tabs that extend laterally from the bottom surface of the keycap, and a protrusion extending from the bottom surface of the keycap. A compressible dome structure is disposed underneath the protrusion, and a plate is coupled to the keyframe and disposed underneath the compressible dome structure. A plurality of openings is disposed within the plate, where a location of the plurality of openings corresponds to a location of the plurality of tabs such that one or more of the plurality of tabs pass through one or more of the plurality of openings in response to the depression of the key. | 2016-12-29 |
20160379775 | KEYBOARD ASSEMBLIES HAVING REDUCED THICKNESSES AND METHOD OF FORMING KEYBOARD ASSEMBLIES - Keyboard assemblies having reduced thicknesses and methods of forming the same. A keyboard assembly may include a printed circuit board (PCB) and a single membrane sheet adhered directly to the PCB. The single membrane sheet may substantially cover the PCB. The keyboard assembly may also include a group of dome switches coupled directly to the single membrane sheet. Another keyboard assembly may include a group of conductive pads and a group of membrane pads. Each of the group of membrane pads may be adhered directly to a corresponding one of the group of conductive pads. The keyboard assembly may also include a group of dome switches coupled directly to the membrane pads. Each of the group of dome switches may be coupled directly to a corresponding one of the group of membrane pads. | 2016-12-29 |
20160379776 | KEYBOARD FOR AN ELECTRONIC DEVICE - Particular embodiments described herein provide for a system that includes means for receiving a signal from a key, the signal indicating that the key has been activated and means for sending lateral haptic feedback to the key in response to the received signal that the key was activated. Additionally, the system may include a means for generating acoustic feedback in response to the received signal indicating that the key was activated and a means for generating visual feedback in response to the received signal indicating that the key was activated. | 2016-12-29 |
20160379777 | OPERATION DEVICE - The operation device includes ball sensors and a determination unit. Each of the ball sensors has a ball, whereof a portion is exposed from an opening provided in an operation surface, rotating in a first direction which is the direction of an operation performed on the operation surface, and a second direction which is a direction opposite to the first direction; a support rotatably supporting the ball, and a rotation sensor for detecting the rotation of the ball. The ball sensors are disposed so as to be arranged on the operation surface along the first direction. The determination unit determines the operations performed in the first direction and the second direction on the operation surface based on detection signals outputted from the rotation sensors of the of ball sensors. | 2016-12-29 |
20160379778 | Service Plug - This service plug ( | 2016-12-29 |
20160379779 | CONTACT CONTACTING STRUCTURE - Provided is a contact contacting structure that reliably prevents the development of arc discharge in a simple configuration regardless of the magnitude of electric energy accumulated between a pair of contacts that are connected and disconnected. An intermediate contact body disposed continuously with a first contact along a movement path of a second contact is formed from material with higher electric resistivity than the first contact in a shape such that the cross sectional area of a transverse section perpendicular to the movement path is gradually decreased in a separating direction along the movement path. | 2016-12-29 |
20160379780 | GAS CIRCUIT BREAKER - In a gas circuit breaker according to an embodiment, a container is filled with an arc extinguishing gas. A movable part housed in the container and includes a movable arc contact. The movable part is provided with an accumulation part for increasing pressure of the arc extinguishing gas. A counter part is housed in the container and includes a counter arc contact, an exhaust pipe, and a shield. The shield is disposed in the exhaust pipe in a state that a flow of the arc extinguishing gas inside the exhaust pipe is allowed. A nozzle is housed in the container and provided with a space. An arc discharge occurs between the movable arc contact and the counter arc contact in the space. The arc extinguishing gas having an increased pressure in the accumulation part flows into the space to extinguish the arc discharge and flows into the exhaust pipe. The shield has a first shield wall crossing the axial direction of the exhaust pipe. | 2016-12-29 |
20160379781 | Thermostat Having Safety Function - A thermostat having a safety function includes a constant temperature mechanism. The constant temperature mechanism includes a metallic lid, an insulation main body coupled to the metallic lid, a dual metallic plate, an insulation push rod leaning against the dual metallic plate, an elastic plate moveably leaning against the insulation push rod, a contact plate movably cooperating with the elastic plate, and two terminals for connecting with a circuit. A safety mechanism is provided between the two terminals of the constant temperature mechanism. The thermostat is compact in structure and has reliable functions and suitable for high power electric appliances to meet the demand of safety effectively. | 2016-12-29 |
20160379782 | CONTROL SYSTEM FOR A WIRELESS POWER SWITCH WITHOUT A NEUTRAL WIRE - A control system for a wireless power switch without a NEUTRAL wire comprises a wireless controlled power switch with both terminals connected between a LINE wire and a switch wire of a switch box without the NEUTRAL wire; a power acquiring device having two power input terminals respectively connected to the LINE wire and the switch wire of the switch box; and a wireless automation control device receiving an output voltage of the power acquiring device as the required power, the wireless automation control device controlling open or close of the wireless controlled power switch according to wireless control signal wirelessly. Specifically, a load device is connected between the switch wire and the NEUTRAL wire, and impedance between the two power input terminals of the power acquiring device is substantially larger than impedance of the load device. | 2016-12-29 |
20160379783 | GASKET, MAGNETIC SWITCH OF STARTER COMPRISING SAME, AND STARTER PROVIDED WITH MAGNETIC SWITCH - The present invention relates to a gasket, a magnetic switch of a starter including the same, and a starter including the magnetic switch, the gasket including: a membrane which carries out a sealing function and is made of a resin material having flexibility; and a membrane washer provided along the edge of the membrane in order to prevent bending of the membrane, wherein the membrane and the membrane washer are insert injected. Unlike prior art, the present invention can enhance the durability of the membrane by insert injection molding a hard membrane washer into the membrane having flexibility, can enhance a waterproofing performance by enabling the membrane to be firmly fixed to a plunger, and can enhance an assembly performance by enabling assembly through an automatic production line. | 2016-12-29 |
20160379784 | REED RELAY - A reed switch relay comprises a PCB base ( | 2016-12-29 |
20160379785 | Electromagnetic Relay - An electromagnetic relay is disclosed. The electromagnetic relay comprises a coil, a yoke having a yoke face, and an armature. The armature has an armature face facing the yoke face and movable, depending on a current through the coil, between an open position and a closed position in which the armature face is positioned closer to the yoke face, and an overlap disposed over a side surface of the yoke. A first distance between the side surface of the yoke and the overlap is smaller than a smallest second distance between the armature face and the yoke face in the open position. | 2016-12-29 |
20160379786 | ELECTRICAL SWITCH - An electrical switch for switching an electric current is disclosed. The electrical switch includes an electronic trip unit, embodied in a bipartite fashion. A first part of the trip unit is fixedly connected to the electrical switch and includes protection functions of the electrical switch. A second part of the trip unit is embodied mountably and detachably on the electrical switch and defines the protection functions enabled for the customer. | 2016-12-29 |
20160379787 | Visible Disconnect Switch Interlock Assembly - A visible disconnect switch (VDS) interlock assembly is provided. The VDS interlock assembly is movable between a CBA, first lockout position, wherein a CBA second contact assembly cannot move when a VDS second contact assembly is in a first position, and a VDS, second lockout position, wherein a VDS second contact assembly cannot move when the CBA second contact assembly is in a second position. Further, the VDS interlock assembly is placed in an open position in between where the CBA, first lockout position and the VDS, second lockout position; from the open position the VDS interlock assembly may be moved into one of the CBA, first lockout position or the VDS, second lockout position. | 2016-12-29 |
20160379788 | Trip Bar Stop - An operating mechanism including a number of biasing elements and a number of linkage members is provided. The linkage members are operatively coupled to each other and each are movable between a second configuration, an initial tripped configuration, a rebound configuration, and a final tripped configuration. The biasing elements are operatively coupled to the number of linkage members and bias the number of linkage members to the final, first configuration. A stop member is coupled to one of the linkage members. The stop member moves with the associated linkage member. The stop member is positioned to contact a stop surface when the linkage members are in the rebound configuration. Contact between the stop member and the stop surface substantially arrests the motion of the linkage members. | 2016-12-29 |
20160379789 | Circuit Breaker with Current Limiting and High Speed Fault Capability - A circuit breaker arraignment including at least two trip mechanisms the first trip mechanism acting to immediately trip to open contacts of the circuit breaker upon reaching a first threshold current level, and the second trip mechanism acting to trip to open the contacts once both a second current threshold is reached and a time delay has elapsed, the contacts moved by a linkage assembly that is held under mechanical advantage such that when acted on by one of the two trip mechanisms, the mechanical advantage is released to rapidly open the contacts. | 2016-12-29 |
20160379790 | A PROTECTIVE ELECTRONIC MODULE FOR AN HVDC CONVERTOR - An electronic module for protecting power semiconductor devices of an HVDC converter against high current surges and damaging electrical discharges includes a capacitor, a short circuit device, a movable portion, a short circuit portion and a spring element. The short circuit device is connected in parallel with the capacitor and has first and second busbars. The movable portion is connected to the first busbar and the short circuit portion is connected to the second busbar. The spring element is arranged between the movable portion and the short circuit portion. When a short circuit current flows through the first busbar, an electromagnetic force between the busbars causes the first busbar to repel the second busbar and move towards the short circuit portion. The latter provides a short circuit path connecting the first busbar to the second busbar short circuiting the capacitor and bypassing the power semiconductor devices of the HVDC converter. | 2016-12-29 |
20160379791 | BRIDGE ASSEMBLY - The present invention relates to a bridge assembly. The bridge assembly according to an exemplary embodiment of the present invention includes: a bridge configured to include a first leg fixed to an upper surface of a printed circuit board, a second leg fixed to the printed circuit board to be spaced apart from the first leg, and an elastic part connecting between the first leg and the second leg and applying an elastic force to any one of the first and second legs; and a cover configured to be positioned at an upper side of the bridge to receive the elastic part. | 2016-12-29 |
20160379792 | CATHODOLUMINESCENT DEVICE WITH IMPROVED EFFICIENCY - A cathodoluminescent device, including a luminescent layer having a first side, called the front side, that is intended to receive incident electrons, the luminescent layer being suitable for absorbing incident electrons and for emitting light radiation in response, wherein the front side of the luminescent layer is coated with a layer including electrically conductive nanowires. | 2016-12-29 |
20160379793 | BEAM FOCUSING AND ACCELERATING SYSTEM - A system for focusing and accelerating a beam of electrically charged particles, for example protons. The system comprises: a beam generator; a charge pulse generator; and a focusing and accelerating device comprising a body with a core. The body defines a charge path extending along the body and beam generator directs a beam of electrically charged particles through the core. The charge pulse generator simultaneously delivers charge pulses to the charge path. The charge path may be helical in shape. Movement of the charge pulse along the path creates an electric field that simultaneously accelerates and focuses the beam. | 2016-12-29 |
20160379794 | X-RAY GENERATING UNIT AND RADIOGRAPHIC APPARATUS - A radiographic apparatus including a target array and an X-ray detecting unit. The target array includes a plurality of targets and a forward shielding member. The forward shielding member includes a plurality of partitions. The X-ray detecting unit includes a detecting portion. The partitions each have sloping surfaces whose angles of inclination change along an array direction. | 2016-12-29 |
20160379795 | Charged Particle Beam Apparatus - An object of the invention is to provide a charged particle beam apparatus which can perform optimized adjustment of a focusing condition of a charged particle beam focused on a sample and optimized adjustment of an orbit of a charged particle emitted from the sample. In order to achieve the above-described object, there is provided a charged particle beam apparatus including a passage restriction member that partially restricts passage of a charged particle emitted from a sample, a first lens that is arranged between the passage restriction member and the sample, and that controls an orbit of the charged particle emitted from the sample, and a second lens that is arranged between the passage restriction member and the charged particle source, and that changes a focusing condition of the charged particle beam in accordance with a control condition of the first lens. | 2016-12-29 |
20160379796 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a processing chamber, a first electrode and a second electrode disposed to face each other, a high frequency power supply unit for applying a high frequency power to either the first electrode or the second electrode, a processing gas supply unit for supplying a processing gas to a processing space, and a main dielectric member provided at a substrate mounting portion on a main surface of the first electrode. A focus ring is attached to the first electrode to cover a peripheral portion of the main surface of the first electrode and a peripheral dielectric member is provided in a peripheral portion on the main surface of the first electrode so that an electrostatic capacitance per unit area applied between the first electrode and the focus ring is smaller than that applied between the first electrode and the substrate by the main dielectric member. | 2016-12-29 |
20160379797 | Charged Particle Beam Apparatus - Disclosed is a charged particle beam apparatus wherein charged particles emitted from a sample are efficiently acquired at a position as close as possible to the sample, said position being in the objective lens. This charged particle beam apparatus is provided with: a charged particle beam receiving surface that is provided with a scintillator that emits light by means of charged particles; a photodetector that detects light emitted from the scintillator; a mirror that guides, to the photodetector, the light emitted from the scintillator; and an objective lens for focusing the charged particle beam to a sample. A distance (Lsm) between the charged particle beam receiving surface and the mirror is longer than a distance (Lpm) between the photodetector and the mirror, and the charged particle beam receiving surface, the mirror, and the photodetector are stored in the objective lens. | 2016-12-29 |
20160379798 | Scanning Electron Microscope System, Pattern Measurement Method Using Same, and Scanning Electron Microscope - In order to allow detecting backscattered electrons (BSEs) generated from the bottom of a hole for determining whether a hole with a super high aspect ratio is opened or for inspecting and measuring the ratio of the top diameter to the bottom diameter of a hole, which are typified in 3D-NAND processes of opening a hole, a primary electron beam accelerated at a high accelerating voltage is applied to a sample. Backscattered electrons (BSEs) at a low angle (e.g. a zenith angle of five degrees or more) are detected. Thus, the bottom of a hole is observed using “penetrating BSEs” having been emitted from the bottom of the hole and penetrated the side wall. Using the characteristics in which a penetrating distance is relatively prolonged through a deep hole and the amount of penetrating BSEs is decreased to cause a dark image, a calibration curve expressing the relationship between a hole depth and the brightness is given to measure the hole depth. | 2016-12-29 |
20160379799 | TRIPLE MODE ELECTROSTATIC COLLIMATOR - A system includes a first electrode to receive an ion beam, a second electrode to receive the ion beam after passing through the first electrode, the first and second electrode forming an upstream gap defined by a convex surface on one of the first or second electrode and concave surface on the other electrode, a third electrode to receive the ion beam after passing through the second electrode, wherein the second and third electrode form a downstream gap defined by a convex surface on one of the second or third electrode and concave surface on the other electrode, wherein the second electrode has either two concave surfaces or two convex surfaces; and a voltage supply system to independently supply voltage signals to the first, second and third electrode, that accelerate and decelerate the ion beam as it passes through the first, second, and third electrode. | 2016-12-29 |
20160379800 | PLASMA ETCHING METHOD AND METHOD OF MANUFACTURING PATTERNED SUBSTRATE - When a mask pattern provided on a dielectric substrate is provided with a pattern area having a plurality of micro openings, and a non-pattern area other than the pattern area, in the case in which the dielectric substrate is mounted at a predetermined position in a substrate mounting structure portion, in the pattern area, the configuration of the substrate mounting structure portion is set such that an average dielectric constant between a surface of the dielectric substrate and a surface of a predetermined electrode of the substrate mounting structure portion is larger than an average dielectric constant in the non-pattern area, and the dielectric substrate is etched by mounting the dielectric substrate at the predetermined portion of the substrate mounting structure portion, and generating plasma under an atmosphere reduced in pressure compared with atmospheric pressure. | 2016-12-29 |
20160379801 | ROTATIONAL ANTENNA AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A rotational antenna and a semiconductor manufacturing device provided with the same are disclosed. The rotational antenna includes a plurality of coils connected in parallel to a high frequency power source and arranged at a regular interval around an axis in a symmetrical relationship with respect to the axis, wherein an electromagnetic field for generating inductively coupled plasma is uniformly formed when the coils are rotated about the axis. | 2016-12-29 |
20160379802 | APPARATUS FOR MONITORING VACUUM ULTRAVIOLET AND PLASMA PROCESS EQUIPMENT INCLUDING THE SAME - An apparatus for monitoring vacuum ultraviolet, the apparatus including a light controller including a slit, the slit to transmit plasma emission light emitted from a process chamber in which a plasma process is performed on a substrate; a light selector adjacent to the light controller, the light selector selectively to transmit light, having a predetermined wavelength band, of the plasma emission light passing through the slit; a light collector to concentrate the light selectively transmitted by the light selector; and a detector to detect the light concentrated by the light collector, the light selectively transmitted by the light selector being vacuum ultraviolet. | 2016-12-29 |
20160379803 | SELECTIVE REMOVAL OF BORON DOPED CARBON HARD MASK LAYERS - Systems and methods for processing a substrate include arranging a substrate including a film layer on a substrate support in a processing chamber. The film layer includes a boron doped carbon hard mask. A plasma gas mixture is supplied and includes molecular hydrogen, nitrogen trifluoride, and a gas selected from a group consisting of carbon dioxide and nitrous oxide. Plasma is struck in the processing chamber or supplied to the processing chamber for a predetermined stripping period. The plasma strips the film layer during the predetermined stripping period and the plasma is extinguished. | 2016-12-29 |
20160379804 | CONTROLLING ION ENERGY WITHIN A PLASMA CHAMBER - Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold. | 2016-12-29 |
20160379805 | PLASMA PROCESSING APPARATUS AND METHOD - A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring. | 2016-12-29 |
20160379806 | USE OF PLASMA-RESISTANT ATOMIC LAYER DEPOSITION COATINGS TO EXTEND THE LIFETIME OF POLYMER COMPONENTS IN ETCH CHAMBERS - In accordance with this disclosure, there are provided several inventions, including an apparatus and method for depositing plasma resistant coatings on polymer materials used in a plasma processing chamber. In a particular example, such a coating may be made on a portion of an electrostatic chuck, where the polymer material is a bead surrounding an adhesive between a chuck base and a ceramic top plate. | 2016-12-29 |
20160379807 | PLASMA ETCHING APPARATUS - An ICP plasma etching apparatus for etching a substrate includes at least one chamber, a substrate support positioned within the chamber, a plasma production device for producing a plasma for use in etching the substrate, and a protective structure which surrounds the substrate support so that, in use, a peripheral portion of the substrate is protected from unwanted deposition of material. The protective structure is arranged to be electrically biased and is formed from a metallic material so that metallic material can be sputtered from the protective structure onto an interior surface of the chamber to adhere particulate material to the interior surface. | 2016-12-29 |
20160379808 | VENTILATION SYSTEMS FOR USE WITH A PLASMA TREATMENT SYSTEM - A gas containment apparatus for use with an end effector including at least one plasma head includes at least one enclosing structure coupled to the end effector. The enclosing structure is configured to capture a gas produced by the at least one plasma head. The gas containment apparatus also includes a duct coupled to the at least one enclosing structure and configured to channel the gas from within the enclosing structure. | 2016-12-29 |
20160379809 | DETECTORS AND METHODS OF USING THEM - Certain embodiments described herein are directed to detectors and systems using them. In some examples, the detector can include a plurality of dynodes, in which one or more of the dynodes are coupled to an electrometer. In some instances, an analog signal from a non-saturated dynode is measured and cross-calibrated with a pulse count signal to extend the dynamic range of the detector. | 2016-12-29 |
20160379810 | Systems and Methods for Acquiring Data for Mass Spectrometry Images - Systems and methods are provided for maximizing the data acquired from a sample in a mass spectrometry imaging experiment. An ion source device is instructed to produce and transmit to a tandem mass spectrometer a plurality of ions for each location of two or more locations of a sample. A mass range is divided into two or more mass window widths. For each location of the two or more locations, the tandem mass spectrometer is instructed to fragment the plurality of ions received for each location using each mass window width of the two or more mass window widths and to analyze resulting product ions. A product ion spectrum is produced for each mass window width, and a plurality of product ion spectra are produced for each location of the two or more locations. | 2016-12-29 |
20160379811 | METHOD OF DETERMINING CELL CYCLE STAGE DISTRIBUTION OF CELLS - A method of determining a cell cycle stage distribution of cells includes the steps of providing a cell sample; pre-treating the cell sample with a solvent; mixing the pre-treated cell sample with a matrix solution to obtain a mixture solution; depositing the mixture solution on a sample plate; obtaining a mass spectrum analysis of the deposited mixture solution; and identifying at least two marker peaks from the mass spectrum analysis, wherein a ratio between the marker peaks provides information about a cell cycle stage distribution of the cell sample, wherein the mass spectrum analysis is a matrix-assisted laser desorption/ ionization time-of-flight mass spectrum test. | 2016-12-29 |
20160379812 | METHOD FOR MEASUREMENT OF ION EVENTS - A method of processing an input data stream including at least one data peak ( | 2016-12-29 |
20160379813 | Systems and Methods for Using Interleaving Window Widths in Tandem Mass Spectrometry - Systems and methods are provided for analyzing a sample using overlapping measured mass selection window widths. A mass range of a sample is divided into two or more target mass selection window widths using a processor. The two or more target widths can have the same width or variable widths. A tandem mass spectrometer is instructed to perform two or more fragmentation scans across the mass range using the processor. Each fragmentation scan of the two or more fragmentation scans includes a measured mass selection window width. The two or more measured widths of the two or more fragmentation scans can have the same width or variable widths. At least two of the two or more measured mass selection window widths overlap. The overlap in measured mass selection window widths corresponds to at least one target mass selection window width. | 2016-12-29 |
20160379814 | MOLECULAR DETECTION APPARATUS AND METHOD - According to one embodiment, a molecular detection apparatus includes an ionizer, a voltage applier, a separator and a detector. The ionizer attaches ions to a substance group including substances that differ in molecular weight to obtain an ionized substance group. The voltage applier applies a voltage to the ionized substance group to cause the ionized substance group to fly toward a detection surface within measurement space. The separator applies a voltage to a flying ionized substance group to bend a flight trajectory, removes a substance whose molecular weight is not more than a threshold from the flying ionized substance group, and extracts a substance whose molecular weight is more than the threshold as a measuring object. The detector performs a photo detection process to obtain a spectrum of the measuring object. | 2016-12-29 |
20160379815 | TRAPPING MULTIPLE IONS - Devices, methods, and systems for trapping multiple ions are described herein. One device includes two or more ovens wherein each oven includes a heating element and a cavity for emitting atoms of a particular atomic species from an atomic source substance, a substrate having a number of apertures that allow atoms emitted from the atomic source substance to exit the oven and enter an ion trapping area and wherein each oven is positioned at a different ion loading area within the ion trapping area, and a plurality of electrodes that can be charged and wherein the charge can be used to selectively control the movement of a particular ion from a particular loading area to a particular ion trap location. | 2016-12-29 |
20160379816 | TECHNIQUES TO ENGINEER NANOSCALE PATTERNED FEATURES USING IONS - A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension. | 2016-12-29 |
20160379817 | PERHYDROPOLYSILAZANE, COMPOSITION CONTAINING SAME, AND METHOD FOR FORMING SILICA FILM USING SAME - [Problem] To provide a perhydropolysilazane making it possible to form a siliceous film with minimal defects, and a curing composition comprising the perhydropolysilazane. | 2016-12-29 |
20160379818 | INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE - Insulating a via in a semiconductor substrate, including: applying a first dielectric layer to the semiconductor substrate; and applying a second dielectric layer to the semiconductor substrate, wherein the second dielectric layer is applied on the first dielectric layer, wherein the second dielectric layer is more conformal than the first dielectric layer. | 2016-12-29 |
20160379819 | INTERCONNECT INTEGRATION FOR SIDEWALL PORE SEAL AND VIA CLEANLINESS - A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition. | 2016-12-29 |
20160379820 | COMPOUND FINFET DEVICE INCLUDING OXIDIZED III-V FIN ISOLATOR - A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer. | 2016-12-29 |
20160379821 | METHOD TO PRODUCE PYRITE - A method for preparing a device having a film on a substrate is disclosed. In the method, a film is deposited on a substrate. The film includes a single-crystalline or poly-crystalline semiconducting thin film. The single-crystalline or poly-crystalline semiconducting thin film is formed by sequential evaporation of a first and a second element. One example device prepared by the method includes a silicon substrate and a film on the substrate, wherein the film includes semiconducting and single- or poly-crystalline pyrite as the compound. | 2016-12-29 |
20160379822 | DIRECT AND PRE-PATTERNED SYNTHESIS OF TWO-DIMENSIONAL HETEROSTRUCTURES - A method for growing a transition metal dichalcogenide on a substrate, the method including providing a growth substrate having a first side and a second side opposite the first side; providing a source substrate having a first side and a second side opposite the first side; depositing a transition metal oxide on at least a portion of the first side of the source substrate; combining the growth substrate with the source substrate such that the first side of the growth substrate contacts the transition metal oxide, the combining producing a substrate stack; exposing the substrate stack to a chalcogenide gas, whereby the transition metal oxide reacts with the chalcogenide gas to produce a layer of a transition metal dichalcogenide on at least a portion of the first side of the growth substrate; and removing the source substrate from the growth substrate having the layer of the transition metal dichalcogenide thereon. | 2016-12-29 |
20160379823 | TONE INVERTED DIRECTED SELF-ASSEMBLY (DSA) FIN PATTERNING - A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins. | 2016-12-29 |
20160379824 | LOW ROUGHNESS EUV LITHOGRAPHY - Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed. | 2016-12-29 |
20160379825 | SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME - A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film. | 2016-12-29 |
20160379826 | CAPPED ALD FILMS FOR DOPING FIN-SHAPED CHANNEL REGIONS OF 3-D IC TRANSISTORS - Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors. | 2016-12-29 |
20160379827 | METHOD FOR SELECTIVELY DEPOSITING A LAYER ON A THREE DIMENSIONAL STRUCTURE - A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion. | 2016-12-29 |
20160379828 | SILICON DOPING SOURCE FILMS BY ALD DEPOSITION - A conformal thermal ALD film having a combination of elements containing a dopant, such as boron (or phosphorus), and an oxide (or nitride), in intimate contact with a semiconductor substrate said combination having stable ambient and thermal annealing properties providing a shallow (less than ˜100 A) diffused (or recoil implanted) dopant, such as boron (or phosphorus) profile, into the underlying semiconductor substrate. | 2016-12-29 |
20160379829 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device. | 2016-12-29 |
20160379830 | MULTIPLE NANOSECOND LASER PULSE ANNEAL PROCESSES AND RESULTANT SEMICONDUCTOR STRUCTURE - Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material. | 2016-12-29 |
20160379831 | Multi-Gate Field Effect Transistors Having Oxygen-Scavenged Gate Stack - A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric. | 2016-12-29 |
20160379832 | FINFET SPACER ETCH WITH NO FIN RECESS AND NO GATE-SPACER PULL-DOWN - A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state. | 2016-12-29 |
20160379833 | METHOD FOR CLEANING PLASMA PROCESSING CHAMBER AND SUBSTRATE - A method for cleaning a plasma processing chamber is provided. The method includes introducing an organic gas into a plasma processing chamber. The organic gas includes an organic compound including carbon and hydrogen. The method includes generating an organic plasma by exciting the organic gas. The organic plasma reacts with metal compound residues over an interior surface of the plasma processing chamber to volatilize the metal compound residues into a gaseous metal compound. The method includes removing the gaseous metal compound from the plasma processing chamber. | 2016-12-29 |
20160379834 | ETCHING METHOD - Disclosed is a method for etching an etching target layer which contains silicon and is provided with a metal-containing mask thereon. The method includes: generating plasma of a first processing gas containing a fluorocarbon gas in a processing container that accommodates the etching target layer and the mask to form a fluorocarbon-containing deposit on the mask and the etching target layer; and generating plasma of a second processing gas containing an inert gas in the processing container to etch the etching target layer by radicals of the fluorocarbon contained in the deposit. A plurality of sequences, each including the generating the plasma of the first processing gas and the generating the plasma of the second processing gas, are performed. | 2016-12-29 |
20160379835 | GAS PHASE ETCHING SYSTEM AND METHOD - A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer. | 2016-12-29 |
20160379836 | METHOD FOR FORMING A PATTERN - A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions. | 2016-12-29 |
20160379837 | DIRECTED SELF-ASSEMBLY - The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls. | 2016-12-29 |
20160379838 | PROCESSING APPARATUS AND PROCESSING METHOD - A processing apparatus includes a rotary table that causes a workpiece to rotate around a rotary axis, a roller-shaped member that rotates on an axis orthogonal to the rotary axis of the rotary table, a vertical driving section that is driven in a direction of the rotary axis of the rotary table so as to bring the roller-shaped member and the workpiece into contact with each other, an ultraviolet ray irradiation source that irradiates a portion between the roller-shaped member and the workpiece with an ultraviolet ray, a polishing material that is supplied to the portion between the roller-shaped member and the workpiece, and a light scattering medium that is supplied to the portion between the roller-shaped member and the workpiece and scatters an ultraviolet ray from the ultraviolet ray irradiation source. | 2016-12-29 |
20160379839 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates. | 2016-12-29 |
20160379840 | CHEMICAL MECHANICAL POLISHING PAD AND METHOD OF MAKING SAME - A chemical mechanical polishing pad is provided, comprising: a chemical mechanical polishing layer having a polishing surface; wherein the chemical mechanical polishing layer is formed by combining (a) a poly side (P) liquid component, comprising: an amine-carbon dioxide adduct; and, at least one of a polyol, a polyamine and a alcohol amine; and (b) an iso side (I) liquid component, comprising: polyfunctional isocyanate; wherein the chemical mechanical polishing layer has a porosity of >10 vol %; wherein the chemical mechanical polishing layer has a Shore D hardness of <40; and, wherein the polishing surface is adapted for polishing a substrate. Methods of making and using the same are also provided. | 2016-12-29 |
20160379841 | ETCHING METHOD - Disclosed is a method for selectively etching a first region made of silicon oxide to a second region made of silicon nitride. The method includes: performing a first sequence once or more to etch the first region; and performing a second sequence once or more to further etch the first region. The first sequence includes: a first step of generating plasma of a processing gas containing a fluorocarbon to form a fluorocarbon-containing deposit on a workpiece; and a second step of etching the first region by radicals of the fluorocarbon. The second sequence includes: a third step of generating plasma of a processing gas containing a fluorocarbon gas to form a fluorocarbon-containing deposit on a workpiece; and a fourth step of generating plasma of a processing gas containing oxygen gas and an inert gas in the processing container. | 2016-12-29 |
20160379842 | GAS PHASE ETCH WITH CONTROLLABLE ETCH SELECTIVITY OF Si-CONTAINING ARC OR SILICON OXYNITRIDE TO DIFFERENT FILMS OR MASKS - A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer. | 2016-12-29 |
20160379843 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section. | 2016-12-29 |
20160379844 | TECHNIQUES AND APPARATUS FOR ANISOTROPIC METAL ETCHING - In one embodiment, a method for etching a copper layer disposed on a substrate includes directing reactive ions to the substrate when a mask that defines an exposed area and protected area is disposed on the copper layer, wherein an altered layer is generated in the exposed area comprising a chemically reactive material; and exposing the copper layer to a molecular species that is effective to react with the chemically reactive material so as to remove the altered layer. | 2016-12-29 |
20160379845 | SEMICONDUCTOR PACKAGES INCLUDING INTERPOSER AND METHODS OF MANUFACTURING THE SAME - A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided. | 2016-12-29 |
20160379846 | SEMICONDUCTOR PACKAGES SEPARATED USING A SACRIFICIAL MATERIAL - One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages. | 2016-12-29 |
20160379847 | Method for Fabricating a Semiconductor Chip Panel - A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips. | 2016-12-29 |
20160379848 | Substrate Processing Apparatus - A substrate processing apparatus includes: a processing chamber for processing a substrate; a substrate holding part whereon the substrate is placed; an elevating mechanism to move the substrate holding part vertically; a first gas supply system to supply a halogen-containing process gas to the substrate; a second gas supply system to supply an inert gas to the substrate; an exhaust unit to exhaust the process and inert gases; and a controller to control the elevating mechanism and the gas supply systems to: supply the process gas with a state where heights of the substrate holding part and exhaust unit are adjusted; and supply the inert gas to a center portion of the substrate from thereabove such that the inert gas flows radially from the center portion to a circumference of the substrate along a surface of the substrate and is exhausted out of the processing chamber through the exhaust unit. | 2016-12-29 |
20160379849 | DEVICE AND METHOD FOR SCRIBING A BOTTOM-SIDE OF A SUBSTRATE WHILE VIEWING THE TOP SIDE - A device includes a table surface defining a horizontal plane having an x-axis and a y-axis orthogonal to the x-axis and the x-axis and y-axis lie in the horizontal plane; a scribe mounted below the horizontal plane, the scribe further disposed to present at least a portion of the tip above the horizontal plane; a rail arranges parallel to the y-axis and movable in a direction parallel to the x-axis; a sample guide configured in relation to the horizontal plane so that the sample guide arranges parallel to the x-axis and movable in a direction parallel to the y-axis; a scribe stop guide configured in relation to the horizontal plane so that the scribe guide arranges parallel to the x-axis and movable in a direction parallel to the y-axis, whereby the sample guide moves independent of the scribe stop, the scribe stop further comprising a locking mechanism. | 2016-12-29 |
20160379850 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. A support structure is used to heat and/or cool at least the first carrier-substrate while the localized pressure is applied. | 2016-12-29 |
20160379851 | TEMPERATURE CONTROLLED SUBSTRATE PROCESSING - A semiconductor processing system includes a vacuum chamber, a gas source configured to supply a gas to the chamber, a platen having a top surface in the chamber to support a substrate, the platen including a conductive plate, a robot to transport the substrate onto and off of the platen, a first plurality of lamps disposed below the top surface of the platen to heat the platen, and an RF power source to generate a plasma in the chamber above the platen. | 2016-12-29 |
20160379852 | LEAK TOLERANT LIQUID COOLING SYSTEM EMPLOYING IMPROVED AIR PURGING MECHANISM - A cooling system for at least one thermal unit includes a tank assembly that includes: a sump chamber, a purge chamber that is located above the sump chamber, and a reservoir chamber that is located above the purge chamber; a cooling circuit that includes a pump, a heat exchanger, and conduits, the cooling circuit being configured to circulate a liquid coolant through the at least one thermal unit, the sump chamber, the pump, the heat exchanger, and the reservoir chamber; a first valve located externally of the tank assembly and configured such that, when the first valve is open, (i) the liquid coolant is flowable from the purge chamber to the sump chamber via the first valve, and (ii) air is simultaneously flowable from the sump chamber to the purge chamber via the first valve; and a second valve located externally of the tank assembly and configured such that, when the second valve is open, (i) the liquid coolant is flowable from the reservoir chamber to the purge chamber via the second valve, and (ii) air is simultaneously flowable from the purge chamber to the reservoir chamber via the second valve. | 2016-12-29 |
20160379853 | Electrostatic Chuck With LED Heating - An electrostatic chuck with LED heating is disclosed. The electrostatic chuck with LED heating comprises a first subassembly, which comprises a LED heater, and a second subassembly, which comprises an electrostatic chuck. The LED substrate heater subassembly includes a base having a recessed portion. A plurality of light emitting diodes (LEDs) is disposed within the recessed portion. The LEDs may be GaN or GaP LEDs, which emit light at a wavelength which is readily absorbed by silicon, thus efficiently and quickly heating the substrate. The second subassembly, which comprises an electrostatic chuck, is disposed on the LED substrate heater subassembly. The electrostatic chuck includes a top dielectric layer and an interior layer that are transparent at the wavelength emitted by the LEDs. One or more electrodes are disposed between the top dielectric layer and the interior layer to create the electrostatic force. | 2016-12-29 |
20160379854 | Vacuum Compatible LED Substrate Heater - A system for heating substrates within a chamber, which may be maintained at vacuum conditions, is disclosed. The LED substrate heater comprises a base having a recessed portion surrounded by sidewalls. A plurality of light emitting diodes (LEDs) are disposed within the recessed portion. The LEDs may be GaN or GaP LEDs, which emit light at a wavelength which is readily absorbed by silicon or a coating on the silicon, thus efficiently and quickly heating the substrate. A transparent window is disposed over the recessed portion, forming a sealed enclosure in which the LEDs are disposed. A sealing gasket may be disposed between the sidewalls and the window. | 2016-12-29 |
20160379855 | STORAGE UNIT, TRANSFER APPARATUS, AND SUBSTRATE PROCESSING SYSTEM - A storage unit of an embodiment includes a container, a rectifying plate, and an exhaust duct. The container provides a first space for storing a plurality of substrates therein, and a second space behind the first space. The rectifying plate is provided between the first and second spaces. The exhaust duct communicates with the second space. The rectifying plate has an effective region facing the first space. The effective region includes a first region and a second region. The first region faces a center of the first space. The second region extends on one side or both sides of the first region. In the first region, a plurality of through holes are formed to be distributed over the first region. The second region has a conductance lower than a conductance of the first region. | 2016-12-29 |
20160379856 | ETCHING METHOD AND PLASMA PROCESSING APPARATUS - An etching method is provided. In the etching method, a silicon oxide film is etched by using plasma in a first condition. In the first condition, a surface temperature of a substrate is controlled to have a temperature lower than −35 degrees C., and the plasma is generated from a hydrogen-containing gas and a fluorine-containing gas by using first radio frequency power output from a first radio frequency power source and second radio frequency power output from a second radio frequency power source. Next, the silicon oxide film is etched by using the plasma in a second condition. In the second condition, the output of the second radio frequency power from the second radio frequency power source is stopped. The silicon oxide film is etched by using the plasma alternately in the first condition and in the second condition multiple times. | 2016-12-29 |
20160379857 | VACUUM PROCESSING APPARATUS - The present invention provides a vacuum processing apparatus that includes gas supply means having a hard interlock of a pair of gas valves. | 2016-12-29 |
20160379858 | SUBSTRATE PROCESSING APPARATUS - A space needed to transfer a substrate container is decreased. A substrate processing apparatus includes a locating part where a substrate container accommodating a substrate is located; a driving unit configured to drive the locating part vertically; a transfer robot configured to transfer the substrate container; and a controller configured to control the driving unit and the transfer robot to move the locating part downward after the transfer robot moves to under the locating part to transfer the substrate container from the locating part to the transfer robot. | 2016-12-29 |
20160379859 | WAFER BOAT AND MANUFACTURING METHOD OF THE SAME - A wafer boat supporting a silicon wafer to be processed provides a sufficient anchor effect between a deposit film and a SiC coating film formed on a base material, and suppresses generation of particles due to peeling off of the deposit film. The vertical wafer boat includes a plurality of columns, being made of SiC-based material having a SiC coating film on a surface thereof, which contains shelf plate portions for supporting wafers, and a top plate and a bottom plate for fixing upper and lower ends of the columns, wherein a supporting plane which is in contact with an outer peripheral portion of the wafer is provided on an upper surface of the shelf plate portion, and a surface roughness Ra of a lower surface of the shelf plate increases toward a front side of the shelf plate portion from a rear side. | 2016-12-29 |
20160379860 | SiC EPITAXIAL WAFER AND METHOD FOR PRODUCING SAME, AND DEVICE FOR PRODUCING SiC EPITAXIAL WAFER - A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface of a SiC single crystal wafer while supplying a raw material gas into a chamber using a SiC epitaxial wafer manufacturing apparatus; and manufacturing a subsequent SiC epitaxial wafer after measuring a surface density of triangular defects originating from a material piece of an internal member of the chamber on the SiC epitaxial layer of the previously manufactured SiC epitaxial wafer. | 2016-12-29 |
20160379861 | Thermal Shield For Electrostatic Chuck - A thermal shield is disclosed that may be disposed between a heated electrostatic chuck and a base. The thermal shield comprises a thermal insulator, such as a polyimide film, having a thickness of between 1 and 5 mils. The polyimide film is coated on one side with a layer of reflective material, such as aluminum. The layer of reflective material may be between 30 and 100 nanometers. The thermal shield is disposed such that the layer of reflective material is closer to the chuck. Because of the thinness of the layer of reflective material, the thermal shield does not retain a significant amount of heat. Further, the temperature of the thermal shield remains far below the glass transition temperature of the polyimide film. | 2016-12-29 |
20160379862 | System and Method for Adhering a Semiconductive Wafer to a Mobile Electrostatic Carrier through a Vacuum - A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The MESC uses a plurality of electrostatic field generating (EFG) circuits to generate electrostatic fields across the MESC that allow the MESC to bond to compositional impurities within the semiconductive wafer. A layer of patterned material is superimposed across the bonding surface of MESC so that the cavities integrated into the layer of patterned material are able produce micro-vacuums that further adhere the semiconductive wafer to the MESC. | 2016-12-29 |
20160379863 | WAFER GRIPPER WITH NON-CONTACT SUPPORT PLATFORM - A wafer transport system includes a substantially horizontal non-contact support platform for supporting a wafer substantially horizontally at a substantially fixed vertical distance from the platform. A wafer gripping device includes wafer grippers to grip a surface of the wafer that is opposite the non-contact support platform. Each of the wafer grippers is mounted on a vertically flexible holder to enable the wafer gripper to adapt to a height of the wafer above the wafer gripping device while maintaining a substantial horizontal rigidity of the vertically flexible holder so as to prevent horizontal motion of the wafer relative to the wafer gripping device. | 2016-12-29 |
20160379864 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process. | 2016-12-29 |
20160379865 | METHOD FOR PREPARING SEMICONDUCTOR SUBSTRATE WITH SMOOTH EDGES - A method is provided for preparing a semiconductor substrate with smooth edges. The method includes: providing a first substrate and a second substrate; forming an insulating layer on a surface of the first substrate and/or the second substrate; bonding the first substrate and the second substrate by using the insulating layer as an intermediate layer; conducting a chamfering process on the bonded first substrate and insulating layer; and conducting edge polishing on the first substrate and insulating layer subjected to the chamfering process. | 2016-12-29 |
20160379866 | Isolated Semiconductor Layer Over Buried Isolation Layer - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 2016-12-29 |
20160379867 | SILICON GERMANIUM-ON-INSULATOR FINFET - A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration. | 2016-12-29 |