52nd week of 2016 patent applcation highlights part 64 |
Patent application number | Title | Published |
20160380568 | VARIABLE SPEED CONSTANT FREQUENCY POWER GENERATOR INCLUDING PERMANENT MAGNET EXCITER - A variable speed constant frequency (VSCF) power generator includes a rotating direct current (DC) power source, rotating multi-phase generator main field windings to generate a rotating alternating current (AC) power, and a rotating inverter configured to control alternating current (AC) generator field windings in response to output AC power generated by the VSCF power generator and DC power from the rotating DC power source. At least one generator main field sensor outputs a generator main field feedback signal based on the rotating AC power applied to the rotating multi-phase generator main field windings. Stationary multi-phase generator armature windings output constant voltage constant frequency AC power controlled by the rotating AC power. An electronic rotating power line communication (PLC) controller generates a control signal that adjusts the rotating AC power based on the rotating generator feedback signal, where the output AC power is controlled by adjusting the rotating AC power. | 2016-12-29 |
20160380569 | DEVICE AND METHOD FOR OPERATING AN ELECTRIC MACHINE - The present invention provides a device and a method for changing over an electric machine from the regular operating mode into the open-circuit mode. In order to avoid excessive increases in voltage and associated adverse effects on the electric machine and the other components, in particular batteries, a further control phase is introduced between the end of the regular operating mode and the freewheeling mode, during which further control phase the voltage at the terminals of the electric machine is continuously adjusted from the voltage previously set in the regular operating mode to the expected open-circuit voltage of the electric machine. | 2016-12-29 |
20160380570 | MOTOR CONTROL CENTER INCLUDING AN INTEGRATED DUAL BUS CONFIGURATION - A medium voltage drive and control system includes a dual bus configuration including an AC bus and a DC bus, a converter module connected to the AC bus and structured to receive AC power from the AC bus and convert the AC power to DC power, a DC link module coupled to the converter module and to the DC bus, wherein the DC link module is structured to store the DC power and provide the DC power to the DC bus, and a plurality of inverter modules, each inverter module being coupled to the DC bus and being structured to receive at least a portion of the DC power from the DC bus and convert the at least a portion of the DC power to quasi-sinusoidal AC output power for provision to a load associated with the inverter module. | 2016-12-29 |
20160380571 | MOTOR DRIVING DEVICE COMPRISING MEANS FOR DETECTING ABNORMAL HEAT GENERATION IN INITIAL CHARGING CIRCUIT - A motor driving device includes: a converter that converts AC power into DC power; a DC link capacitor provided for the DC link; an inverter that converts DC power into AC power for a motor; an initial charging circuit that charges the DC link capacitor; a potential difference determination unit that determines a potential difference between both ends of the initial charging circuit; a direct current detecting unit that detects direct current supplied to the initial charging circuit; an alternating current detecting unit that detects alternating current supplied to a motor; and an abnormality determination unit that determines that abnormal heat generation occurs in the initial charging circuit when the alternating current detecting unit detects alternating current and the direct current detecting unit detects direct current, in a case in which a potential difference occurs between both of the ends of the initial charging circuit. | 2016-12-29 |
20160380572 | SHIELDING STRUCTURE FOR POWER CONVERSION SYSTEM - An electromagnetic shielding structure includes a first shielding material disposed at a first location with respect to at least one radiation source and a second shielding material attached with the first shielding material by fastening means. The second shielding material is disposed at a second location with respect to the at least one electromagnetic radiation source so as to define a predetermined gap between the first shielding material and the second shielding material. The first shielding material shields at least part of first frequency electromagnetic radiations generated from the at least one electromagnetic radiation source and penetrating through the second shielding material and the predetermined gap. The second shielding material shields at least part of second frequency electromagnetic radiations generated from the at least one electromagnetic radiation source. | 2016-12-29 |
20160380573 | MOTOR CONTROL APPARATUS, MOTOR CONTROL SYSTEM, MOTOR CONTROL METHOD - A motor control apparatus for controlling driving of a motor includes an inverter which supplies power to a motor having a position detector, and circuitry which controls power conversion of the inverter based on at one or more predetermined control parameters, determine a type of the motor based on a signal received from the position detector of the motor, and control notification of setting confirmation of one or more of the predetermined control parameters in accordance with the type of the motor. | 2016-12-29 |
20160380574 | CHIP EVACUATION DEVICE DRIVEN BY SYNCHRONOUS MOTOR - In a chip evacuation device that evacuates chips produced in a machine tool to outside of the machine tool, a synchronous motor is used as a power source for the chip evacuation device. A load on the synchronous motor is monitored and a number of rotation or a direction of rotation of the synchronous motor is changed when it is determined that the load exceeds a preset threshold. | 2016-12-29 |
20160380575 | MOTOR DRIVE CONTROL DEVICE, COMPRESSOR, AIR-SENDING DEVICE, AND AIR-CONDITIONING APPARATUS - A motor drive control device includes a three-phase rectifier; a boosting circuit including a reactor, a switching element, and a backflow preventing element and boosts a direct-current bus voltage supplied from the three-phase rectifier; a smoothing capacitor; an inverter circuit; a boosting control unit; an inverter control unit; and a circuit protecting unit suppresses a ripple current flowing through the smoothing capacitor. In the circuit protecting unit, a correlation of an on-duty ratio of the switching element included in the boosting circuit, the output power of the inverter circuit, and an estimated ripple current are set. On the basis of the on-duty ratio of the switching element, output power of the inverter circuit, and the correlation, the circuit protecting unit determines an estimated ripple current flowing through the smoothing capacitor. When the estimated ripple current exceeds a preset threshold, the circuit protecting unit suppresses the ripple current. | 2016-12-29 |
20160380576 | CONTROL DEVICE - Object of the present disclosure is to improve accuracy of over-temperature protection of an electric motor. A control device controls an inverter main circuit for driving the electric motor. An electric power conversion circuit controller acquires DC voltage input to the inverter main circuit, output voltage of the inverter main circuit, motor amperage of current flowing through the electric motor, and motor frequencies indicating rotation rate of the electric motor. Based on at least one of the DC voltage, output voltage, motor amperage and motor frequencies, a motor loss estimator calculates a stator loss and rotor loss, each including fundamental and harmonic losses of the electric motor. Based on the inverter output voltage, stator loss and rotor loss, the electric power conversion circuit controller outputs an actual control value for control of the inverter main circuit. | 2016-12-29 |
20160380577 | Solar Energy Collector - A solar collector may include a frame for supporting a plurality of photovoltaic (PV) panels. The frame may be adapted to removably attach to a base. The solar collector may include a first panel assembly, including at least one of the plurality of PV panels, pivotally attached to the frame about a first axis. The solar collector may also include a second panel assembly, including at least one of the plurality of PV panels, pivotally attached to the first panel assembly. The second panel assembly may collectively move with the first panel assembly about the first axis and to pivot relative to the frame, and to pivot about a second axis that is substantially parallel to and radially offset from the first axis, to move between a deployed position and a retracted position. | 2016-12-29 |
20160380578 | SYSTEMS FOR ATTACHING MOUNTING RAILS ONTO PHOTOVOLTAIC MOUNTING POSTS - A system for connecting a photovoltaic mounting rail onto a mounting post using a connection system with a pair of interlocking grasps having interdigitated fingers that can be locked into the mounting rail when moved by a fastening system. | 2016-12-29 |
20160380579 | SOLAR TILE AND SOLAR TILE SYSTEM - A solar tile comprises a solar panel, a fixing substrate configured to support the solar panel, and a circuit module disposed on the fixing substrate. The fixing substrate comprises a metal frame and a rubber layer cladding the metal frame. The solar panel is fixedly stacked on the fixing substrate. The metal frame is capable of providing the solar tile with sufficient support strength, and the inner of the metal frame has great mutual restraint and containment forces, such that the metal frame has great impact resistance. Because the fixing substrate only comprises the metal frame and the rubber layer, the weight thereof is greatly reduced compared with a pure-metal structured fixing substrate. In addition, because the fixing substrate is made of less amount of metal material and has simple structure, the cost for manufacturing is reduced. | 2016-12-29 |
20160380580 | Large-Scale Space-Based Solar Power Station: Multi-Scale Modular Space Power - A space-based solar power station, a power generating satellite module and/or a method for collecting solar radiation and transmitting power generated using electrical current produced therefrom is provided. Each solar power station includes a plurality of satellite modules. The plurality of satellite modules each include a plurality of modular power generation tiles including a photovoltaic solar radiation collector, a power transmitter and associated control electronics. The power transmitters can be coordinated as a phased array and the power generated by the phased array is transmitted to one or more power receivers to achieve remote wireless power generation and delivery. Each satellite module may be formed of a compactable structure capable of reducing the payload area required to deliver the satellite module to an orbital formation within the space-based solar power station. | 2016-12-29 |
20160380581 | SOLAR PANEL SUPPORT FRAME AND SOLAR POWER DEVICE - There is provided a non-fix type solar panel support frame and a solar power device having improved resistance property against wind without decreasing workability. In the solar panel support frame, a first rail for supporting an upper end edge of the solar panel is composed of three first rail portions arranged in a lateral direction of the solar panel with gaps. The first rail portion includes: a weight-mounting plate on which a weight is mounted; a windbreak wall extended vertically from the weight-mounting plate for preventing wind from entering a rear surface side with respect to a light-receiving surface of the solar panel; and a panel fixing portion provided on an upper end edge of the windbreak wall. | 2016-12-29 |
20160380582 | PHOTOVOLTAIC POWER GENERATION APPARATUS - A photovoltaic power generation apparatus includes a support frame, on which solar cell modules are mounted such that neighboring solar cell modules are spaced apart from each other by a predetermined gap set in a lateral direction. A pair of guide rails is mounted on the support frame in a parallel manner at opposite sides of the solar cell modules. A cleaning unit reciprocates on the guide rails in a horizontal direction to clean upper surfaces of the solar cell modules by rotation. Interference frames are mounted on the support frame in the predetermined gaps or at opposite ends of the solar cell modules. The interference frames are arranged at a height at least equal to or higher than the upper surfaces of the solar cell modules such that the cleaning unit contacts the interference frames while rotating or reciprocating. | 2016-12-29 |
20160380583 | Solar Panel Efficacy-Method and Device - The disclosed technology describes methods and devices for generating electricity and heat using a parabolic solar panel which employs photo-voltaic and photo-thermal technology. Embodiments include forming a flexible substrate into a parabola. A plurality of flexible photo-voltaic cells is disposed in a grid pattern over the interior surface of the parabola. Photo-reflective mirrors are disposed on the parabola's interior surface in areas not occupied by photo-voltaic cells. A copper pipe is positioned to coincide with the parabola's focal line, so that light rays reflected off the parabola are focused on the copper pipe. Inflow and outflow tubes are attached to opposite ends of the copper pipe. Water or other heat absorbing liquid is circulated through the copper pipe where the liquid absorbs thermal energy of the sunrays reflected from the photo-reflective mirrors . The liquid can be directed to a device which converts the liquid's thermal energy to electricity. Electricity produced by the photo-voltaic cells is stored in a battery. | 2016-12-29 |
20160380584 | UNIVERSAL PHOTOVOLTAIC LAMINATE - A photovoltaic (PV) module can include a PV laminate, a frame coupled to a perimeter of the laminate, a junction box that includes a housing for an electrical connection between a plurality of PV cells of the laminate and a plurality of conductors, and an electronics enclosure coupled to the frame. In embodiments, the electronics enclosure can include electronic circuitry that is electrically coupled to the plurality of conductors and to another photovoltaic module. | 2016-12-29 |
20160380585 | TERMINAL FOR SOLAR JUNCTION BOX - A solar junction box for a solar panel includes a housing having a base and walls defining a cavity. The cavity extends along a primary axis and a secondary axis generally perpendicular to the primary axis. The base has a foil opening receiving a foil of the solar panel. A terminal is received in the cavity. The terminal has a protection device contact terminated to a protection device and a foil contact configured to be terminated to the foil. The foil contact is oriented within the cavity such that the foil contact is configured to be terminated to the foil when the foil extends into the foil opening along the primary axis and such that the foil contact is configured to be terminated to the foil when the foil extends into the foil opening along the secondary axis. | 2016-12-29 |
20160380586 | CABLE TERMINATION FOR SOLAR JUNCTION BOX - A solar junction box for a solar panel having at least one photovoltaic cell and a foil electrically connected to the at least one cell includes a housing having a base and walls defining a cavity. The base has at least one foil opening configured to receive the foil. A protection device is received in the cavity. A terminal is received in the cavity. The terminal has a diode contact terminated to the protection device. The terminal has a foil contact configured to be terminated to the foil. The terminal has a cable contact terminated to an electrical cable. The cable contact has insulation displacement contact (IDC) beams terminated to the electrical cable. | 2016-12-29 |
20160380587 | TERMINAL FOR SOLAR JUNCTION BOX - A solar junction box for a solar panel having at least one photovoltaic cell and a foil electrically connected to the at least one cell includes a housing having a base and walls defining a cavity. The housing is configured to be mounted to the solar panel. The base has at least one foil opening. A protection device is received in the cavity. A terminal is received in the cavity. The terminal has a protection device contact terminated to the protection device and a foil contact being crimped to the foil to electrically connect the terminal to the foil. | 2016-12-29 |
20160380588 | SOLAR JUNCTION BOX - A solar junction box for a solar panel includes a contact assembly having a base configured to be mounted to a solar panel and a terminal held by the base. The base has at least one foil opening configured to receive a foil. The terminal has a protection device contact configured to be terminated to a protection device. The terminal has a foil contact configured to be terminated to the foil. The terminal has a terminating contact configured to be electrically connected to a terminating assembly. The solar junction box includes a cover covering the contact assembly. The cover has walls defining a cavity receiving the terminal of the contact assembly. The walls are configured to be mounted directly to the solar panel. | 2016-12-29 |
20160380589 | GROUND FAULT DETECTION DEVICE - When a ground fault detection device detects a ground fault of a photovoltaic string, for example, while a power conditioner is in operation, a great current may be flowing in a switching section from the photovoltaic string, so that components resistant to a great current have been used for the switching section. A ground fault detection device includes a stop determination unit configured to determine whether a power converter for converting electric power from a solar battery is in stoppage, and a ground fault detector configured to detect a ground fault of the solar battery in a state where the solar battery and the power converter are electrically disconnected from each other by a disconnection unit arranged between the solar battery and the power converter when the stop determination unit determines that the power converter is in stoppage. | 2016-12-29 |
20160380590 | LOW-POWER BALANCED CRYSTAL OSCILLATOR - A circuit includes: first and second output terminals; a reference resonator coupled between the first and second output terminals; a cross-coupled oscillation unit coupled to the first and second output terminals; a first MOSFET diode coupled to the cross-coupled oscillation unit, the first MOSFET diode including a first transistor, a first resistor coupled between gate and drain terminals of the first transistor, and a first capacitor; a second MOSFET diode coupled to the cross-coupled oscillation unit, the second MOSFET diode including a second transistor, a second resistor coupled between gate and drain terminals of the second transistor, and a second capacitor cross coupled between the drain terminal of the second transistor and the gate terminal of the first transistor, wherein the first capacitor is cross coupled between the drain terminal of the first transistor and the gate terminal of the second transistor. | 2016-12-29 |
20160380591 | ELEMENT - An element which oscillates or detects terahertz waves includes a resonance unit including a differential negative resistance element, a first conductor, a second conductor, and a dielectric body, a bias circuit configured to supply a bias voltage to the differential negative resistance element, and a line configured to connect the resonance unit and the bias circuit to each other. The differential negative resistance element and the dielectric body are disposed between the first and second conductors. The line is a low impedance line in a frequency f | 2016-12-29 |
20160380592 | FRONT-END ARCHITECTURE FOR TRANSMITTER - Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency. | 2016-12-29 |
20160380593 | HARMONIC REJECTION TRANSLATIONAL FILTER - A harmonic-rejection translational filter includes: a first path, a second path and a signal combiner. The first path has a first translational filter that is driven by a plurality of first oscillation signals, and is arranged to generate a first output signal according to an input signal. The second path has a second translation filter that is driven by a plurality of second oscillation signals that are different from the first oscillation signals in phase. The second path is coupled to the first path and arranged to generate a second output signal according to the input signal. The signal combiner is coupled to the first path and the second path, and arranged to combine the first output signal and the second output signal to SIN generate a filtered signal. | 2016-12-29 |
20160380594 | POWER AMPLIFIER MODULES WITH HARMONIC TERMINATION CIRCUIT AND RELATED SYSTEMS, DEVICES, AND METHODS - One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to provide a radio frequency signal at an output, an output matching network coupled to the output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the radio frequency signal, and a harmonic termination circuit coupled to the output of the power amplifier. The power amplifier is included on a power amplifier die. The output matching network can include a first circuit element electrically connected to an output of the power amplifier by way of a pad on a top surface of a conductive trace, in which the top surface has an unplated portion between the pad the power amplifier die. The harmonic termination circuit can include a second circuit element. The first and second circuit elements can have separate electrical connections to the power amplifier die. Other embodiments of the module are provided along with related methods and components thereof. | 2016-12-29 |
20160380595 | APPARATUS AND METHOD FOR FILTER SETTLING CALIBRATION TO IMPROVE SPEED OF TRACKING AND CANCELLING OF DC OFFSET - Described is an apparatus which comprises: an amplifier to receive a reference voltage; and calibration logic which is operable to receive a first voltage and to provide the reference voltage to the amplifier, wherein the calibration logic is operable to generate a look-up table (LUT) that maps the first voltage to a drive current. | 2016-12-29 |
20160380596 | Sense Amplifier - A sense amplifier measures a state of a memory cell coupled to a sense node. The sense amplifier receives a control signal to enable the sense amplifier. The sense amplifier generates a voltage based on an amplifier current that is based on a sense current flowing through the sense node. The sense amplifier generates a feedback current based on the voltage to compensate variations of the sense current. The sense amplifier receives a reference control signal to enable a reference circuit to generate a reference current. The sense amplifier provides an output based on a result of comparing the sense current with the reference current, the output representing the state of the memory cell. | 2016-12-29 |
20160380597 | ENVELOPE TRACKING POWER CONVERTER - A tracking power converter for a radio frequency power amplifier includes a boost converter circuit, a switching network circuit, a filter circuit, and a controller circuit. The boost converter circuit provides a boosted voltage in response to a battery voltage. The switching network provides a switching signal in response to the boosted voltage, a first switch enable signal, a second switch enable signal, and a third switch enable signal. The filter circuit provides a power converter output voltage in response to the switching signal. The controller circuit provides the first switch enable signal, the second switch enable signal, and the third switch enable signal in response to a predetermined reference voltage, the switching voltage, the boosted voltage, and the battery voltage. | 2016-12-29 |
20160380598 | PSEUDO-RANDOM CHOPPER AMPLIFIER - A chopper stabilized amplifier that utilizes a multi-frequency chopping signal to reduce chopping artifacts. By utilizing a multi-frequency chopping signal, the amplifier DC offset and flicker noise are translated to the higher chopping frequencies but are also smeared, or spread out in frequency and consequently lowered in amplitude. This lower amplitude signal allows for less stringent filtering requirements. | 2016-12-29 |
20160380599 | DC BIAS CIRCUIT AND THE RADIO FREQUENCY RECEIVER CIRCUIT USING THE SAME - The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor. | 2016-12-29 |
20160380600 | BOOSTRAP CLASS-D WIDEBAND RF POWER AMPLIFIER - A high-power, high-frequency radio frequency power amplifier includes an output stage and a single-phase driver. The output stage is arranged in a Class-D amplifier configuration and includes a first depletion mode field effect transistor (FET), a second depletion mode FET, and a bootstrap path that couples the output of the output stage to the gate of the second FET. The first and second depletion mode FETs are switched out-of-phase and between fully-ON and fully-OFF states, under the direction of the single-phase driver. The single-phase driver directly controls the ON/OFF state of the first depletion mode FET and provides a discharge path through which the input gate capacitor of the second depletion mode FET in the output stage can discharge to turn OFF the second depletion mode FET. The bootstrap path provides a current path through which the input gate capacitor of the second depletion mode FET can charge to turn the second depletion mode FET ON. | 2016-12-29 |
20160380601 | Multimode Operation for Differential Power Amplifiers - An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier. | 2016-12-29 |
20160380602 | POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS - One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof. | 2016-12-29 |
20160380603 | FLIP-CHIP AMPLIFIER WITH TERMINATION CIRCUIT - Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity. | 2016-12-29 |
20160380604 | TRANSFORMER BASED DUPLEXER - A tunable transformer based duplexer (TTBD) comprising a first antenna port and a second antenna port. The TTBD further comprises a first winding coupled between a transmitting port and the first antenna port, wherein the first antenna port is configured to receive a first signal; a second winding coupled between the transmitting port and the second antenna port, wherein the second antenna port is configured to receive a second signal. Further, the TTBD comprises a receiving amplifier comprising at least one input and at least one output. The TTBD also comprises a third winding comprising a first terminal and a second terminal. The third winding comprises a first inductance and is coupled to the at least one output of the amplifier circuit. A first coupling is formed between the first winding and the third winding and a second coupling is formed between the second winding and the third winding. The TTBD further comprises a tunable capacitance coupled between the first terminal and the second terminal of the third winding. The tunable capacitance and the first inductance together form a band-pass filter. | 2016-12-29 |
20160380605 | SAW DEVICE MANUFACTURING METHOD - A SAW device wafer has a crystal substrate having a front side partitioned into a plurality of regions by a plurality of crossing division lines, a pair of comblike electrodes formed in each region defined on the front side of the crystal substrate by the division lines, and a cover layer formed of resin for covering the whole of the front side of the crystal substrate. The SAW device is manufactured by forming a laser processed groove on the cover layer along each division line, the laser processed groove having a depth not reaching the crystal substrate, forming a modified layer inside the crystal substrate along each division line, and applying an external force to the SAW device wafer, thereby dividing the SAW device wafer along each division line to obtain the plural SAW devices. | 2016-12-29 |
20160380606 | VERTICAL MAGNETIC BARRIER FOR INTEGRATED ELECTRONIC MODULE - An integrated electronic component assembly can include an electrically-conductive structure comprising two or more electrically-conductive terminals accessible on an exterior of the integrated electronic component assembly, a first component attachment region for a first component within the integrated electronic component assembly, and a second component attachment region for a second component within the integrated electronic component assembly. The integrated electronic component assembly can include an electrically-conductive magnetically-permeable shield coupled to or defined by the electrically-conductive structure, the electrically-conductive magnetically-permeable shield located between the first and second component attachment regions, including a portion extending in a direction out of a plane defined by the first and second component attachment regions, to suppress magnetic coupling between the first and second components. | 2016-12-29 |
20160380607 | SIGNAL INTERCONNECT WITH HIGH PASS FILTER - A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency. | 2016-12-29 |
20160380608 | MULTIPLEXERS HAVING HYBRID CIRCUITS WITH RESONATORS - Multiplexers having hybrid circuits with resonators. In some embodiments, a multiplexer for processing radio-frequency signals can include a plurality of nodes, a common node, and a signal path implemented between each of the plurality of nodes and the common node. Each signal path can include a filter, and each of at least some of the signal paths can further include a resonator coupled with the corresponding filter. A signal path with the resonator provides a sharper notch profile for a radio-frequency signal than a signal path without the resonator. | 2016-12-29 |
20160380609 | ALTERNATING CURRENT (AC) COUPLER FOR WIDEBAND AC SIGNALS AND RELATED METHODS - An AC coupler for transmitting high-frequency components of a wideband signal includes a signal conductor and a shielding structure arranged as a transmission line. The signal conductor includes a conductive element and a capacitor configured to block direct current (DC) components of the wideband signal while transmitting high-frequency alternating current (AC) components of the wideband signal. The shielding structure is configured for conducting at least the AC components of the wideband signal while confining electric fields and currents in the shielding structure substantially to a region proximate to the signal conductor. The shielding structure has a width substantially greater than a width of the signal conductor. The difference between the shielding structure width and the signal conductor width may be substantially greater than an offset distance between the signal conductor and the shielding structure. | 2016-12-29 |
20160380610 | VOLTAGE REDUCTION CIRCUIT - In one embodiment, the invention can be an impedance matching network including an input configured to operably couple to a radio frequency (RF) source; an output configured to operably couple to a load; a first variable capacitor; a second variable capacitor; and a third capacitor in series with the second variable capacitor and reducing a voltage on the second variable capacitor. | 2016-12-29 |
20160380611 | ELASTIC WAVE DEVICE - An elastic wave device includes a support substrate and a laminated film disposed on the support substrate. A portion of the laminated film is removed in a region outside a region in which an interdigital transducer electrode is disposed and below a region to which an external connection terminal is joined. An insulating layer is disposed in at least a portion of the region in which the portion of the laminated film is removed. A support layer is disposed on the insulating layer so as to surround the region in which the interdigital transducer electrode is disposed. A main component of a material of which the support layer is made is about 50% or more identical to a main component of a material of which the insulating layer is made. A cover is secured to the support layer to seal a cavity defined by the support layer. | 2016-12-29 |
20160380612 | CRYSTAL VIBRATION DEVICE - Provided is a crystal vibration device in which it is difficult to transfer heat to a temperature-sensitive element and a crystal vibrator. A crystal vibration device | 2016-12-29 |
20160380613 | ELASTIC WAVE DEVICE - An elastic wave device includes a piezoelectric substrate, first and second IDT electrodes on a first main surface, and electrode lands each connected to one of the first and second IDT electrodes. First and second side portions extend in a direction perpendicular or substantially perpendicular to a polarization axis direction and to a direction normal to the piezoelectric substrate. The length of the piezoelectric substrate along the polarization axis direction at the first side portion is shorter than that at the second side portion. The first IDT electrode is closer to the first side portion than the second IDT electrode. The electrode lands include a first electrode land connected to the first busbar of the first IDT electrode without having the second IDT electrode interposed therebetween, and a second electrode land being at the same potential as the first busbar of the first IDT electrode. | 2016-12-29 |
20160380614 | SAW RESONATOR WITH RESONANT CAVITIES - A surface acoustic wave (SAW) resonator is provided with reduced rattling at frequencies lower than the resonance value. The SAW resonator includes an interdigital transducer (IDT) on a piezoelectric substrate. The IDT includes a first set of interdigital electrodes distributed between and parallel to the first end of the | 2016-12-29 |
20160380615 | LADDER-TYPE FILTER, DUPLEXER, AND MODULE - A ladder-type filter includes: one or more series resonators connected in series between an input terminal and an output terminal; one or more parallel resonators connected in parallel between the input terminal and the output terminal; divided parallel resonators formed by serially dividing at least one parallel resonator of the one or more parallel resonators; and an inductor of which a first end is coupled to a first node located in a path from the input terminal to the output terminal through the one or more series resonators, and of which a second end is coupled to a second node located between the divided parallel resonators. | 2016-12-29 |
20160380616 | SURFACE ACOUSTIC WAVE FILTER - A longitudinally coupled resonator type surface acoustic wave filter includes a high-acoustic-velocity member, a low-acoustic-velocity film provided on the high-acoustic-velocity member, a piezoelectric film provided on the low-acoustic-velocity film, a plurality of interdigital transducers provided on the piezoelectric film and along a propagation direction of a surface acoustic wave and each including a plurality of electrode fingers, and reflectors arranged such that the interdigital transducers are interposed therebetween from both sides in the propagation direction of the surface acoustic wave. An electrode finger pitch is uniform or substantially uniform in each of the interdigital transducers. When a wavelength determined by the electrode finger pitch in the reflector is defined as λ, an inter-electrode finger center distance that is an interval between each of the interdigital transducers and the interdigital transducer adjacent thereto is not shorter than about 0.25λ and not longer than about 0.37λ. | 2016-12-29 |
20160380617 | ELASTIC WAVE DEVICE - An elastic wave device includes a piezoelectric substrate, first and second IDT electrodes disposed on a first main surface, and bumps each connected to one of the first and second IDT electrodes. First and second side portions extend in a direction perpendicular or substantially perpendicular to the polarization axis direction and to a direction normal to the piezoelectric substrate. The length of the piezoelectric substrate along the polarization axis direction at the first side portion is shorter than that at the second side portion. The first IDT electrode is located at a position closer to the first side portion than the second IDT electrode. The bumps include three or more first side bumps including first and second bumps that sandwich the first IDT electrode therebetween. The distance between the first and second bumps is the smallest distance among the distances between adjacent bumps of the first side bumps. | 2016-12-29 |
20160380618 | FEEDFORWARD FILTER USING TRANSLATIONAL FILTER - Described in embodiments herein are techniques for realizing filters having a variety of frequency responses, such as multiple pass-bands, high out-of-band rejection, without complicated designs. In accordance with an embodiment, a feedforward filter includes a first path, at least one second path and a signal combiner. The first path has a first translational filter, and employed for providing a first frequency response and generating a first output in response to an input signal based on the first frequency response. The at least one second path has a second translational filter and is coupled to the first path. The at least one second path is employed for providing a second frequency response that is different from the first frequency response to the input signal, and generating at least one second output in response to the input signal based on the second frequency response. The signal combiner is coupled to the first path and the second path, and employed for combining the first output and the at least one second output to generate a filtered signal. | 2016-12-29 |
20160380619 | CLOCK GENERATION CIRCUIT THAT TRACKS CRITICAL PATH ACROSS PROCESS, VOLTAGE AND TEMPERATURE VARIATION - Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal. | 2016-12-29 |
20160380620 | Signal Generation and Waveform Shaping - Measures, including apparatus, methods and computer program products, for generating an output signal with a defined waveform shape are provided. A plurality of switched inductor arrangements are each connected in parallel to generate a combined output signal. Each of the switched inductor arrangements are selectively enabled, wherein the number of enabled switched inductor arrangements is varied to define a waveform shape of the combined output signal. | 2016-12-29 |
20160380621 | COMPACT HIGH VOLTAGE RF GENERATOR USING A SELF-RESONANT INDUCTOR - RF generators including active devices driving series resonant circuits are described. The series resonant circuits include a self-resonant dual inductor. The RF generators can be used to drive capacitive loads. | 2016-12-29 |
20160380622 | LATCHED COMPARATOR CIRCUIT - Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals. | 2016-12-29 |
20160380623 | State Change Stabilization in a Phase Shifter/Attenuator Circuit - An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits. | 2016-12-29 |
20160380624 | DELAY CELL IN A STANDARD CELL LIBRARY - A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal. | 2016-12-29 |
20160380625 | POWER ELECTRONIC DEVICE ASSEMBLY FOR PREVENTING PARASITIC SWITCHING-ON OF FEEDER CIRCUIT-BREAKER - Disclosed herein is a power electronic device assembly for preventing parasitic switching-on of a feeder circuit breaker. The assembly includes a logic circuit, a power switch with an input and a reference leg, and a driver circuit which drives the power switch. The driver circuit includes a drive unit and a short circuit having a safety function. When the input of the power switch is not operated, the power switch is short-circuited by the reference leg so that the potential of the input decreases below a switching-on threshold. An additional wire connection device is disposed between the driver circuit and the power switch and configured such that when no or excessively small amount of supply voltage is applied, the input of the power switch is short-circuited or is coupled to a safety potential at which discharge is secured, whereby discharge of parasitic charge current is secured. | 2016-12-29 |
20160380626 | DEVICES WITH SIGNAL CHARACTERISTIC DEPENDENT CONTROL CIRCUITRY AND METHODS OF OPERATION THEREFOR - An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device. | 2016-12-29 |
20160380627 | INSULATED GATE DEVICE DISCHARGING - A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided. The inductive circuit is coupled to the gate of the switching device and further coupled to receive the charging voltage such that application of the charging voltage to the inductive circuit is with a polarity that induces a first current to flow through the inductor in a direction corresponding to charge moving away from the gate and such that discontinuation of the application of the charging voltage to the inductive circuit induces a second current flowing through the inductor in the direction corresponding to charge moving away from the gate such that the second current discharges the gate of the switching device. Faster turn off of the switching device is thus made possible and is synchronized to the discontinuation of the charging voltage. | 2016-12-29 |
20160380628 | Keyboard Assembly - A keyboard assembly includes a plurality keycaps, a plurality of sensor units and a control unit. The sensor units correspond respectively to the keycaps, and each of the sensor units is to output a pressure signal indicating magnitude of a pressure applied to a corresponding keycap. The control unit is configured to receive the pressure signal, and to determine a current repetition rate according to the pressure signal. When one keycap is depressed, the control unit repeatedly outputs a key code corresponding to the keycap at the current repetition rate while the keycap was depressed, and outputs the key code once while the keycap was not depressed. | 2016-12-29 |
20160380629 | SCALABLE CROSSBAR APPARATUS AND METHOD FOR ARRANGING CROSSBAR CIRCUITS - Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects. | 2016-12-29 |
20160380630 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor. | 2016-12-29 |
20160380631 | LOGIC CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor. | 2016-12-29 |
20160380632 | VOLTAGE GENERATOR WITH CHARGE PUMP AND RELATED METHODS AND APPARATUS - Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage. | 2016-12-29 |
20160380633 | SIGNAL CONVERSION - A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal. | 2016-12-29 |
20160380634 | PRINTED LOGIC GATE - An additively manufactured apparatus having a gas filled sealed cavity containing at least two additively manufactured cathodes and an additively manufactured anode spaced from the cathodes such that a continuous electric discharge of the gas stimulated between at least one of the cathodes and the anode provides a Boolean function output at the anode corresponding to electrical input signals at two of the cathodes. | 2016-12-29 |
20160380635 | COMPUTER ARCHITECTURE USING RAPIDLY RECONFIGURABLE CIRCUITS AND HIGH-BANDWIDTH MEMORY INTERFACES - A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions. | 2016-12-29 |
20160380636 | DRIVING THE COMMON-MODE OF A JOSEPHSON PARAMETRIC CONVERTER USING A THREE-PORT POWER DIVIDER - An on-chip Josephson parametric converter is provided. The on-chip Josephson parametric converter includes a Josephson ring modulator. The on-chip Josephson parametric converter further includes a lossless power divider, coupled to the Josephson ring modulator, having a single input port and two output ports for receiving a pump drive signal via the single input port, splitting the pump drive signal symmetrically into two signals that are equal in amplitude and phase, and outputting each of the two signals from a respective one of the two output ports. The pump drive signal excites a common mode of the on-chip Josephson parametric converter. | 2016-12-29 |
20160380637 | TEMPERATURE STABILIZATION OF AN ON-CHIP TEMPERATURE-SENSITIVE ELEMENT - Disclosed is an integrated circuit (IC) chip incorporating a temperature-sensitive element and temperature stabilization circuitry for ensuring that the temperature of the temperature-sensitive element (TSE) remains essentially constant. The IC chip comprises a temperature-sensitive element and, within at least one region adjacent to the temperature-sensitive element, a first circuit that radiates a first heat amount to the TSE and a second circuit that radiates a second heat amount to the TSE. The second circuit senses changes in a first current amount in the first circuit and, thereby changes in the first heat amount. In response to those changes, the second circuit also automatically adjusts a second current amount in the second circuit and, thereby the second heat amount in order to ensure that the total heat amount radiated by the first circuit and the second circuit, in combination, to the TSE remains constant. Also disclosed is an associated method. | 2016-12-29 |
20160380638 | CDR CONTROL CIRCUIT, CDR CIRCUIT, AND CDR CONTROL METHOD - A CDR control circuit detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit includes a change detection circuit that detects an over-change in the phase shift; and a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein during the predetermined period of time, the phase control data is generated based on the phase shift before change. | 2016-12-29 |
20160380639 | PHASE LOCK METHOD - A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal. | 2016-12-29 |
20160380640 | FREQUENCY TUNING AND/OR FREQUENCY TRACKING OF A MECHANICAL SYSTEM WITH LOW SENSITIVITY TO ELECTRICAL FEEDTHROUGH - An apparatus and method for frequency tuning/tracking between an electrical subsystem and a mechanical transducer subsystem is presented. An electromechanical transducer generates acoustic pulses as it is driven by a transmit signal from an electrical subsystem. As the transmit signal goes inactive, the settling behavior of the transducer is registered from which the difference in frequency between the resonance of the electromechanical transducer and the transmit signal frequency is determined and utilized for locking the electrical subsystem to the mechanical transducer subsystem by either tuning operating frequency of the electrical subsystem, or the mechanical transducer, to keep them matched (locked). | 2016-12-29 |
20160380641 | ELECTRONIC CIRCUIT - An electronic circuit includes an oscillator configured to generate an oscillating signal having a cycle responsive to an input signal, a voltage detector configured to produce a detection signal responsive to a power supply voltage, a frequency divider configured to generate a frequency-divided signal obtained by dividing a frequency of the oscillating signal by a frequency-division ratio responsive to the detection signal, and an adder configured to obtain a sum of a first signal and a second signal and to supply a signal responsive to the sum to the oscillator as the input signal, the first signal being responsive to a difference in phase between the frequency-divided signal and a reference signal, and the second signal being responsive to the detection signal. | 2016-12-29 |
20160380642 | DIVISOR CONTROL CIRCUIT, FRACTIONAL FREQUENCY DIVISION DEVICE, FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIS METHOD - A divisor control circuit allows a frequency divider to have a fractional divisor. The divisor control circuit includes: a multiplexer, arranged to select one of a first clock signal and a second clock signal as a multiplexed signal according to a selection signal, and accordingly provide the multiplexed signal to the frequency divider, wherein there is a phase difference between the first clock signal and the second clock signal; and a selection signal generation circuit, coupled to the multiplexer, arranged to generate the selection signal according to a frequency-divided signal outputted by the frequency divider. The multiplexer alternately selects the first clock signal and the second clock signal as the multiplexed signal during a period of the frequency-divided signal. | 2016-12-29 |
20160380643 | Reducing Distortion In An Analog-To-Digital Converter - In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value. | 2016-12-29 |
20160380644 | TELESCOPIC AMPLIFIER WITH IMPROVED COMMON MODE SETTLING - Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed. | 2016-12-29 |
20160380645 | CIRCUIT AND METHOD - Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input. | 2016-12-29 |
20160380646 | APPARATUS FOR OVERLOAD RECOVERY OF AN INTEGRATOR IN A SIGMA-DELTA MODULATOR - Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output. | 2016-12-29 |
20160380647 | APPARATUS AND METHOD FOR WIRED DATA COMMUNICATION - The present disclosure describes a wired communication device having media access control (MAC) circuitry and physical layer (PHY) circuitry. The MAC circuitry frames one or more data packets in accordance with a wired communication standard or protocol to provide one or more data frames. The one or more data frames include one or more packets that are separated by interpacket gaps (IPGs). The MAC circuitry selectively choses a duration of the IPGs to maintain an average IPG duration. The PHY circuitry encodes the one or more data frames in accordance with a line coding scheme that is efficiently represents different possible combinations for types of characters present in the one or more data frames. | 2016-12-29 |
20160380648 | OPTIMIZED CODE TABLE SIGNALING FOR AUTHENTICATION TO A NETWORK AND INFORMATION SYSTEM - In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed. | 2016-12-29 |
20160380649 | HARDWARE DATA COMPRESSOR USING DYNAMIC HASH ALGORITHM BASED ON INPUT BLOCK TYPE - A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block. | 2016-12-29 |
20160380650 | FLEXIBLE ERASURE CODING WITH ENHANCED LOCAL PROTECTION GROUP STRUCTURES - In various embodiments, methods and systems for erasure coding with enhanced local protection groups are provided. An erasure coding scheme can be defined based on a Vertical Local Reconstruction Code (VLRC) that achieves high storage efficiency by combining the Local Reconstruction Code and conventional erasure coding, where the local reconstruction code (LRC) is carefully laid out across zones. Thus, when a zone is down, remaining fragments form an appropriate LRC. Further, an inter-zone erasure coding scheme—Zone Local Reconstruction Code (ZZG-2 code)—is provided having both local reconstruction within every zone and a-of-b recovery property across zones. An inter-zone adaptive erasure coding (uber code) scheme is provided, the uber code is configurable to produce near optimal performance in different environments characterized by intra and inter-zone bandwidth and machine failure rates. It is contemplated that embodiments described herein include functionality for recognizing correctable patterns and decoding techniques for coding schemes. | 2016-12-29 |
20160380651 | MULTIPLE ECC CHECKING MECHANISM WITH MULTI-BIT HARD AND SOFT ERROR CORRECTION CAPABILITY - Embodiments of the inventive concept include a system and method for correcting multi-bit errors. A data vector and corresponding check vector can be stored. Error correcting circuitry can be used to identify which bits in the data vector, if any, are in error. Using information from a fault information storage, a correction vector can also be applied to the data vector to generate an alternate data vector. Error correcting circuitry can be used to identify which bits in the alternate data vector, if any, are in error. A final data vector can then be generated based on the data vector, the alternate data vector, and the results of the error correcting circuitries, which can then be returned as the read data vector. | 2016-12-29 |
20160380652 | POWER DETECTION OF INDIVIDUAL CARRIER OF AGGREGATED CARRIER - Aspects of this disclosure relate to detecting power associated with an individual carrier of a carrier aggregated signal. In an embodiment, a carrier aggregation system includes radio frequency (RF) sources, a transmission output, and a directional coupler. The RF sources, such as power amplifiers, can each be associated with a separate carrier. The transmission output can provide a carrier aggregated signal that includes an aggregation of the separate carriers associated with the RF sources. The directional coupler can provide an indication of RF power of one of the separate carriers. | 2016-12-29 |
20160380653 | ENERGY EFFICIENT POLYNOMIAL KERNEL GENERATION IN FULL-DUPLEX RADIO COMMUNICATION - A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders. | 2016-12-29 |
20160380654 | METHODS AND APPARATUS FOR DATA COMMUNICATION USING BANDWIDTH MODULATION - Methods and apparatus to determine a level of inherent jitter for signals from a transmitter and a receiver, and modulate information onto a signal transmitted by the transmitter by using spot jitter (with bandwidth and center frequency modulation) and/or pulse width jitter in a region outside of a data region with inherent jitter to carry communication between systems. | 2016-12-29 |
20160380655 | DIGITAL RF RECEIVER POWER SAVING WITH SIGNAL QUALITY DEPENDENT WORD LENGTH REDUCTION - A radio frequency (RF) transceiver system comprises an input port configured to receive an RF receive signal and a receiver (RX) digital signal processing (DSP) unit configured to process a digital IF signal based on the RF receive signal and generate a processed digital IF signal at an output port based thereon. Further, the RF transceiver system comprises a digital interface unit comprising a digital interface configured to convey the processed digital IF signal from the output port. In addition, the RF transceiver system comprises a quality estimation unit configured to estimate a quality indicator of the RF receive signal or a signal associated therewith, and dynamically adapt a digital transmission word length of the processed digital IF signal over the digital interface, based on the estimated quality indicator. | 2016-12-29 |
20160380656 | PROGRAMMABLE TRANSMIT CONTINUOUS-TIME FILTER - A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF. | 2016-12-29 |
20160380657 | INTERFERENCE CANCELLATION - A method for interference cancellation in a wireless communication receiver including a signal generator configured to regenerate, from a communication signal received from a plurality of cells, an interference signal of a current subframe of a cell for which information bits are known; and a subtractor configured to subtract the regenerated interference signal from the received communication signal, or from a buffered communication signal having interference of one or more cells cancelled. | 2016-12-29 |
20160380658 | RECEIVER CIRCUIT AND ASSOCIATED METHOD CAPABLE OF CORRECTING ESTIMATION OF SIGNAL-NOISE CHARACTERISTIC VALUE - A receiver circuit capable of correcting an estimation of a signal-noise characteristic value (e.g., SNR) is provided. The receiver circuit includes an equalizer, a slicer, an estimation circuit and a correction circuit. The equalizer provides an equalized signal according to a received signal. The slicer interprets digital information in the equalized signal and accordingly provides a sliced signal. The estimation circuit provides an initial signal-noise characteristic value according to a difference between the equalized signal and the sliced signal. The correction circuit provides a corresponding correction value according to the initial signal-noise characteristic value, and corrects the initial signal-noise characteristic value according to the corresponding correction value to generate a corrected signal-noise characteristic value. | 2016-12-29 |
20160380659 | SIGNAL PROCESSING METHOD AND APPARATUS - A signal processing method and apparatus are disclosed. The signal processing method includes: receiving, by a first signal processing apparatus, a mixed signal; acquiring, by the first signal processing apparatus, an energy strength ratio of the mixed signal, where the energy strength ratio includes a ratio of energy strength of a signal sent by a first signal source and received by the first signal processing apparatus to energy strength of a signal sent by a second signal source and received by the first signal processing apparatus; and if the energy strength ratio is less than a first preset threshold, using, by the first signal processing apparatus, the signal sent by the second signal source in the mixed signal as an interference signal and separating the interference signal, and determining that a mixed signal obtained after the separation processing is the desired signal sent by the first signal source. | 2016-12-29 |
20160380660 | Methods and Apparatus for Reducing Noise, Power and Settling Time in Multi-Modal Analog Multiplexed Data Acquisition Systems - Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed. | 2016-12-29 |
20160380661 | METHOD OF PROCESSING SIGNALS, DATA PROCESSING SYSTEM, AND TRANSCEIVER DEVICE - A data processing system may include a transmit circuit configured to transmit a first signal sequence comprising one or more signals, a receive circuit configured to transmit a second signal sequence comprising one or more additional signals, wherein one or more signals of the second signal sequence comprise an interference component related to the first signal sequence, and a processing circuit. The processing circuit may be configured to generate a kernel set comprising one or more kernels based on the first signal sequence, wherein a first kernel of the kernel set comprises: a first complex exponential component of the first kernel based on the phase of a first signal of the first signal sequence, and a second complex exponential component of the first kernel based on the amplitude of the first signal of the first signal sequence, and apply the kernel set to generate a solution to a linear system, wherein the solution to the linear system represents a substantially linear relationship between the kernel set and the signal component of the second signal sequence arising from the first signal sequence. | 2016-12-29 |
20160380662 | WIRELESS COMMUNICATION DEVICE - A method includes receiving a request to send data to a destination device. The method includes determining a value associated with. QoS of a wireless network. The wireless communication device includes first SIM card information that enables first data delivery according to a first priority via the wireless network and second SIM card information that enables second data delivery via the wireless network according to a second priority at least at a first delivery rate. The method includes determining, based on the value, a throughput value and a first portion of the data to send with the first data delivery. The method also includes determining a second portion of the data to send to the destination device with the second data delivery based on the throughput value, where the second portion includes none of the data when the throughput value is greater than a threshold. | 2016-12-29 |
20160380663 | BUTTON INTEGRATION FOR AN ELECTRONIC DEVICE - This application relates to various button related embodiments for use with a portable electronic device. In some embodiments, a snap clip can be integrated with a button bracket to save space where two separate brackets would take up too much space in the portable electronic device. In other embodiments, a tactile switch can be waterproofed by welding a polymeric layer atop a tactile switch assembly. In this way water can be prevented from contacting moisture sensitive components of the tactile switch assembly. The weld joining the polymeric layer to the tactile switch can include at least one gap to trapped gas surrounding the tactile switch assembly to enter and exit during heat excursions caused by various operating and/or assembly operations. | 2016-12-29 |
20160380664 | METHODS AND APPARATUS FOR CONTROLLING MULTIPLE-INPUT AND MULTIPLE-OUTPUT OPERATION IN A COMMUNICATION DEVICE BASED ON A POSITION SENSOR INPUT - A method for disabling multiple-input and multiple-output operation in a communication device includes communicating data using multiple-input and multiple-output operation, wherein the data is communicated using multiple transceiver paths. Further, the method includes receiving position sensor input and disabling at least a portion of one or more transceiver paths, of the multiple transceiver paths, based on the position sensor input. | 2016-12-29 |
20160380665 | COEXISTENCE OVER A SHARED BAND WITH DUAL ANTENNA SHARING - This disclosure provides techniques for managing antenna sharing on a multi-mode wireless device between coexisting cellular and WLAN modems operating on the same band. One of the modems can communicate a WLAN scanning parameter to another one of the modems, and the distribution of shared antennas between the cellular modem and the WLAN modem may be modified based at least in part on the communicated scanning parameter to accommodate a WLAN scan on channels in the shared band. The distribution of the shared antennas between the modems for the WLAN scan may additionally or alternatively be selected based at least in part on the source of a detected WLAN scanning trigger (e.g., whether the scan is triggered by an application of the wireless device or the WLAN modem of the wireless device). | 2016-12-29 |
20160380666 | TRANSCEIVER DEVICE AND METHOD OF PROCESSING SIGNALS - A method of processing signals may include calculating a covariance matrix and a correlation vector based on an input signal vector and an output signal vector; identifying a plurality of critical elements of a parameter vector based on a predefined criteria, wherein the parameter vector describes a relationship between the input signal vector and the output signal vector; calculating a solution to a linear system to generate a reduced parameter update vector having a plurality of elements, wherein the linear system is based on the plurality of critical elements of the parameter vector, the covariance matrix, and the correlation vector; updating the plurality of critical elements of the parameter vector using the reduced parameter update vector to generate an updated parameter vector, wherein the reduced parameter update vector has less elements than the parameter vector; and processing one or more signals associated with the input signal vector using the updated parameter vector. | 2016-12-29 |
20160380667 | HARMONIC-BASED CODING - A communicated signal is made up of a fundamental frequency and zero or more harmonic frequencies of the fundamental frequency. These harmonic frequencies are selected to represent digital data (e.g., binary bits) according to a mapping of different digital patterns to different combinations of a fundamental frequency and zero or more harmonic frequencies of the fundamental frequency. For example, a transmit-side device may encode a given digital pattern as a signal made up of the corresponding fundamental frequency and zero or more harmonics indicated for that digital pattern in the mapping. The transmit-side device sends this signal to a receive-side device. The receive-side device may then identify the fundamental frequency and zero or more harmonics of the received signal and thereby determine, based on the mapping, the digital pattern sent by the transmit-side device. | 2016-12-29 |