52nd week of 2010 patent applcation highlights part 70 |
Patent application number | Title | Published |
20100332676 | Software Aware Throttle Based Flow Control - A system, comprising a compute node and coupled network adapter (NA), that supports improved data transfer request buffering and a more efficient method of determining the completion status of data transfer requests. Transfer requests received by the NA are stored in a first buffer then transmitted on a network interface. When significant network delays are detected and the first buffer is full, the NA sets a flag to stop software issuing transfer requests. Compliant software checks this flag before sending requests and does not issue further requests. A second NA buffer stores additional received transfer requests that were perhaps in-transit. When conditions improve the flag is cleared and the first buffer used again. Completion status is efficiently determined by grouping network transfer requests. The NA counts received requests and completed network requests for each group. Software determines if a group of requests is complete by reading a count value. | 2010-12-30 |
20100332677 | EFFICIENT FILE TRANSFER ON WEB SERVICE-ENABLED IMAGE FORMING DEVICE - Techniques are provided for efficiently transferring documents (or files) between a client device and a WS-enabled device. A document is divided into a plurality of distinct chunks. Each chunk is packaged in a separate SOAP message. Each SOAP message includes a document identifier and a data transmission serial number (DTSN). The DTSN uniquely identifies a particular chunk of the document relative to the other chunks of the document. After one or more chunks of the document are transferred, the size of one or more subsequent chunks is adjusted based on changes in the client device, the WS-enabled device, and/or the network connection. Thereafter, each of the one or more subsequent chunks of the document is either larger or smaller than the one or more chunks that were already transferred. | 2010-12-30 |
20100332678 | SMART NAGLING IN A TCP CONNECTION - An approach is provided to improve network efficiency. A send segment size, such as a maximum segment size (MSS), that corresponds to data segments being sent to a receiver over a computer network. A data block is identified in a send buffer and the data block includes more than one data segments. Based on the determined send segment size, all but a remaining data segment of the data segments are sent to the receiver. The sent data segments are each the determined send segment size and the remaining data segment is smaller than the send segment size. The remaining data segment is sent to the receiver in response to identifying that the remaining data segment is a portion of the data block. | 2010-12-30 |
20100332679 | FRAME RELAY DEVICE AND FRAME RELAY METHOD - A communication relay device includes a memory that stores a flooding destination address in advance separately from a learning table. When a source address received from a terminal is learned, the communication relay device determines whether the source address matches the stored destination address of the terminal, and when these addresses match each other, causes the matching source address to be learned more preferentially than other source addresses. | 2010-12-30 |
20100332680 | FAULT TOLERANCE APPROACHES FOR DNS SERVER FAILURES - Techniques are provided for handling failures of DNS (domain name system) servers to respond to DNS queries. A DNS resolver is configured to resolve domain names, and includes a time-to-live (TTL)-based cache, a negative cache, and a long term store cache. The TTL-based cache is configured to temporarily store domain names with resolved IP addresses. The negative cache is configured to store negative entries that include information indicating domain names that were failed to be resolved. The long term store cache is configured to store domain names with resolved IP address for an indefinite time period. The caches are accessed in a manner that enables fewer DNS query retries to be performed when a DNS server is non-responsive, to reduce delays and network traffic. Furthermore, the DNS resolver may reduce a number of DNS queries performed the longer the DNS server stays non-responsive. | 2010-12-30 |
20100332681 | COMMUNICATION APPARATUS CAPABLE OF SELECTING A PROPER SOURCE ADDRESS FROM A PLURALITY OF SOURCE ADDRESSES ASSIGNED THERETO, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - A communication apparatus capable of selecting a proper source address even when a plurality of source addresses are assigned thereto and reducing the occurrence of a communication error caused by a source address change during communication processing. A transmission section transmits data. A transmission information management section manages transmission information including data identification information for identifying a type of data to be transmitted, and a destination address and source address of the data. A source address-determining section is operable when data to be transmitted is of a specific type, to refer to the managed transmission information, and out of the assigned source addresses, determine a source address used in the past for transmitting data to a destination address of the data to be transmitted, as a source address thereof. A communication control section causes the transmission section to transmits the data using the determined source address. | 2010-12-30 |
20100332682 | UPDATING MULTIPLE COMPUTING DEVICES - A system includes a server site that includes a memory for storing update data sets that correspond to data sets stored on multiple computing devices of a user. The system also includes a synchronization manager for determining that one computing device associated with the user and another computing device associated with the user are absent one or more data updates stored in the memory at the server site. The synchronization manager is configured to send in parallel, absent establishing a data transfer lock, the one or more data updates to the both computing devices of the user for updating the corresponding data stored on each computing device. | 2010-12-30 |
20100332683 | Methods and Apparatus for Merging Peer-to-Peer Overlay Networks - Methods and apparatus for merging peer-to-peer overlay networks. A method includes receiving an advertisement from a second overlay network, determining a size of the second overlay network, performing a self search on the second overlay network based on a persistent node identifier, if the size of the second overlay network is greater than the size of a first overlay network, and joining the second overlay network if the persistent node identifier is not part of the second overlay network. An apparatus includes a transceiver to receive an advertisement from a second overlay network, and a processor coupled to the transceiver to determine a size of the second overlay network, perform a self search on the second overlay network based on a persistent node identifier, and join the second overlay network if the persistent node identifier is not part of the second overlay network. | 2010-12-30 |
20100332684 | SYSTEM AND METHOD FOR PROVIDING A SPLIT DEPLOYMENT MODEL FOR A TELECOMMUNICATION SERVICE ACCESS GATEWAY - A split deployment model is enabled for a telecommunication service access gateway. The services of the gateway are segregated into a set of core services that provide container-based functionality and a set of exposure services that enable network integration and translation of protocols. The core services are executed as part of the application server, while the exposure services are deployed in separate archive files. This isolation of services allows single or groups of services to be independently upgraded, patched or removed and reduces the impact of one service on others. Furthermore, the services can scale independently, allowing additional hardware resources to be added to a particular service. Multiple versions of a single service can also be deployed in a single cluster or server. | 2010-12-30 |
20100332685 | APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA - A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream. | 2010-12-30 |
20100332686 | WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS - Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device. | 2010-12-30 |
20100332687 | METHOD AND APPARATUS FOR RESTRICTING THE EXECUTION OF OPEN SERVICES GATEWAY INITIATIVE (OSGi) LIFE CYCLE COMMANDS - Method and Open Services Gateway initiative (OSGi) device for selective execution of commands from a controller device in Open Services Gateway initiative (OSGi) framework are provided. The method includes receiving a request for execution of a command from a controller device. The method also includes determining if the command is associated with a unique identifier of the controller device based on a reference database. The reference database stores the unique identifier of the controller device and a set of commands associated with the unique identifier. The method further includes executing the command when the command is associated with the unique identifier. | 2010-12-30 |
20100332688 | ORIENTATION MEASUREMENT TOOL FOR SEISMIC DATA ACQUISITION - An apparatus for in-field configuration of a seismic device such as a seismic sensor may include a memory module having data for configuring the seismic device, a location sensor determining a location parameter for the seismic sensor, an alignment member aligning the location sensor with the seismic sensor, and a communication device transmitting the determined location parameter to a selected external device. | 2010-12-30 |
20100332689 | CABLE CONNECTION SUPPORT APPARATUS AND METHOD OF SUPPORTING CABLE CONNECTION - A cable connection support apparatus has a structure in which a master apparatus and a slave apparatus are connected to both ends of a plurality of cables, and each apparatus is connected to each cable by a connecting terminal. The master apparatus and the slave apparatus are grounded. The master apparatus makes, for each connected cable, an inquiry about a position of a terminal of the slave apparatus to which the cable is connected, and inspects for inter-continuity, grounded connection, and unintentional disconnection. The connection destinations and inspection results are displayed on a display apparatus. Consequently, the connection condition for each cable wire in a cable can be confirmed. | 2010-12-30 |
20100332690 | PROCESSOR PERFORMANCE ANALYSIS DEVICE, METHOD, AND SIMULATOR - A processor performance analysis device analyzes performance of a multithreaded processor in a system LSI which includes: the multithreaded processor which executes processing in parallel using multiple logical processors; a functional core which executes processing different from the processing executed by the multithreaded processor; and a memory interface which receives each access request and controls access to memory. The processor performance analysis device includes: an operational information output unit which monitors the multithreaded processor to output operational information; an access information output unit which monitors the memory interface to output memory access information; and an analysis information output unit which analyzes the performance of the multithreaded processor using the operational information and the memory access information. | 2010-12-30 |
20100332691 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - An information processing apparatus includes an interface unit configured to connect with a peripheral device capable of loading a storage medium, a first processing unit configured to execute a process for causing the storage medium inserted into the peripheral device connected to the interface unit to be in an unusable state, a connection detection unit configured to detect that the peripheral device is connected to the interface unit, a determination unit configured to determine whether the storage medium which is caused by the first processing unit to be in the unusable state is inserted into the peripheral device detected by the connection detection unit, and a control unit configured to control the first processing unit to cause the storage medium to be in the unusable state according to the determination unit determining that the storage medium which is caused by the first processing unit to be in the unusable state is inserted into the peripheral device. | 2010-12-30 |
20100332692 | INFORMATION PROCESSING APPARATUS, AND METHOD FOR CONTROLLING THE SAME - An information processing apparatus includes an interface, a detector, a manager, a usage interruption unit, and a determination unit. The interface is for connecting to a peripheral device to form a connected peripheral device. The detector is for detecting a connection and a disconnection between the interface and a peripheral device. The manager is for managing device specifying information that specifies the connected peripheral device. The usage interruption unit is for setting a connected peripheral device to a usage interruption state. The determination unit is for determining whether the usage interruption unit set the connected peripheral device to the usage interruption state. The manager may manage a reconnected peripheral device using device information that existed before the connected peripheral device was disconnected from the interface. | 2010-12-30 |
20100332693 | DIRECT MEMORY ACCESS IN A COMPUTING ENVIRONMENT - A method of address translation in a computing system providing direct memory access (DMA) by way of one or more remote memory management units (MMUs) is provided. The method comprises intercepting a request for a first DMA operation forwarded by a first device to a second device; and translating a guest address included in the request to a first address according to a mapping referencing a memory frame in a memory of the second device. A local MMU increments a first reference count indicating number of active DMA operations directed to the memory frame and a second reference count indicating number of remote MMUs that have mapped the memory frame. | 2010-12-30 |
20100332694 | METHOD AND APPARATUS FOR USING A SINGLE MULTI-FUNCTION ADAPTER WITH DIFFERENT OPERATING SYSTEMS - A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface. | 2010-12-30 |
20100332695 | INFORMATION DETECTING APPARATUS AND METHOD - Proposed is a highly reliable information detecting apparatus and method. In an information detecting apparatus and method for detecting transmission information a transmission signal in which a burst period of transmitting a burst signal and a space period as a no-signal period are repeated in a pattern according to the subject matter of the transmission information, whether the absolute value of a signal amplitude level of the transmission signal is not less than a first threshold is detected, whether the absolute value of a signal amplitude level of the transmission signal is not less than a second threshold is detected, and whether the amplitude level displacement of the transmission signal is based on noise or the reception of the transmission information is determined based on the detection results. | 2010-12-30 |
20100332696 | Managing I/O Request in Storage System - The invention relates to management of a plurality of I/O requests in a storage system. The host interface module is configured to receive a plurality of I/O request which includes an associated priority; create an I/O request queue for each associated priority; define a threshold value for the queue length for each of the plurality of I/O request queues; and determine if the queue length for one of the plurality of the I/O request queue corresponding to the associated priority is less than the defined threshold value for the queue length for the one of the plurality of the I/O request queues. If the queue length of the one of the plurality of I/O request queues is more than the defined threshold value for the queue then the host interface module is further configured to rejecting the I/O request and sending a queue full message; wherein the threshold value for the queue length is based on the processing rate of the I/O requests in the plurality of the I/O request queues. | 2010-12-30 |
20100332697 | STORAGE DEVICE AND STORAGE DEVICE ASSEMBLY - A storage device includes a USB connector, a storage module, a first USB receiver, and a multiplexer. The USB connector is configured for connected to a computer. The storage module is configured for storing data. The first USB receiver is configured to receive a second storage device. The multiplexer is connected to the USB connector and the first USB receiver, and is capable of accessing the storage module, wherein the multiplexer is capable of accessing the storage module and the second storage device at the same time when the USB connector is connected to the computer and the second storage device is connected to the first USB receiver. | 2010-12-30 |
20100332698 | EFFICIENT BUFFER MANAGEMENT IN A MULTI-THREADED NETWORK INTERFACE - Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed. | 2010-12-30 |
20100332699 | COMPUTER READABLE MEDIUM AND INFORMATION PROCESSING APPARATUS - A computer readable medium storing a program causing a computer to execute a process for managing peripheral devices, the process includes: acquiring a state of an apparatus when a peripheral device is connected to the apparatus; controlling the peripheral device to be available in a case where the acquired state of the apparatus is a first state, when a kind of the connected peripheral device is a first kind; and controlling the peripheral device to be available in a case where the acquired state of the apparatus is a second state, when the kind of the connected peripheral device is a second kind, in addition to when the kind of the connected peripheral device is the first kind. | 2010-12-30 |
20100332700 | DATA STOREWIDTH ACCELERATOR - Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration. | 2010-12-30 |
20100332701 | HOST COMPUTER, COMPUTER TERMINAL, AND CARD ACCESS METHOD - According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information. | 2010-12-30 |
20100332702 | KVM SWITCH APPARATUS WITH BRIDGING FUNCTION - A KVM switch apparatus with bridging function includes a processor with a keyboard connection interface and a mouse connection interface; a keyboard/mouse switching circuit; a USB bridge unit and at least one computer interface unit electrically connected to at least one computer. The keyboard/mouse switching circuit and the USB bridge unit are selectively connected, whereby a switching of bridging channels is provided between at least two computers. | 2010-12-30 |
20100332703 | COMPUTER UNIT, COMPUTER PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - Improves ease of operation by making it easier for the operator to view and select storage media devices connected to a computer unit. Provides a computer unit with a USB root hub and running an operating system that has the function of managing a storage media device connected to the root hub directly or indirectly via a hub. The unit includes a topology configuration portion that, when the hub is connected to a port of the root hub and the storage media device is connected to the hub, configures the hub as a virtual drive and sets up a connection whereby a folder corresponding to the storage media device is placed in the virtual drive; and a display controller that displays on a display device a directory list DP of the connections that were configured by the topology configuration portion. | 2010-12-30 |
20100332704 | SEMICONDUCTOR DEVICE AND SERIAL INTERFACE CIRCUIT - The serial interface circuit can adapt to various frame formats readily and reduces the load on CPU owing to serial interface. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields before a data field of a frame defined by a communication protocol. The inter face circuit analyzes the field structure before the data field according to a setting of the control register. Only when a destination of a received frame is judged to match an expected value, the inter face circuit issues a request for having CPU process the data field information. After a setting is made on the control register, the serial interface circuit can readily adapt to various formats of frames defined by a communication protocol according to the information held there, and can even analyze a destination. | 2010-12-30 |
20100332705 | GROUP MASTER COMMUNICATION SYSTEM AND METHOD FOR SERIALLY TRANSMITTING DATA IN AUTOMATION SYSTEMS - A communication system and method are disclosed for serially transmitting data in automation systems. In at least one embodiment, the system includes a base module as the system master, a plurality of extension modules as the slaves and a bidirectional communication connection that serially connects the base module to the extension modules. A status as group master for the serially subsequent extension module is allocated to at least two of the extension modules, the base module communicating with the extension modules depending on said allocation. | 2010-12-30 |
20100332706 | SENSOR TRANSMITTER DEVICE AND METHOD FOR TRANSMITTING THE PAYLOAD DATA OF A SENSOR TO A BUS CONTROL DEVICE - A sensor transmitter device for transmitting the payload data of a sensor to a bus control device is described, the sensor transmitter device being connectable to a data bus of a vehicle, which is configured for simultaneous transmission of bus data packets between a plurality of sensor transmitter devices and a bus control device. The bus data packets should include at least one signaling field and one payload data field having a plurality of payload data blocks. The sensor transmitter device includes a sensor interface for receiving payload data which represent a physical variable and a memory which is configured for storing position information which identifies at least one payload data block from the payload data field, which is reserved exclusively for the transmission of payload data from the sensor transmitter device to the bus control device. The sensor transmitter device also includes a bus interface which is configured for placing, after receiving predetermined signaling data in the signaling field, at least part of the payload data received via the sensor interface in the payload data block specified by the position information. | 2010-12-30 |
20100332707 | Bi-directional handshake for advanced reliabilty availability and serviceability - In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed. | 2010-12-30 |
20100332708 | Information Processing Apparatus - According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed. | 2010-12-30 |
20100332709 | PERFORMANCE OPTIMIZATION SYSTEM, METHOD AND PROGRAM - Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access. | 2010-12-30 |
20100332710 | HARD DISK DRIVE HAVING A BYPASS FOR SAS/SATA SIGNALS - There is disclosed a mass storage device (such as a hard disk drive) comprising an input connector for electrically receiving both a first set of data signals and a second set of data signals. The first set of data signals are used to store or retrieve information on the mass storage device, whereas the second set of data signals are electrically conducted to an output connector on the mass storage device. When an adjacent mass storage device is connected to the output connector, the second set of data signals are used to store or retrieve information on this adjacent mass storage device. | 2010-12-30 |
20100332711 | Display device with built in hard drive docking station - The invention is directed to a display device having an integral hard disk drive; in particular, a removable integral hard disk drive removable by a docking port. The display device and hard disk drive share a power supply and a housing. | 2010-12-30 |
20100332712 | APPARATUSES FOR REGISTER FILE WITH NOVEL BIT CELL IMPLEMENTATION - Approaches to organizing/constructing a register file base cell in a way that reduces the number of signals which need to be routed to and through the bit base cell are disclosed. Base cells so constructed allow industry standard static timing approaches and tools to verify the timing of a register file comprised of such base cells as a whole and allow industry standard place-and-route (APR) tools to be used to implement the connections between the base cells and the other register file logic not directly included in the base cell. | 2010-12-30 |
20100332713 | Systems and Methods for Efficient Handling of Data Traffic and Processing Within a Processing Device - The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power. | 2010-12-30 |
20100332714 | INTEGRATED CIRCUIT SYSTEM, AND DATA READOUT METHOD - An integrated circuit system includes: a first integrated circuit that is connected with a first data bus having first bus width and requires first time to perform data transmission and reception once; a second integrated circuit that is connected with a second data bus having second bus width larger than the first bus width in bit width and requires second time longer than the first time to perform data transmission and reception once; and a relay circuit that is connected with the first data bus and the second data bus and transmits and receives data to and from the first integrated circuit and the second integrated circuit respectively via the buses. | 2010-12-30 |
20100332715 | VEHICLE SYSTEM MONITORING AND COMMUNICATIONS ARCHITECTURE - Systems, methods and devices are provided that allow more efficient transfer and processing of sensor information in a hierarchical data system. The system provides for a plurality of component area managers (CAM), each of the CAMS being in operable communication with at least one of a plurality of transducers that monitors a phenomena of a component and in operable communication with a data bus. A CAM comprises a processor in operable communication with the at least one transducer of the plurality of transducers, wherein the first processor is configured to record data generated by the at least one transducer of the plurality of transducers, to reduce the recorded data, to place the reduced data on the data bus. The system also includes a transducer selection module controlled by the first processor by which the first processor selects one of the plurality of transducers to record and a rolling buffer in operable communication with the first processor and in operable communication with the at least one transducer by which to record the data generated by the at least one transducer of the plurality in a first-in-first-out manner. | 2010-12-30 |
20100332716 | METAPHYSICALLY ADDRESSED CACHE METADATA - Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space. | 2010-12-30 |
20100332717 | ACCESS DEVICE, INFORMATION RECORDING DEVICE, CONTROLLER, AND INFORMATION RECORDING SYSTEM - Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module ( | 2010-12-30 |
20100332718 | SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY IN MEMORY DEVICES - Memory devices, memory controllers, methods, and systems are provided, such as methods for masking the row cycle latency time of a memory array. In one embodiment, a memory device that is configurable to operate in full or reduced density modes is provided. In a reduced density mode, certain banks within the memory array function as duplicate memory banks associated with an addressable memory bank. Write operations performed in the reduced density mode may write a data segment to an addressed memory bank as well as its associated duplicate banks. When repeated read requests are issued for the data segment, the read requests may be interleaved between the addressed bank and its duplicate banks, thereby masking the row cycle time of each physical bank. That is, the interval between each read out of the data segment from the memory array will appear to be less than the row cycle time. | 2010-12-30 |
20100332719 | Memory Write Signaling and Methods Thereof - In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources. | 2010-12-30 |
20100332720 | Direct Memory Access and Super Page Swapping Optimizations For A Memory Blade - A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network. | 2010-12-30 |
20100332721 | OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY - Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction. | 2010-12-30 |
20100332722 | VIRTUAL MACHINE SYSTEM AND CONTROL METHOD THEREOF - In a two-level virtual machine system having child VMMs operating on a parent VMM, the field update frequency of VMCS and VMCB which control a VMM assist function of a CPU is not uniform. A G field requiring reflection of emulation results is higher in update frequency than a C field. The semiconductor quantity and power dissipation caused by the assist function expansion tend to increase in the C field used for a condition decision as compared with the G field simply retaining a value because influence upon the CPU operation is greater in the C field. Therefore, events relating to the G field which is high in update frequency and less in increase of semiconductor quantity and power dissipation caused by the assist function expansion are coped with by the CPU with its assist function expanded. Events relating to the C field are coped with by the parent VMM. | 2010-12-30 |
20100332723 | Memory Device and Method for Embedding Host-Identification Information into Content - A memory device and method for embedding host-identification information into content are disclosed. In one embodiment, a memory device is provided comprising a memory operative to store content and a controller in communication with the memory. The controller is operative to receive a credential comprising host-identification information from a host in communication with the memory device, authenticate the host using the credential, receive a request from the host to play content stored in the memory, embed the host-identification information into the content, and send the content with the embedded host-identification information to the host. | 2010-12-30 |
20100332724 | Accessing a Serial Number of a Removable Non-Volatile Memory Device - A removable non-volatile memory device durably stores a serial number or identifier, which is used to mark multimedia content legally stored on the removable non-volatile memory device. In order to retrieve the serial number, a host electronic system coupled to the removable non-volatile memory device sends a sequence of multiple file access commands to access a predefined target file stored on the removable non-volatile memory device. In accordance with the executed predefined sequence of multiple file access commands, a corresponding sequence of data access commands are received at the removable non-volatile memory device and are interpreted as a request by the host electronic device to read the serial number. The removable non-volatile memory device outputs the serial number in response to the sequence of data access commands. | 2010-12-30 |
20100332725 | PINNING CONTENT IN NONVOLATILE MEMORY - Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g., directories or files) to be pinned. A list of pinned sectors can be stored so that a driver or controller that operates on a sector basis and not a file or directory basis can identify data to be pinned. | 2010-12-30 |
20100332726 | STRUCTURE AND METHOD FOR MANAGING WRITING OPERATION ON MLC FLASH MEMORY - A method for managing a writing operation for a multi-level cell (MLC) nonvolatile memory by a host is provided. The MLC nonvolatile memory has a plurality of MLC blocks, each MLC cell of each MLC block can store multiple logical data bits. The method includes forming a turbo writing unit from the spare block pool; writing a data sent by the host to the turbo writing unit; and changing the role of the turbo writing unit into a turbo data unit. The turbo writing unit is formed with at least one of the MLC blocks, each MLC cell of the at least one of the MLC blocks stores a portion of the logical data bits the MLC cell is capable of storing. | 2010-12-30 |
20100332727 | EXTENDED MAIN MEMORY HIERARCHY HAVING FLASH MEMORY FOR PAGE FAULT HANDLING - A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM. | 2010-12-30 |
20100332728 | SYSTEM AND METHOD OF SELECTING A FILE PATH OF A REMOVABLE STORAGE DEVICE - Systems and methods of identifying a file path of a removable storage device are disclosed. A method includes, at a host device that is coupled to the removable storage device, selecting a file path that is associated with the removable storage device by accessing a size associated with a root directory accessible to the host device, where the root directory corresponds to the removable storage device. The file path is selected based upon the size associated with the root directory. The selected file path is verified by initiating a memory access operation using the selected file path. | 2010-12-30 |
20100332729 | MEMORY OPERATIONS USING LOCATION-BASED PARAMETERS - Systems and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a first set of parameter values associated with a first physical block of a memory array. The first set of parameter values is identified based on a first physical location of the first physical block. A memory access operation is initiated with respect to the first physical block in accordance with the first set of parameter values. | 2010-12-30 |
20100332730 | METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY - A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention. | 2010-12-30 |
20100332731 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command. | 2010-12-30 |
20100332732 | MEMORY SYSTEMS AND MAPPING METHODS THEREOF - Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s). | 2010-12-30 |
20100332733 | MATERIAL SERVER AND METHOD OF STORING MATERIAL - According to one embodiment, a material server that includes a NAND flash memory which stores material that includes one or all of moving image data, audio data, and ANC data. A material ID detector detects a material ID in inputted material when such material is inputted into the material server. A block allocation unit in the material server allocates a block for storing the material each material ID. A plurality of buffers in the material server buffer the material each inputted material ID. A buffering data monitor in the material server monitors buffering data size in the buffers. A memory accessing unit in the material server writes buffered material to the NAND memory when a buffering data monitor detects that the buffering data size amounts to one page size. | 2010-12-30 |
20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 2010-12-30 |
20100332735 | FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE - A flash memory device resilient to bit errors and a programming method suitable for the flash memory are provided. The flash memory device stores data in a parallel manner in a superpage which is generated by grouping a plurality of physical pages into a logical page. The flash memory device spreads input data using a predetermined spreading code to generate spread data. The spread data is stored on a superpage-by-superpage basis. | 2010-12-30 |
20100332736 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block. | 2010-12-30 |
20100332737 | FLASH MEMORY PREPROCESSING SYSTEM AND METHOD - A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data. | 2010-12-30 |
20100332738 | STORAGE DEVICE AND DATA PROCESSING METHOD - A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block. | 2010-12-30 |
20100332739 | Storage device, storage controlling device, and storage controlling method - A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory. | 2010-12-30 |
20100332740 | ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller. | 2010-12-30 |
20100332741 | Interleaving Policies for Flash Memory - Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source. | 2010-12-30 |
20100332742 | DEVICE AND METHOD FOR MONITORING AND USING INTERNAL SIGNALS IN A PROGRAMMABLE SYSTEM - The invention relates to a device for monitoring and using internal signals in a programmable system ( | 2010-12-30 |
20100332743 | SYSTEM AND METHOD FOR WRITING CACHE DATA AND SYSTEM AND METHOD FOR READING CACHE DATA - A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device. With a combination of the on-chip and off-chip memory devices, a large-capacity data storage space and a high-speed read and write efficiency is achieved. | 2010-12-30 |
20100332744 | DATA RECOVERY AND OVERWRITE INDEPENDENT OF OPERATING SYSTEM - Methods and systems to access data in a computer system independent of an operating environment of the computer system, including to recover data to a remote system, to overwrite data, and to copy data to a hidden partition. A management system may directly access a storage device of the computer system and communicate with the remote system over a data channel that is secure from an operating environment of the computer system. The management system may access the storage device on a block basis, using a device driver associated with a storage device controller, and may include a virtualization engine to access the storage device. The remote system may include logic to request meta-data, to identify disk blocks corresponding to files of interest from the meta-data, and to construct the files of interest from the disk blocks. | 2010-12-30 |
20100332745 | AUTOMATED ON-LINE CAPACITY EXPANSION METHOD FOR STORAGE DEVICE - A volume provider unit in a computer system that detects a logical block address of a read or write I/O accessing a logical volume of a storage device from a host. According to the logical block address fetched, a storage domain of the logical volume is dynamically expanded. Moreover, the storage domain of the logical volume is reduced or expanded according to an instruction of logical volume capacity reduction or expansion from a host commander part to a volume server. | 2010-12-30 |
20100332746 | APPARATUS CAPABLE OF COMMUNICATING WITH ANOTHER APPARATUS, METHOD OF CONTROLLING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - An apparatus capable of communicating with another apparatus including a first writing unit for writing data into a plurality of recording mediums housed in a first housing, a first storage, has a first reading unit for reading out data from a plurality of recording mediums housed in a second housing for housing the recording mediums storing data written by the first writing unit, a second reading unit for reading out data from the first storage, a second storage for storing cache data of the plurality of the recording mediums housed in the second housing, a controller unit for enabling the first and second reading units to read out data on the basis of the determined area, and a second writing unit for writing data read out by the first reading unit and the second reading unit into the second storage. | 2010-12-30 |
20100332747 | STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND COMPUTER PROGRAM PRODUCT - Ease of operation is improved by making it easier for the operator to monitor and select a storage medium device connected to a computer device. The device is a USB hard disk connected to a personal computer, and includes a disk, a cache memory, a push-button, and an LED. When the push-button is pushed (S | 2010-12-30 |
20100332748 | DISTRIBUTED DATA STORAGE SYSTEM USING LOCAL COPY OPERATIONS FOR RAID-1 VOLUMES - In a distributed RAID-1 (DR1) copy operation, operation of source and target DR1 volumes is first converted to a local-copy operating mode in which the distributed copy operation is converted into a set of local copy operations. Each t is performed at a respective location of the disks of the DR1 volumes and involves copying data of the source DR1 from a first disk to a second disk via a local second communication channel of relatively high bandwidth. Following conversion, the local copy operations are performed at the locations. Upon completion of the local copy operations, storage operations to the source and target DR1 volumes are temporarily suspended, operation of the source and target DR1 volumes is converted back to the normal operating mode, and storage operations to the source and target DR1 volumes are resumed. | 2010-12-30 |
20100332749 | WEAR LEVELING OF SOLID STATE DISKS DISTRIBUTED IN A PLURALITY OF REDUNDANT ARRAY OF INDEPENDENT DISK RANKS - A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present. | 2010-12-30 |
20100332750 | MAINTAINING ACCESS TIMES IN STORAGE SYSTEMS EMPLOYING POWER SAVING TECHNIQUES - An apparatus, method, and computer program for maintaining access times in a data processing system, wherein the data processing system comprises a plurality of storage devices, the apparatus including: a receive component, for receiving a command or an availability message, wherein an availability message indicates whether the storage device is available; an evaluate component for evaluating a plurality of first relationships between the storage devices and a plurality of first values, wherein each of the first values indicates whether a related storage device is a redundant; a send component, for sending a power message to one or more of the storage devices; and an update component for updating a second relationship between the redundant storage device and a plurality of second values, wherein each of the second values indicates whether a related redundant storage device is available. | 2010-12-30 |
20100332751 | DISTRIBUTED STORAGE PROCESSING MODULE - A dispersed storage (DS) processing module may include a gateway module operable to communicate data and/or corresponding information with a user device and may include an access module operable to segment outbound data of the data into one or more outbound data segments and aggregate one or more inbound data segments into inbound data of the data. The DS processing module may include a grid module operable to encode an outbound data segment of the one or more outbound data segments into a plurality of outbound encoded data slices and decode a plurality of inbound encoded data slices into an inbound data segment of the one or more inbound data segments. The DS processing module may include a storage module operable to output the plurality of outbound encoded data slices to a plurality of DS storage units and receive the plurality of inbound encoded data slices from the plurality of DS storage units. | 2010-12-30 |
20100332752 | METHOD TO DEFRAG A MEMORY OF AN IC CARD - A method may defrag a memory for an IC card having a plurality of files stored in memory portions, each file including respective links to one or more other files. The method may include detecting a start address of a first free memory portion of the memory, detecting an address of a memory portion following the start address and storing one file to be moved, detecting files including links to the address of the file to be moved, moving the file to be moved to the start address of the first free memory portion, updating the links to point at the start address, and repeating the above steps until at least two free memory portions following the moved files are separated by one or more of files. | 2010-12-30 |
20100332753 | WAIT LOSS SYNCHRONIZATION - Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions. | 2010-12-30 |
20100332754 | System and Method for Caching Multimedia Data - Systems and methods are provided for caching media data to thereby enhance media data read and/or write functionality and performance. A multimedia apparatus, comprises a cache buffer configured to be coupled to a storage device, wherein the cache buffer stores multimedia data, including video and audio data, read from the storage device. A cache manager coupled to the cache buffer, wherein the cache buffer is configured to cause the storage device to enter into a reduced power consumption mode when the amount of data stored in the cache buffer reaches a first level. | 2010-12-30 |
20100332755 | METHOD AND APPARATUS FOR USING A SHARED RING BUFFER TO PROVIDE THREAD SYNCHRONIZATION IN A MULTI-CORE PROCESSOR SYSTEM - An apparatus and method for improving synchronization between threads in a multi-core processor system are provided. An apparatus includes a memory, a first processor core, and a second processor core. The memory includes a shared ring buffer for storing data units, and stores a plurality of shared variables associated with accessing the shared ring buffer. The first processor core runs a first thread and has a first cache associated therewith. The first cache stores a first set of local variables associated with the first processor core. The first thread controls insertion of data items into the shared ring buffer using at least one of the shared variables and the first set of local variables. The second processor core runs a second thread and has a second cache associated therewith. The second cache stores a second set of local variables associated with the second processor core. The second thread controls extraction of data items from the shared ring buffer using at least one of the shared variables and the second set of local variables. | 2010-12-30 |
20100332756 | PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS - Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed. | 2010-12-30 |
20100332757 | Integrated Pipeline Write Hazard Handling Using Memory Attributes - A system and method for write hazard handling are described, including a method comprising pre-computing a memory management unit policy for a write request using an address that is at least one clock cycle before data; registering the pre-computed memory management unit policy; using the pre-computed memory management unit policy to control a pipeline stall to ensure that non-bufferable writes are pipeline-protected, ensuring that no non-bufferable locations are bypassed from within the pipeline and all subsequent non-bufferable reads will get data from a final destination; bypassing a read request only after a corresponding write request is updated an write pending buffer; decoding the write request with the write request aligned to data; registering the write request in the write pending buffer; allowing arbitration logic to force the pipeline stall for a region that will have a write conflict; and stalling read requests to protect against write hazards. | 2010-12-30 |
20100332758 | Cache memory device, processor, and processing method - A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit. | 2010-12-30 |
20100332759 | METHOD OF PROGRAM OBFUSCATION AND PROCESSING DEVICE FOR EXECUTING OBFUSCATED PROGRAMS - A program is obfuscated by reordering its instructions. Original instruction addresses are mapped to target addresses. A cache efficient obfuscated program is realized by restricting target addresses of a sequence of instructions to a limited set of the disjoint ranges ( | 2010-12-30 |
20100332760 | MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION - A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events. | 2010-12-30 |
20100332761 | Reconfigurable Cache - A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power. | 2010-12-30 |
20100332762 | DIRECTORY CACHE ALLOCATION BASED ON SNOOP RESPONSE INFORMATION - Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy of the data corresponding to the address. Other embodiments are also disclosed. | 2010-12-30 |
20100332763 | APPARATUS, SYSTEM, AND METHOD FOR CACHE COHERENCY ELIMINATION - An apparatus, system, and method are disclosed for improving cache coherency processing. The method includes determining that a first processor in a multiprocessor system receives a cache miss. The method also includes determining whether an application associated with the cache miss is running on a single processor core and/or whether the application is running on two or more processor cores that share a cache. A cache coherency algorithm is executed in response to determining that the application associated with the cache miss is running on two or more processor cores that do not share a cache, and is skipped in response to determining that the application associated with the cache miss is running on one of a single processor core and two or more processor cores that share a cache. | 2010-12-30 |
20100332764 | Modular Three-Dimensional Chip Multiprocessor - A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is present but not if the stacked cache die is absent. In one implementation, the chip multiprocessor die includes a first set of connection pads for electrically connecting to a die package and a second set of connection pads for communicatively connecting to the stacked cache die if the stacked cache die is present. Other embodiments, aspects and features are also disclosed. | 2010-12-30 |
20100332765 | HIERARCHICAL BLOOM FILTERS FOR FACILITATING CONCURRENCY CONTROL - Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict. | 2010-12-30 |
20100332766 | SUPPORTING EFFICIENT SPIN-LOCKS AND OTHER TYPES OF SYNCHRONIZATION IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM - Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations. | 2010-12-30 |
20100332767 | Controllably Exiting An Unknown State Of A Cache Coherency Directory - In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed. | 2010-12-30 |
20100332768 | FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS - A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mechanism implementing an instruction set architecture including instructions accessible by software. The instructions are configured to: set per-hardware-thread, for a first thread, memory access monitoring indicators for a plurality of memory blocks, and test whether any monitoring indicator has been reset by the action of a conflicting memory access by another agent. The processor further includes mechanism configured to: detect conflicting memory accesses by other agents to the monitored memory blocks, and upon such detection of a conflicting access, reset access monitoring indicators corresponding to memory blocks having conflicting memory accesses, and remember that at least one monitoring indicator has been so reset. | 2010-12-30 |
20100332769 | Updating Shared Variables Atomically - When a thread begins an atomic transaction, the thread reads one or more variables from one or more source addresses. The read portion of the transaction is constrained to a predetermined amount of time or number of cycles (N). The mechanism then performs a test and set operation to determine whether any other threads hold locks on the one or more source addresses. If the locks for the one or more source addresses are free, then the thread acquires locks on the one or more source addresses. The thread then performs work and updates the one or more variables. Thereafter, the mechanism delays for an amount of time or number of cycles greater than or equal to N before releasing the locks. If another thread attempts to acquire a lock on the one or more source addresses, then the test and set operation for that other thread will fail. | 2010-12-30 |
20100332770 | Concurrency Control Using Slotted Read-Write Locks - A system and method for concurrency control may use slotted read-write locks. A slotted read-write lock is a lock data structure associated with a shared memory area, wherein the slotted read-write lock indicates whether any thread has a read-lock and/or a write-lock for the shared memory area. Multiple threads may concurrently have the read-lock but only one thread can have the write-lock at any given time. The slotted read-write lock comprises multiple slots, each associated with a single thread. To acquire the slotted read-write lock for reading, a thread assigned to a slot performs a store operation to the slot and then attempts to determine that no other thread holds the slotted read-write lock for writing. To acquire the slotted read-write lock for writing, a thread assigned to a slot sets its write-bit and then attempts to determine that the write-lock is not held. | 2010-12-30 |
20100332771 | PRIVATE MEMORY REGIONS AND COHERENCE OPTIMIZATIONS - Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions. | 2010-12-30 |
20100332772 | APPARATUS, COMPUTER-READABLE RECORDING MEDIUM AND STORAGE SYSTEM - A apparatus for controlling a first storage and a second storage, has a controller for receiving a write command and a read command sent out from a host and for sending out the write command and the read command to the first storage and the second storage, a determining unit for sending out a request corresponding to the write command to the first storage and the second storage, for receiving a first response corresponding to the request from the first storage and a second response corresponding to the request from the second storage, and for determining one of the storages on the basis of each of response times, a first writing unit for writing data into the determined storage, and a second writing unit for writing the data written in the determined storage into the other storage after writing the data into the determined storage by the first writing unit. | 2010-12-30 |
20100332773 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device comprises includes a program unit configured to generate program data, information about the number of program data, and digital sum value information (hereinafter referred to as ‘DSVi’) of the program data, a memory unit configured to store or read the program data, the information about the number of program data, and the DSVi the program data, and a data read control circuit configured to read program data programmed into the memory unit, generate digital sum value information (hereinafter referred to as ‘DSVo’) of the read program data, and generate a read voltage control signal using the DSVi of the program data, the DSVo of the read program data, and the information about the number of program data. | 2010-12-30 |
20100332774 | COMBINED PARALLEL/SERIAL STATUS REGISTER READ - Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command. | 2010-12-30 |
20100332775 | HYBRID INTERLEAVING IN MEMORY MODULES - A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module. | 2010-12-30 |