52nd week of 2021 patent applcation highlights part 74 |
Patent application number | Title | Published |
20210408175 | PIXEL UNIT, MANUFACTURING METHOD, AND DISPLAY DEVICE - The present invention discloses a pixel unit, a manufacturing method, and a display device. The pixel unit includes a first positive electrode layer, a first pixel definition layer disposed on the first positive electrode layer, a second positive electrode layer disposed on the first pixel definition layer, and a second pixel definition layer disposed on the second positive electrode layer such that the first positive electrode layer and the second positive electrode layer are driven individually. The present invention, by employing two anode driving voltages in the same sub-pixel, drives two parts of a light emitting material individually to improve a brightness in a central region such that the entire pixel emits light evenly. | 2021-12-30 |
20210408176 | ORGANIC LIGHT-EMITTING DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display panel, a manufacturing method thereof, and an organic light-emitting display device are provided. The organic light-emitting display panel includes a substrate, a plurality of anode electrodes, a pixel definition layer, an electron transport layer, and a cathode electrode. The pixel definition layer surrounds to form a plurality of array-distributed grooves, and the anode electrodes are disposed in the grooves one by one. The pixel definition layer includes first retaining walls, second retaining walls, and third retaining walls. At least one compartment is formed among a first organic light-emitting layer, a second organic light-emitting layer, and a third organic light-emitting layer disposed on the anode electrodes. | 2021-12-30 |
20210408177 | DISPLAY BACK PANEL, MANUFACTURING METHODS THEREOF, AND DISPAY DEVICE - A display back panel may include a substrate, an insulating layer disposed on one side of the substrate and including a plurality of recesses, the plurality of recesses including a bottom surface, a first electrode disposed on a surface of the insulating layer away from the substrate, a pixel defining layer disposed on a surface of the first electrode away from the substrate and including a plurality of openings, a light-emitting layer disposed in the plurality of openings and covering the first electrode, and a second electrode disposed on a surface of the light-emitting layer away from the substrate. Therein, the first electrode may reflect waveguide light laterally propagated by the light-emitting layer, thereby improving a light-emitting efficiency of the light-emitting layer. Further, the reflected waveguide light may not be absorbed by the second electrode, thereby enhancing an external quantum effect of the light-emitting layer. | 2021-12-30 |
20210408178 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present disclosure provides a display panel and a manufacturing method thereof. The display panel includes at least a part of metal layer disposed in a bonding area. The metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer disposed in sequence and in a stack. A material used as the first sub-metal layer and the third sub-metal layer is one of molybdenum, titanium, or molybdenum-titanium alloy, and a material used as the second sub-metal layer is copper. The display panel provided by the present disclosure can solve problems that metal silver in the bonding area cannot be exposed outside and metal copper exposed outside is easily oxidized. | 2021-12-30 |
20210408179 | DISPLAY PANEL - The present invention provides a display panel, and the display panel includes an array substrate, a drain metal layer disposed on the array substrate, a flat layer disposed on the drain metal layer, and a pixel defining layer and light-emitting device layer disposed on the flat layer. The pixel defining layer includes a first pixel defining layer located in a display region of the display panel, and a second pixel defining layer located in an edge region of a side portion of the display region. A packaging layer is disposed on the first pixel defining layer, and a blocking structure is disposed on the second pixel defining layer. | 2021-12-30 |
20210408180 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - A display panel may include a substrate ( | 2021-12-30 |
20210408181 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a light-emitting functional layer including a first light-emitting functional portion and a second light-emitting functional portion adjacent to each other; and a photo spacer (PS), the PS is located between the first light-emitting functional portion and the second light-emitting functional portion, the PS includes a plurality of protrusions protruded in a direction away from the base substrate and a first recess located between adjacent protrusions. | 2021-12-30 |
20210408182 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a display panel configured to display an image on a first surface of the display panel, and including: a first display area including a first sub-pixel area, and having a first resolution; and a second display area including a second sub-pixel area and a first transmission area, and having a second resolution that is lower than the first resolution; and a first optical sensor on a second surface of the display panel opposite to the first surface to overlap with the second display area. Accordingly, an image may be displayed at a portion where the first optical module is disposed. | 2021-12-30 |
20210408183 | DISPLAY PANEL, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - A display panel includes a substrate, and a pixel defining layer and a cathode layer that are laminated on the substrate. The pixel defining layer includes a plurality of strip-shaped first pixel defining structures and a plurality of strip-shaped second pixel defining structures. A slope angle of the second pixel defining structure is greater than a slope angle of the first pixel defining structure, and the second pixel defining structure is configured to separate portions of the cathode layer on two sides of the second pixel defining structure. | 2021-12-30 |
20210408184 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display panel and an organic light emitting diode display device are provided. The display panel includes a first display region and a second display region disposed adjacent to the first display region. A thin film transistor layer is disposed on the first substrate layer. A display function of the second display region is controlled by the thin film transistor of the first display region. Thus, the second display region is ensured to normally display images, a layered structure of the second display region is simplified, and a light transmittance of the second display region is improved. The functional requirements of front-facing photosensitive elements, such as cameras, can be met, so that it is conducive to achieve full-screen display. | 2021-12-30 |
20210408185 | ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE - An organic light-emitting diode display device is provided, which includes a base layer, a device layer, a pixel layer, an encapsulation layer, and a camera, wherein the camera is disposed on a back side of the base layer, and the pixel layer includes an anode layer, a pixel definition layer, and a cathode layer. A nanopore array is provided in a region of the anode layer corresponding to the camera, and the nanopore array is configured to allow external light to be transmitted to the camera through the anode layer to implement camera function of the camera. Selective transmission of light can be achieved by adjusting size of nanopores in the nanopore array, so that the display device positioned above the camera can display a picture normally, which is beneficial to achieving a full-screen display. | 2021-12-30 |
20210408186 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A method of manufacturing a display substrate includes: forming a switch unit on a base substrate; forming a planarization layer on one side of the switch unit away from the base substrate, wherein a region, corresponding to an output electrode, of the planarization layer is provided with a planarization layer via hole, and an orthographic projection of the planarization layer via hole onto the base substrate is located within an orthographic projection region of the output electrode onto the base substrate; etching a surface of a region, corresponding to the planarization layer via hole, of the output electrode; and forming a pixel electrode on one side of the planarization layer away from the switch unit, wherein the pixel electrode is in contact with the output electrode through the planarization layer via hole. | 2021-12-30 |
20210408187 | ORGANIC LIGHT-EMITTING DIODE SUBSTRATE - An organic light-emitting diode (OLED) display panel is provided and includes a plurality of pixel regions spaced apart from each other. Each of the pixel regions includes an active region and a non-active region surrounding the active region. The active region includes a base substrate, a thin-film transistor (TFT) layer disposed on the base substrate, a planarization layer disposed on the TFT layer, and an anode disposed on the planarization layer. The anode is in contact with the TFT layer via an anode connection hole that passes through the planarization layer. The non-active area is provided with a photosensor placement region on the non-active area and the photosensor placement region is spaced apart from the anode connection hole. | 2021-12-30 |
20210408188 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate and a manufacturing method thereof are provided. The array substrate includes a flexible substrate, a plurality of thin film transistors, a plurality of replacement units, an organic filling layer, a source and drain layer, a planarization layer, an anode layer, and a pixel definition layer. The organic filling layer is made of a flexible material which has good bendability. Thus, a risk of breakage or crack during a bending process is reduced, thereby realizing a dynamic folding of the array substrate. | 2021-12-30 |
20210408189 | DISPLAY PANEL - A display panel is provided, which includes a display area, an encapsulation area, and a frame area, wherein the encapsulation area includes a first encapsulation area and a second encapsulation area, multiple layers of crack prevention structures are disposed in sequence in the frame area and the second encapsulation area and on a side of the first encapsulation area adjacent to the frame area, and each of the multiple layers of the crack prevention structures are present as a dashed circle structure, and includes at least one groove, and the organic layer fills the groove, and wherein grooves of one layer of the multiple layers of the crack prevention structures and grooves of another layer of the multiple layers of the crack prevention structures adjacent to the one layer are mutually staggered. | 2021-12-30 |
20210408190 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An array substrate, a manufacturing method thereof and an organic light emitting diode display device are provided. The manufacturing method of the array substrate includes forming a first thin film transistor including a first semiconductor pattern, including forming a first electrode pattern including a first source electrode and a first drain electrode and a second electrode pattern including a first auxiliary source electrode and a first auxiliary drain electrode respectively through two patterning processes; forming a second thin film transistor including forming a second source electrode and a second drain electrode through one patterning process. The second electrode pattern, the second source electrode and the second drain electrode are formed in the same patterning process, the first electrode pattern is connected with the first semiconductor patterns. | 2021-12-30 |
20210408191 | DISPLAY PANEL AND ELECTRONIC DEVICE - The present application provides a display panel and an electronic device, wherein by setting a ratio of a vertical distance from a center point of the additional functional area to one of the first side and the third side to a vertical distance between the first side and the third side ranging from 1/10 to 1/2 and a ratio of a vertical distance from the center point of the additional functional area to one of the second side and fourth side to a vertical distance between the second side and fourth side ranging from 1/10 to 1/2. | 2021-12-30 |
20210408192 | OLED DISPLAY DEVICE AND MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE - An OLED display device including an OLED pixel driving circuit is provided. A driving thin film transistor in the OLED pixel driving circuit is configured as a double gate oxide thin film transistor, and a switch thin film transistor is configured as a top gate self-aligned oxide thin film transistor. A manufacturing method of a TFT array substrate is also provided, and the TFT array substrate is used for preparing the OLED display device. | 2021-12-30 |
20210408193 | DISPLAY DEVICE - A display device, including an irregularly-shaped display area disposed with a plurality of irregularly-shaped display pixels and at least one attachment device; and a pixel display area disposed adjacent to the irregularly-shaped display area; wherein each of the irregularly-shaped display pixels comprises an irregularly-shaped gate disposed below a driving thin-film transistor, and the irregularly-shaped gate changes a light-emitting brightness of the irregularly-shaped display pixel according to an adjustment voltage signal to balance light-emission uniformity of the irregularly-shaped display area and the pixel display area. | 2021-12-30 |
20210408194 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure provides a display panel and a display device. The display panel includes a display area, including a first display area. The first display area includes light non-transmissive areas and light transmissive areas, and sub-pixels in the light non-transmissive areas include a first light-shielding layer, a pixel driving circuit, and a light-emitting structure layer. In a direction perpendicular to a substrate, a projection of the first light-shielding layer covers a projection of the light-emitting structure layer and a projection of at least one transistor of the pixel driving circuit. | 2021-12-30 |
20210408195 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view. | 2021-12-30 |
20210408196 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure provides a display panel and a display device. The display panel includes pixel circuits arranged in a matrix, and a blocking unit. Each pixel circuit includes: a driving transistor; a first switch transistor; a second switch transistor; and a third switch transistor. The blocking unit is configured to receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion, the first semiconductor connection portion is connected between a second electrode of the first switch transistor and a gate electrode of the driving transistor, and the second semiconductor connection portion is electrically connected between a first electrode of the second switch transistor and a data line. | 2021-12-30 |
20210408197 | DISPLAY APPARATUS AND PREPARATION METHOD THEREOF - The present disclosure relates to a display apparatus. The display apparatus may include a plurality of display units, each of the plurality of display units including at least one pixel, and a plurality of connectors that connect the plurality of display units to one another. The plurality of connectors and the plurality of display units may form a mesh distribution structure and, when the mesh distribution structure is stretched in a first direction, the mesh distribution structure may be configured to expand in a second direction perpendicular to the first direction. | 2021-12-30 |
20210408198 | Chip Structure and Display Device - A chip structure includes a chip substrate and a plurality of bumps. The plurality of bumps are disposed on a surface of the chip substrate and function as an interface for electrical connection between the chip substrate and an external connecting portion. The plurality of bumps are spaced apart from each other, and each of the plurality of bumps includes a rhombic configuration. | 2021-12-30 |
20210408199 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure provides a display panel and a display device. A through-hole is defined in a bending area of the display panel, and after the bending area is bent along a bending center line, the through-hole forms a light transmitting area, and the light transmitting area is disposed on a light path of an electronic component. Based on the light transmitting area formed after bending the through-hole, the electronic component can be disposed under the display panel, thereby achieving a narrow frame design. | 2021-12-30 |
20210408200 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention provides a display panel and a display device. The display panel includes a main display region and at least one function add-on region, the function add-on region includes at least one display light-transmitting region, a plurality of first pixel driving circuits are disposed at a periphery of the display light-transmitting region, and a multiple layers transparent lines is disposed to electrically connect a first pixel anode and the first pixel driving circuits to drive first display pixels to emit light, which is beneficial for increasing wiring space, as well as improving light transmittance, photographing effect, and display effect of under-screen cameras. | 2021-12-30 |
20210408201 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The disclosure provides a display panel, a manufacturing method thereof, and a display device. A display area is defined on a surface of the display panel, and a first electricity supply area and a second electricity supply area are disposed opposite to each other at two sides of the display area. The display panel includes a substrate layer, and a first metal layer and a second metal layer which are sequentially disposed on the substrate layer, and an insulating layer is further disposed between the first metal layer and the second metal layer in the display area. | 2021-12-30 |
20210408202 | ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - An array substrate is provided. The array substrate includes a data line; a first voltage supply line; a second voltage supply line; and a pixel driving circuit. The pixel driving circuit includes one or more transistors in a first group and one or more transistors in a second group. A source electrode and a drain electrode of at least one transistor in the first group, the data line, the first voltage supply line, and the second voltage supply line are in a same layer. A source electrode and a drain electrode of at least one transistor in the second group are in a layer different from the first voltage supply line and the second voltage supply line. | 2021-12-30 |
20210408203 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device. The display substrate includes a plurality of sub-pixel groups and a plurality of signal line groups. The plurality of signal line groups are arranged along a first direction and are spaced apart from each other, each of the signal line groups includes at least one signal line, and the signal line extends along a second direction intersecting the first direction. Each of the sub-pixel groups includes a first sub-pixel, and the first sub-pixel includes a first anode and a first effective light-emitting region, the first anode includes a first main portion, and the first main portion at least partially overlaps with the first effective light-emitting region, a size of the first main portion in the first direction is larger than a size of the first main portion in the second direction, and the first anode overlaps with two adjacent signal line groups. | 2021-12-30 |
20210408204 | STRETCHABLE DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF FABRICATING STRETCHABLE DISPLAY PANEL - A stretchable display panel is provided. The stretchable display panel includes a plurality of encapsulated islands; and a plurality of bridges connecting the plurality of encapsulated islands. A respective one of the plurality of bridges connects two adjacent encapsulated islands of the plurality of encapsulated islands along an extension direction from a first one of the two adjacent encapsulated islands to a second one of the two adjacent encapsulated islands, The respective one of the plurality of bridges includes a plurality of first parts and a plurality of second parts alternately arranged. The stretchable display panel includes an insulating layer. The insulating layer includes a plurality of insulating blocks respectively in the plurality of first parts, The insulating layer is at least partially absent in the respective one of the plurality of second parts. | 2021-12-30 |
20210408205 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting functional layer. The first electrode pattern is located in a display region and includes a plurality of first electrodes spaced apart from each other. The connecting electrode pattern is located in a peripheral and includes a plurality of connecting electrodes. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode, the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other. | 2021-12-30 |
20210408206 | DISPLAY PANEL AND DISPLAY DEVICE - Provided are a display panel including: a first component, a second component, and a bending component connecting the first component and the second component; wherein, the first component has a display surface, and the bending component has a via passing through the bending component in a direction perpendicular to the display surface. A display device is also provided. | 2021-12-30 |
20210408207 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided, and the display panel includes a bonding area, a thin film transistor functional layer, and a conductive layer disposed in order. A part of the thin film transistor functional layer disposed on the bonding area includes a first inorganic layer and a plurality of signal lines. The conductive layer includes a second inorganic layer and a conductive layer disposed in order, and a part of the second inorganic layer disposed in the bonding area is disposed on the signal line and is directly disposed on the first inorganic layer. | 2021-12-30 |
20210408208 | DISPLAY DEVICE - A display device includes: scan lines extending in a first direction; data lines extending in a second direction intersecting the first direction and receiving data voltages; first driving voltage lines extending in the second direction and receiving a first driving voltage; second driving voltage lines extending in the second direction and receiving a second driving voltage different from the first driving voltage; and pixels connected to the scan and data lines. Each of the pixels includes first, second, and third subpixels arranged in the first direction. The first driving voltage lines and the second driving voltage lines are alternately arranged in the first direction. A location of the first driving voltage line in a first pixel differs from a location of the second driving voltage line in a second pixel. The second pixel is adjacent to the first pixel in the first direction. | 2021-12-30 |
20210408209 | DISPLAY DEVICE - A display device includes: a substrate; a driving voltage line and a data line that are on the substrate; a semiconductor layer that includes a first electrode, a channel, and a second electrode of a driving transistor, the driving transistor being connected to the driving voltage line; a gate electrode of the driving transistor overlapping the channel; a lower storage electrode extending from the gate electrode; and an upper storage electrode overlapping the lower storage electrode, wherein the semiconductor layer further includes a first electrode, a channel, and a second electrode of a switching transistor, the switching electrode being connected between the lower storage electrode and the data line, the upper storage electrode does not overlap the channel of the driving transistor, the lower storage electrode includes a first portion and a second portion that are at opposite sides of the gate electrode. | 2021-12-30 |
20210408210 | DISPLAY DEVICE - A display panel includes a first area in which first pixels of a first pixel column, second pixels of a second pixel column, and third pixels of a third pixel column are arranged, a second area which cuts off each of the first pixel column, the second pixel column, and the third pixel column and through which an optical signal travels, and first to third data lines. The first data line is connected to the first pixels and a portion of the third pixels arranged on one side of the second area in a direction in which the pixel columns extend, the second data line is connected to the second pixels, and the third data line is connected to a remaining portion of the third pixels arranged on the other side of the second area in the direction in which the pixel columns extend. | 2021-12-30 |
20210408211 | DISPLAY DEVICE - A display device including a display area configured to display an image, a first non-display area disposed adjacent to the display area, a second non-display area disposed adjacent to the first non-display area, and a first driving voltage line disposed in the first non-display area and the second non-display area, the first driving voltage line being configured to be applied with a first driving voltage and includes a first sub-driving voltage line including first holes, and a second sub-driving voltage line disposed on the first sub-driving voltage line and including second holes, in which the second holes include first sub-holes and second sub-holes having a different size than the first sub-holes. | 2021-12-30 |
20210408212 | FLEXIBLE DISPLAY SCREEN AND DISPLAY DEVICE - The present disclosure provides a flexible display screen and a display device. The flexible display screen includes an array substrate and a chip bounding to the array substrate; the chip includes an output end and an input end; a total area of a contact surface between the array substrate and the output end of the chip is equal to a total area of a contact surface between the array substrate and the input end of the chip. | 2021-12-30 |
20210408213 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - A display device according to an embodiment of the present invention includes a display panel having a through hole in a display area including a plurality of pixels. The display panel includes a substrate, and an organic light-emitting diode including a first electrode provided above the substrate for each of the pixels, a second electrode provided over the plurality of pixels, and an organic electroluminescence layer arranged between the first electrode and the second electrode. The through hole penetrates at least the second electrode, and the second electrode includes an oxidized part exposed at an inner surface of the through hole. | 2021-12-30 |
20210408214 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of wiring structures and a plurality of pads. The substrate comprises a display area and a non-display area comprising a bending area. The sub-pixels and data lines are in the display area and electrically connected with each other. The wiring structures are in the bending area and electrically connected with the data lines. At least one wiring structure comprises a plurality of hollow patterns connected successively, each hollow pattern comprises a first conductive part and a second conductive part connected with each other. The plurality of pads are in the non-display area and located on a side of the plurality of wiring structures away from the display area and electrically connected with the plurality of wiring structures. | 2021-12-30 |
20210408215 | DISPLAY DEVICE - A display device including: a first data line arranged in a display area of a substrate and extending in a first direction; a second data line arranged in the display area and extending in the first direction; a connecting line arranged in the display area and including a first portion parallel to the first data line, a third portion parallel to the second data line, and a second portion between the first portion and the third portion, wherein the connecting line is electrically connected to the second data line; and an auxiliary line overlapping the first data line or the second data line. | 2021-12-30 |
20210408216 | DISPLAY PANEL AND DISPLAY DEVICE - Provided are a display panel and a display device. The display panel includes a display area and a non-display area. The non-display area includes a bending area and a binding area. The bending area is located between the display area and the binding area in a first direction. The bending area is provided with a first signal trace. The display panel further includes a substrate and a protection structure. The protection structure includes a first protection structure. The first protection structure includes at least a first protection layer, a second protection layer, and a third protection layer arranged in stack in a second direction, the first protection layer is located on one side of the second protection layer farther from the substrate in the second direction, the third protection layer is located on one side of the second protection layer closer to the substrate. | 2021-12-30 |
20210408217 | DISPLAY PANEL, PACKAGING METHOD THEREOF, AND DISPLAY DEVICE HAVING SAME - A display panel, a packaging method thereof, and a display device having same are described. The display panel has: a substrate having a display region and a non-display region surrounding the display region; electrode lines distributed on a surface of the substrate, and located within the display region; a package covering plate attached to the surface of the substrate having the electrode lines; a double-sided sealant adhered to the package covering plate and the surface of the substrate having the electrode lines; a conductive nanofiber layer disposed between the double-sided sealant and the substrate, and located on the electrode lines of the display region. The conductive nanofiber layer can achieve good surface contact and parallel connection with the electrode lines. Therefore, surface resistance of the electrode lines in the display panel is effectively reduced, and luminous efficiency and brightness uniformity of the display panel are improved. | 2021-12-30 |
20210408218 | ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - An OLED display substrate, a manufacturing method thereof, and a display device are provided. The OLED display substrate includes a base substrate, a conductive pattern, a driving circuit layer, an anode layer, a light-emitting layer and a cathode layer. The driving circuit layer, the anode layer, the cathode layer and the light-emitting layer are arranged at a same side of the base substrate. The conductive pattern is arranged between the base substrate and the driving circuit layer and electrically connected to the cathode layer through a plurality of via holes. | 2021-12-30 |
20210408219 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, DISPLAY SCREEN AND DISPLAY DEVICE - A display panel includes a substrate; multiple first electrode signal lines formed on the substrate; and multiple isolation columns located on a side of the multiple first electrode signal lines facing away from the substrate. The display panel includes multiple pixel regions and multiple partition regions, each of the multiple pixel regions is internally provided with a respective one of the multiple isolation columns, each of the multiple isolation columns are internally provided with multiple pixel openings, and each of the multiple pixel openings is internally provided with a first electrode and a light-emitting function layer located on a side of the first electrode facing away from the substrate, the first electrode is electrically connected to a corresponding one of the multiple first electrode signal lines, and the multiple partition regions are used for partitioning a second electrode between two adjacent pixel regions. | 2021-12-30 |
20210408220 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device comprises a supporting substrate, a flexible substrate disposed on the supporting substrate, a plurality of electronic units and a conductive pattern layer. The flexible substrate is bent from a front side to a back side of the supporting substrate, and a portion of the flexible substrate is disposed on the back side of the supporting substrate. The electronic units are disposed within a display region of the flexible substrate. The conductive pattern layer extends from the display region to the portion of the flexible substrate, and the conductive pattern layer electrically connects at least two of the electronic units. | 2021-12-30 |
20210408221 | GATE IMPLANT FOR REDUCED RESISTANCE TEMPERATURE COEFFICIENT VARIABILITY - Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero. | 2021-12-30 |
20210408222 | SEMICONDUCTOR DEVICE - A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher. | 2021-12-30 |
20210408223 | FERROELECTRIC TUNNEL JUNCTION DEVICES WITH DISCONTINUOUS SEED STRUCTURE AND METHODS FOR FORMING THE SAME - A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer. | 2021-12-30 |
20210408224 | CRYSTALLINE BOTTOM ELECTRODE FOR PEROVSKITE CAPACITORS AND METHODS OF FABRICATION - A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy. | 2021-12-30 |
20210408225 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode. | 2021-12-30 |
20210408226 | METAL CAPACITOR - A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor. | 2021-12-30 |
20210408227 | TRANSITION METAL DICHALCOGENIDE NANOWIRES AND METHODS OF FABRICATION - A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer. | 2021-12-30 |
20210408228 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes: a substrate is provided; a barrier layer is formed on an upper surface of the substrate, and a proportion of crystal orientation <111> in crystal orientations of the barrier layer is at least a preset value; and a metal material layer is formed on an upper surface of the barrier layer, crystal orientations of the metal material layer including a crystal orientation <111>. | 2021-12-30 |
20210408229 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer. | 2021-12-30 |
20210408230 | ISOLATION STRUCTURES FOR TRANSISTORS - The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer. | 2021-12-30 |
20210408231 | Semiconductor Device and Method - In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void. | 2021-12-30 |
20210408232 | INTEGRATED CIRCUIT DEVICE INCLUDING GATE LINE - An integrated circuit device includes an active area extending in a first direction on a substrate and a gate line extending in a second direction intersecting with the first direction to intersect with the active area. The gate line comprises a first sidewall and a second sidewall opposite to each other. The first sidewall has a convex shape. The second sidewall has a concave shape. | 2021-12-30 |
20210408233 | TRANSISTOR HAVING STACKED SOURCE/DRAIN REGIONS WITH FORMATION ASSISTANCE REGIONS AND MULTI-REGION WRAP-AROUND SOURCE/DRAIN CONTACTS - Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers. | 2021-12-30 |
20210408234 | HIGH-VOLTAGE NANO-SHEET TRANSISTOR - The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure. | 2021-12-30 |
20210408235 | SEMICONDUCTOR DEVICE WITH SILICIDE GATE FILL STRUCTURE - A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process. | 2021-12-30 |
20210408236 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region; first nanowires formed over the first region of the semiconductor substrate; second nanowires with a diameter smaller than a diameter of the first nanowires formed over the second region of the semiconductor substrate; a first gate layer formed around the first nanowires; and a second gate layer formed around the second nanowires. | 2021-12-30 |
20210408237 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer. | 2021-12-30 |
20210408238 | DOUBLE MESA HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter. | 2021-12-30 |
20210408239 | PLASMA NITRIDATION FOR GATE OXIDE SCALING OF GE AND SIGE TRANSISTORS - Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor channels with a first end and second end. In an embodiment, individual ones of the semiconductor channels comprise a nitrided surface. In an embodiment, the semiconductor device further comprises a source region at the first end of the stack and a drain region at the second end of the stack. In an embodiment, a gate dielectric surrounds the semiconductor channels, and a gate electrode surrounding the gate dielectric. | 2021-12-30 |
20210408240 | FIELD EFFECT TRANSISTOR WITH CONTROLLABLE RESISTANCE - A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer. | 2021-12-30 |
20210408241 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width. | 2021-12-30 |
20210408242 | SEMICONDUCTOR FILM - Provided is a semiconductor film having a corundum-type crystal structure composed of α-Ga | 2021-12-30 |
20210408243 | Contact Structure for Power Semiconductor Devices - A transistor device includes field plate contacts that electrically connect overlying contact pads to field electrodes in underlying trenches, and mesa contacts that electrically connect the contact pads to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts. | 2021-12-30 |
20210408244 | FIELD-EFFECT TRANSISTORS AND METHODS OF THEIR FORMATION - Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon. | 2021-12-30 |
20210408245 | MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE/DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD - A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure. | 2021-12-30 |
20210408246 | CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES - Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer. | 2021-12-30 |
20210408247 | SOURCE/DRAIN CONTACTS AND METHODS OF FORMING SAME - A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact. | 2021-12-30 |
20210408248 | RADIO FREQUENCY SWITCH - A radio frequency (RF) switch is provided. The RF switch is configured to switch a RF signal input to a first terminal. The RF switch includes a first transistor, disposed at a first distance from the first terminal, and configured to switch the RF signal, and a second transistor, disposed at a second distance from the first terminal, and configured to switch the RF signal. The first distance is shorter than the second distance, and a number of first contact vias formed in a first electrode in the first transistor is greater than a number of second contact vias formed in a second electrode of the second transistor. | 2021-12-30 |
20210408249 | Semiconductor Device and Method of Forming Thereof - A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact. | 2021-12-30 |
20210408250 | METHOD OF DISTRIBUTING METAL LAYERS IN A POWER DEVICE - A metal distributing method of a FET (Field Effect Transistor) device, having: depositing a first dielectric layer on a planar silicon surface; etching a first level metal layer pattern in the first dielectric layer; filling in a first level metal layer in openings determined by the first level metal layer pattern; depositing a second dielectric layer on the first dielectric layer and the first level metal layer; etching a second level metal layer pattern in the second dielectric layer; and filling in a second level metal layer in openings determined by the second level metal layer pattern; the first level metal layer and the second level metal layer are contacted directly, with no via layer in between. | 2021-12-30 |
20210408251 | SEMICONDUCTOR DEVICE WITH T-SHAPED BURIED GATE ELECTRODE AND METHOD FOR FORMING THE SAME - The present disclosure provides a semiconductor device with a T-shaped buried gate electrode and a method for forming the semiconductor device. The semiconductor device includes a semiconductor substrate having an active region, and a first gate electrode disposed in the semiconductor substrate. The semiconductor device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the first gate electrode. The first gate electrode has a first portion extending across the active region and a second portion extending into the first source/drain region. | 2021-12-30 |
20210408252 | TRI-GATE ORTHOGONAL CHANNEL TRANSISTOR AND METHODS OF FORMING THE SAME - A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer. | 2021-12-30 |
20210408253 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole. | 2021-12-30 |
20210408254 | SEMICONDUCTOR DEVICES INCLUDING CAPPING LAYER - A semiconductor device includes first and second active regions on a substrate, an element isolation layer between the first and second active regions, a dummy gate line, dummy gate spacers at opposite side walls of the dummy gate line, and a dummy gate capping layer on the dummy gate line and. An upper surface of the element isolation layer is proximate to an upper surface of the substrate in relation to an upper end of the first active region in a vertical direction. The dummy gate line includes a horizontal section extending on the first active region to the element isolation layer in a horizontal direction, and a vertical section extending downwards from the horizontal section along a side wall of the first active region, the dummy gate line having an L shape, a vertical thickness of the horizontal section being smaller than a vertical thickness of the vertical section. | 2021-12-30 |
20210408255 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer. | 2021-12-30 |
20210408256 | ANTENNA-FREE HIGH-K GATE DIELECTRIC FOR A GATE-ALL-AROUND TRANSISTOR AND METHODS OF FORMING THE SAME - A gate-all-around field effect transistor may be provided by forming a sacrificial gate structure and a dielectric gate spacer around a middle portion of a semiconductor plate stack. A source region and a drain region may be formed on end portions of semiconductor plates within the semiconductor plate stack. The sacrificial gate structure and other sacrificial material portions may be replaced with a combination of a gate dielectric layer and a gate electrode. The gate dielectric layer and the gate electrode may be vertically recessed selective to the dielectric gate spacer. A first anisotropic etch process recesses the gate electrode and the gate dielectric layer at about the same etch rate. A second anisotropic etch process with a higher selectivity may be subsequently used. Protruding remaining portions of the gate dielectric layer are minimized to reduce leakage current between adjacent transistors. | 2021-12-30 |
20210408257 | PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON DEVICES - Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels. | 2021-12-30 |
20210408258 | INTEGRATED CIRCUIT STRUCTURES INCLUDING A TITANIUM SILICIDE MATERIAL - Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi | 2021-12-30 |
20210408259 | GATE STRUCTURE AND METHOD - A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer. | 2021-12-30 |
20210408260 | SEMICONDUCTOR DEVICES HAVING MULTIPLE BARRIER PATTERNS - Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal. | 2021-12-30 |
20210408261 | VERTICAL TRANSISTOR HAVING AN OXYGEN-BLOCKING TOP SPACER - Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material. | 2021-12-30 |
20210408262 | Stacked Gate Spacers - The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material. | 2021-12-30 |
20210408263 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature. | 2021-12-30 |
20210408264 | SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with a programmable feature such as anti-fuse and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer including a peak portion and an upper portion positioned on the peak portion, and first conductive blocks positioned on two sides of the peak portion. A width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion. | 2021-12-30 |
20210408265 | METAL OXIDE SEMICONDUCTOR-CONTROLLED THYRISTOR DEVICE HAVING UNIFORM TURN-OFF CHARACTERISTIC AND METHOD OF MANUFACTURING THE SAME - The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation. | 2021-12-30 |
20210408266 | Air Spacer and Method of Forming Same - In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap. | 2021-12-30 |
20210408267 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH ANNULAR SEMICONDUCTOR FIN - A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin. | 2021-12-30 |
20210408268 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device comprising: providing a substrate, wherein an amorphous silicon layer is formed on the substrate; forming an etching auxiliary layer on the amorphous silicon layer, wherein the upper surface of the etching auxiliary layer is flat, and the etching auxiliary layer is made of a single material; and etching the amorphous silicon layer and the etching auxiliary layer to obtain an amorphous silicon layer with a target thickness, wherein the upper surface of the etched amorphous silicon layer is flat. | 2021-12-30 |
20210408269 | MANUFACTURING METHOD OF CMOS INVERTER - The present disclosure provides a manufacturing method of a complementary metal-oxide-semiconductor (CMOS) inverter includes annealing a substrate printed with an oxide ink to obtain a first active layer, printing a carbon tube ink between a first source and the first drain to form a second active layer for obtaining a first thin-film transistor (TFT), forming a second source and a second drain on two sides of the first active layer to obtain a second TFT, and forming wires between the first TFT and the second TFT. | 2021-12-30 |
20210408270 | SILICIDE-BLOCK-RING BODY LAYOUT FOR NON-INTEGRATED BODY LDMOS AND LDMOS-BASED LATERAL IGBT - An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region. | 2021-12-30 |
20210408271 | SINGLE ELECTRON TRANSISTORS (SETS) AND SET-BASED QUBIT-DETECTOR ARRANGEMENTS - Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands. | 2021-12-30 |
20210408272 | FIELD EFFECT TRANSISTORS INCLUDING QUANTUM LAYERS - Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region. | 2021-12-30 |
20210408273 | INTEGRATED DESIGN FOR III-NITRIDE DEVICES - A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole. | 2021-12-30 |
20210408274 | CONNECTOR VIA STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure. | 2021-12-30 |