53rd week of 2009 patent applcation highlights part 23 |
Patent application number | Title | Published |
20090322377 | METHOD AND SYSTEM FOR SIZING FLOW CONTROL BUFFERS - A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input. | 2009-12-31 |
20090322378 | Electrical Device For Performing Logic Functions - An electronic device is presented for performing at least one logic function. The device comprises an electron emission based electrode arrangement associated with an electron extractor. The electrode arrangement comprises at least one basic unit including a photocathode, an anode, and one or more gates arranged aside a cavity defined between the photocathode and the anode. Said one or more gates are connectable to a voltage supply unit to be operated by one or more input voltages signals corresponding to one or more logical values, respectively. Said anode is operable as a floating electrode from which an electrical output of the device indicative of a resulted logic function is read. The anode is electrically connected to a photocathode of another cathode-anode unit of the same device, or is connected to an electrode of another electronic device. | 2009-12-31 |
20090322379 | PEAK HOLD CIRCUIT - A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor. | 2009-12-31 |
20090322380 | DRIVE CIRCUIT DEVICE FOR A POWER SEMICONDUCTOR, AND SIGNAL TRANSFER CIRCUIT DEVICE FOR USE THEREIN - A power semiconductor drive circuit device includes: an electronic control device generating a control input signal; a signal transfer circuit device having a main path and a self-diagnosis functional block; and a power semiconductor driven by the control output signal from the signal transfer circuit device. The self-diagnosis functional block includes: a feedback pulse transmitter circuit; a second signal transfer circuit; and a second receiver circuit. The second receiver circuit compares the control output signal with the control input signal so as to find out whether the control output signal is matched or unmatched with the control input signal, and then outputs a result to a comparison signal output terminal. A signal outputted to the comparison signal output terminal is transferred to the electronic control device. | 2009-12-31 |
20090322381 | LIGHT RECEIVING CIRCUIT, LIGHT RECEIVING METHOD, AND STORAGE MEDIUM - The PD converts the light into a current signal and supplies the converted a current signal to a TIA and a light intensity measuring unit. The TIA converts the current signal into a voltage signal. The CDR circuit identifies whether the voltage signal is 1 data or 0 data for reproduction. The counter counts the 1 data and 0 data, calculates their ratio. The control unit refers to light intensity data from the light intensity measuring unit and a ROM, acquires an optimum ratio, and determines whether the ratio supplied from the counter is the optimum ratio. When the ratio is not the optimum one, the control unit controls the threshold voltage setting unit to set the threshold voltage so that the ratio is the optimum one. | 2009-12-31 |
20090322382 | Semiconductor Device, Driving Method Thereof and Electronic Device - The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened. | 2009-12-31 |
20090322383 | SEMICONDUCTOR DEVICE, SIGNAL TRANSMITTER, AND SIGNAL TRANSMISSION METHOD - A semiconductor device is provided with a plurality of semiconductor chips and at least one transmission coil ( | 2009-12-31 |
20090322384 | Drive and startup for a switched capacitor divider - Drive and startup circuits are described particularly suitable for use with a switched capacitor divider. In one example, a drive circuit has a level shifter coupled to a gate of each switch of a switched capacitor drive circuit to couple alternating current into the respective gate, a positive phase low side driver coupled to each level shifter to drive the gates of the top switch path through the respective level shifters, and a negative phase low side driver coupled to each level shifter to drive gates of the bottom switch path through the respective level shifters. A startup circuit, such as a capacitive soft start circuit may be used to slow the application of the current to each switch. | 2009-12-31 |
20090322385 | DEVICE HAVING CLOCK GENERATING CAPABILITIES AND A METHOD FOR GENERATING A CLOCK SIGNAL - A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal. | 2009-12-31 |
20090322386 | PROGRAMMABLE DIVIDER APPARATUS AND METHOD FOR THE SAME - A programmable divider apparatus comprises a first divider, a second divider, a feedback control unit, and a plurality of control signals. The first divider provides a frequency division operation of division by at least three integers, the second divider is cascaded to the first divider to provide a frequency division operation of division by two integers. The feedback control unit is coupled to between the first divider and the second divider to provide a feedback control signal to selectively supply an output of the second divider to an input of the first divider. The apparatus control signals and the feedback control signal are used to execute the first divider or the second divider. | 2009-12-31 |
20090322387 | OUTPUT ENABLE SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency. | 2009-12-31 |
20090322388 | MULTI-PHASE CORRECTION CIRCUIT - A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another. | 2009-12-31 |
20090322389 | JITTER ATTENUATING DELAY LOCKED LOOP (DLL) USING A REGENERATIVE DELAY LINE - In general, in one aspect, the disclosure describes a delay locked loop (DLL) with a regenerative delay line that includes a cascade of delay stages. A first delay stage includes a two-input delay device which receives a 180 degree phase shifted signal as feedback. This feedback signal configures the delay line into a regenerative amplifier, the frequency response of which has peaking or resonance at the input frequency which results in jitter filtering. The amount of regeneration is determined by relative strength of an input signal and the feedback signal. Relative strength is determined by relative size of devices receiving the signals. The resonant frequency (with or without oscillations) of the delay line may automatically be tuned to the incoming clock frequency by the DLL control loop. Each of the other delay stages may include two-input delay devices with the inputs shorted for uniformity. | 2009-12-31 |
20090322390 | DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit and a delay locked loop circuit including the same are capable of reducing area and power consumption of a circuit. The delay locked loop circuit includes a delay locked loop unit, a delay controller, a duty cycle ratio correction circuit, and a duty cycle ratio detector. The delay locked loop unit outputs an internal clock by delaying an external clock in order to compensate a clock skew. The delay controller outputs a delay internal clock by delaying the internal clock in response to correction signals. The duty cycle ratio correction circuit outputs an internal correction clock by increasing or decreasing a high level section of the internal clock according to the correction signals. The duty cycle ratio detector outputs the correction signals in accordance with a duty cycle ratio of the internal correction clock. | 2009-12-31 |
20090322391 | PHASE SYNCHRONIZATION APPARATUS - A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells. | 2009-12-31 |
20090322392 | DIGITAL DELAY LOCKED LOOP CIRCUIT - A phase determination section determines the quantity of first fixed delay elements for delaying a clock signal by one cycle and generates a selection signal indicating the determination result. A phase adjustment section determines, based on the selection signal, the quantity of second fixed delay elements for delaying an input signal and generates the output signal by delaying the input signal by a certain phase amount. The phase adjustment section includes a variable delay unit which generates, based on the selection signal, a variable delay time allowing the delay time of the output signal to be adjusted in steps of ½ | 2009-12-31 |
20090322393 | EDGE-TIMING ADJUSTMENT CIRCUIT - According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner. | 2009-12-31 |
20090322394 | RING OSCILLATOR AND MULTI-PHASE CLOCK CORRECTION CIRCUIT USING THE SAME - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 2009-12-31 |
20090322395 | TRANSMISSION PATH DRIVING CIRCUIT - A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit | 2009-12-31 |
20090322396 | CIRCUIT TO REDUCE DUTY CYCLE DISTORTION - A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals. | 2009-12-31 |
20090322397 | DELAY CIRCUIT AND RELATED METHOD THEREOF - A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal. | 2009-12-31 |
20090322398 | Dual-path clocking architecture - A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal. | 2009-12-31 |
20090322399 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 2009-12-31 |
20090322400 | INTEGRATED CIRCUIT WITH NON-CRYSTAL OSCILLATOR REFERENCE CLOCK - An integrated circuit with a non-crystal reference clock includes: an oscillator adapted to generate and transmit an oscillator output signal, wherein the oscillator includes at least one of an inductor, a resistor, and a capacitor; a comparator adapted to receive the oscillator output signal and a calibration input signal, compare the oscillator output signal characteristics and the calibration input signal characteristics, and generate and transmit a first comparator signal in response to the comparison of the oscillator output signal and the calibration input signal, a state machine adapted to receive the first comparator signal, analyze the first comparator signal and calibrate the oscillator in response to the analysis of the first comparator signal, and a controller adapted to the receive the oscillator output signal, wherein a frequency of the oscillator output signal is utilized by the controller as a clock frequency. | 2009-12-31 |
20090322401 | METHOD AND APPARATUS FOR AN EVENT TOLERANT STORAGE CIRCUIT - An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit. | 2009-12-31 |
20090322402 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 2009-12-31 |
20090322403 | MULTIPLE-PHASE, DIFFERENTIAL SAMPLING AND STEERING - Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs. | 2009-12-31 |
20090322404 | Arrangement, Use of an Arrangement, Reference Voltage Source and Method for Generating a Voltage Value Linearly Proportional to the Temperature - The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off. | 2009-12-31 |
20090322405 | Enhanced Transistor Gate Drive - An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off. | 2009-12-31 |
20090322406 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a core circuit, a power supply switch situated on a path providing a current to the core circuit and configured to control a state of current supply to the core circuit in response to a control signal applied to a control node, a clamp circuit configured to clamp a voltage of the control signal, and a switching circuit configured to control whether to enable or disable a clamp operation of the clamp circuit. | 2009-12-31 |
20090322407 | Speed Recognition for Half Bridge Control - Circuit and method for controlling a high bridge circuit with increased efficiency is disclosed. Circuitry is provided outputting gating signals to a high side driver and a low side driver responsive to a time varying input signal. A frequency measurement circuit determines a high speed mode when the input signal is at a frequency above a threshold, and the gating signal to the high side driver is inhibited. When the input signal frequency is below the threshold, the low side driver and the high side driver gating signals switch alternately. In an exemplary implementation, the frequency measurement circuit is provided as two counters outputting signals to a decision circuit which controls the half bridge circuit. Methods are provided for efficiently providing gating signals to the drivers of a half bridge circuit based upon the frequency of the input signal. | 2009-12-31 |
20090322408 | METHOD FOR REDUCING SWITCHING POWER LOSS - A method of controlling a switch in a power converter in order to reduce switching power loss is disclosed. A trigger voltage level is set and the voltage level across the switch V | 2009-12-31 |
20090322409 | Power reduction apparatus and method - Provided is an approach to saving active power through lowering a supply voltage when operating temperature goes up, while substantially maintaining operating performance. | 2009-12-31 |
20090322410 | SYSTEM AND METHOD FOR MONITORING A CAPACITIVE SENSOR ARRAY - A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes. | 2009-12-31 |
20090322411 | CIRCUIT AND METHOD FOR AVOIDING SOFT ERRORS IN STORAGE DEVICES - A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement. | 2009-12-31 |
20090322412 | SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE - Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog. | 2009-12-31 |
20090322413 | Techniques of Ripple Reduction for Charge Pumps - A charge pump system for supplying an output voltage to a load is described. It includes a regulation circuit connected to receive the output voltage and derive an enable signal from it and multiple charge pump circuits connected in parallel to supply the output voltage. Each of the charge pump circuits is also connected to receive a clock signal and the enable signal. The system also includes one or more delay circuit elements, where a corresponding one or more, but less than all, of the charge pump circuits are connectable to receive the enable signal delayed by the corresponding delay circuit element. | 2009-12-31 |
20090322414 | INTEGRATION OF SWITCHED CAPACITOR NETWORKS FOR POWER DELIVERY - Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module. | 2009-12-31 |
20090322415 | Regulated Energy Supply for a Circuit - The device ( | 2009-12-31 |
20090322416 | Bandgap voltage reference circuit - A voltage reference circuit is provided with: an operational amplifier circuit; first and second resistor elements; first and second diodes; and first and second transistors. The first resistor element and the first diode are connected in series between a first input terminal of the operational amplifier circuit and a reference level node. The second resistor element and the second diode are connected in series between a second input terminal of the operational amplifier circuit and the reference level node. The first transistor is connected between a power supply node and the first input terminal of the operational amplifier circuit and has a control electrode receiving an output of the operational amplifier circuit. The second transistor is connected between the power supply node and the second input terminal of the operational amplifier circuit and has a control electrode receiving the output of the operational amplifier circuit. The value of R12·ln(n11·n22)/(R12·n12·R11) is adjusted to approximately 23.25, where R11 and R12 are resistance values of the first and second resistor elements, n11 is a ratio of an area of a p-n junction of the second diode to an area of a p-n junction of the first diode, and n12 is a ratio of a W/L ratio of the first transistor to a W/L ratio of the second transistor. | 2009-12-31 |
20090322417 | SEMICONDUCTOR COMPONENT ARRANGEMENT HAVING A COMPONENT WITH A DRIFT ZONE AND A DRIFT CONTROL ZONE - Disclosed is a semiconductor including a component having a drift zone and a drift control zone. A first connection zone is adjacent to the drift zone and is doped more highly than the drift zone. A drift control zone is arranged adjacent to the drift zone and is coupled to the first connection zone. A drift control zone is dielectric arranged between the drift zone and the drift control zone. At least one rectifier element is arranged between the first connection zone and the drift control zone. A charging circuit is connected to the drift control zone. | 2009-12-31 |
20090322418 | DISCRETE TIME MULTI-RATE ANALOG FILTER - A discrete time analog filter suitable for use in a receiver and other electronics devices is described herein. In one exemplary design, an apparatus may include a transconductance amplifier, a sampler, and a discrete time analog filter. The transconductance amplifier may amplify a voltage input signal and provide an analog signal. The sampler may sample the analog signal and provide analog samples at a sampling rate. The discrete time analog filter may filter the analog samples and provide filtered analog samples either at the sampling rate for a non-decimating filter or at an output rate that is lower than the sampling rate for a decimating filter. The discrete time analog filter may also filter the analog samples with either equal weights for a rectangular filter or at least two different weights for a weighted filter. | 2009-12-31 |
20090322419 | AMPLIFYING APPARATUS USING MAGNETO-RESISTIVE DEVICE - An amplifying apparatus includes a magneto-resistive device which has a magnetic free layer, a magnetic pinned layer having a magnetic moment larger than that of the magnetic free layer, and an intermediate layer provided in between the magnetic free layer and the magnetic pinned layer. The amplifying apparatus has a first electrode layer provided in a magnetic free layer side of the magneto-resistive device, and a second electrode layer provided in a magnetic pinned layer side of the magneto-resistive device. The amplifying apparatus further includes a direct-current bias power-source for applying a direct-current bias to the magneto-resistive device, and a load resistor. The amplifying apparatus continually causes the change of a magnetization direction of the magnetic free layer to make the magneto-resistive device show negative resistance, and thereby amplifies an input signal. | 2009-12-31 |
20090322420 | Feedback Biasing Technique For A Stage Of An Amplifier That Uses A Feedback Control Loop Having Low Gain - According to an aspect of the present invention, a stage of an amplifier contains a positive feedback loop in addition to a negative feedback loop to maintain the bias currents at a desired level in the active components providing the output of the amplifier. The positive feedback loop senses the finite gain (i.e., less than the ideal infinite gain) of the negative feedback loop and compensates for the finite gain. Due to the use of the positive feedback, the duration and extent of deviation of the bias currents from the desired level is reduced, thereby minimizing the distortions in the output of the amplifier. In an embodiment, the stage corresponds to a class AB stage. | 2009-12-31 |
20090322421 | POWER EFFICIENT TRANSMITTER WITH HIGH DYNAMIC RANGE - One embodiment of the present invention relates to a method for transistor matching. The power transmitter comprises a first, second, and third amplification path. The paths are selectively activated and deactivated to output a received signal with high efficiency and linearity. The first amplification path is configured to receive a first signal and output a first amplified signal to a first port of a output power combiner when activated and provide an impedance that results in a high reflection factor when deactivated. The second amplification path is configured to receive a second signal with 90° phase shift with respect to the first signal and output a second amplified signal to a second port of the combiner when activated and provide an impedance that results in a high reflection factor when deactivated. The third amplification path is configured to receive a third signal and output a third amplified signal to a third port of the output power combiner when activated and provide an impedance that results in an impedance that matches the output impedance when deactivated. | 2009-12-31 |
20090322422 | SIGNAL AMPLIFICATION - Apparatus for amplifying a signal, the apparatus comprising an amplifier ( | 2009-12-31 |
20090322423 | METHOD AND SYSTEM FOR POLAR MODULATING QAM SIGNALS WITH DISCONTINUOUS PHASE - Aspects of a method and system for polar modulating QAM signals with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or said amplitude offset gain may be adjusted dynamically and/or adaptively. The signal may be generated by phase-modulation of a radio-frequency carrier. The combined gain of the plurality of amplifiers may be controlled based on a desired amplitude modulation. The plurality of amplifiers may be integrated within an integrated circuit (IC) or chip. | 2009-12-31 |
20090322424 | POWER AMPLIFIER WITH PRE-DISTORTER - Amplifier apparatus comprising a power amplifier having an operating frequency in the radio frequency or microwave or higher ranges and a pre-distorter, the characteristics of the power amplifier comprising a distortion from a linear transfer function. The pre-distorter comprises a non-linear path and a linear path including amplifiers having substantially identical physical characteristics, an input divider responsive to an amplifier input signal for applying respective pre-distorter input signals to the paths, and an output coupler for combining the signals from the linear path and the non-linear path to produce a pre-distorted signal. The characteristics of the pre-distorter comprise a distortion relative to a linear transfer function that compensates for the distortion of the transfer function of the power amplifier. | 2009-12-31 |
20090322425 | Distortion Compensating Amplifier And Front-End Distortion Compensation Amplifying Device - A distortion compensating amplifier including a forward circuit and a feedback circuit and performing distortion compensation of a signal in the forward circuit by use of a gain of the feedback circuit, includes a detecting unit which detects that the gain of the forward circuit is changed, a calculating unit which calculates, when the detecting unit detects that the gain of the forward circuit is changed, the gain of the feedback circuit on the basis of an input signal to the forward circuit and an output signal from the forward circuit, and a feedback gain updating unit which updates the present gain of the feedback circuit with the gain calculated by the calculating unit. | 2009-12-31 |
20090322426 | Output Short Circuit and Load Detection - One embodiment of an apparatus for testing an amplifier includes an amplifier having a driver and a filter, the filter being connected between an output of the driver and an output of the amplifier. The filter is operable to produce a demodulated output signal from a higher frequency modulated signal at the driver output. The apparatus also includes a voltage level detector connected to the driver output and a control circuit operable to detect at least one fault based on a voltage level measured at the driver output by the voltage level detector. | 2009-12-31 |
20090322427 | TRANSISTOR AND ROUTING LAYOUT FOR A RADIO FREQUENCY INTEGRATED CMOS POWER AMPLIFIER DEVICE - An integrated CMOS power amplifier system to improve amplifier performance, the integrated CMOS power amplifier system including a plurality of differential main amplifier cores, a plurality of ground pads, and a plurality of routes to connect the plurality of differential main amplifier cores to the plurality of ground pads. Each differential main amplifier core includes a pair of collocated main amplifier core transistors. Each ground pad is connected to a subset of the differential main amplifier cores. Embodiments of the integrated CMOS power amplifier system decrease parasitic inductance to ground and increase the transconductance and amplification of the integrated CMOS power amplifier system, thus improving performance. | 2009-12-31 |
20090322428 | TUNABLE LINEAR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER - A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals. | 2009-12-31 |
20090322429 | Variable gain current input amplifier and method - Variable gain circuitry includes a first input transistor (M | 2009-12-31 |
20090322430 | SEMICONDUCTOR PACKAGE WITH REDUCED INDUCTIVE COUPLING BETWEEN ADJACENT BONDWIRE ARRAYS - A semiconductor package ( | 2009-12-31 |
20090322431 | SELF-BIASED BIPOLAR RING-OSCILLATOR PHASE-LOCKED LOOPS WITH WIDE TUNING RANGE - Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals. | 2009-12-31 |
20090322432 | FREQUENCY SYNTHESIZER - A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal. | 2009-12-31 |
20090322433 | Method of Controlling Voltage-Controlled Oscillator - The present invention relates to a method for controlling a voltage-controlled oscillator (VCO), which uses a control unit to produce a switching signal according to a counting signal for switching a plurality of current sources. The VCO receives the currents of the plurality of current sources and a reference current and produces an output frequency signal. Thereby, according to the present invention, the counting signal is used for controlling the currents of the plurality of current sources, and thus the frequency range of the output frequency signal can be controlled. The output frequency band of the VCO is broadened accordingly. | 2009-12-31 |
20090322434 | CONTROL METHOD FOR OPERATION MODES OF OSCILLATOR AND THE APPARATUS THEREOF - The present invention relates to a control method for the operation modes of an oscillator and the apparatus thereof, for which the method and the apparatus can be applied to the electronic circuits with multi-operation modes of the oscillator so as to correctly choose the desirable oscillator operation mode. Furthermore, an oscillator checking circuit sets up the oscillation mode automatically and judges if the oscillator operates properly. Hence, there is no need for the user to set up the oscillator operation mode manually. | 2009-12-31 |
20090322435 | DIGITALLY CONTROLLED OSCILLATORS - Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors. | 2009-12-31 |
20090322436 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator comprises an inductor and a group of variable capacitance elements forming a resonance circuit. The group of variable capacitance elements includes first and second variable capacitance elements connectable in parallel and having mutually different absolute values of a ratio of control-voltage sensitivity to capacitance. The first and second variable capacitance elements both have a first end supplied with a control voltage for controlling resonance frequency of the resonance circuit and have a second end selectively connected to the inductor by a band selection signal for deciding a band in which the resonance frequency exists. | 2009-12-31 |
20090322437 | SYSTEM, METHOD AND APPARATUS EMPLOYING CRYSTAL OSCILLATOR - In some embodiments, an apparatus and system includes a substrate including outer surfaces, one of the outer surfaces defining a first plurality of electrical contacts, one of the outer surfaces adapted to be mounted to a circuit board and defining a second plurality of electrical contacts adapted to be electrically connected to the circuit board; an integrated circuit die mounted to one of the outer surfaces, and a crystal oscillator mounted to one of the outer surfaces and electrically connected to the integrated circuit die. In some embodiments, a method includes providing a substrate including outer surfaces, one of the outer surfaces defining a first plurality of electrical contacts, one of the outer surfaces adapted to be mounted to a circuit board and defining a second plurality of electrical contacts adapted to be electrically connected to the circuit board; mounting an integrated circuit die to one of the outer surfaces, mounting a crystal oscillator to one of the outer surfaces; and electrically connecting the crystal oscillator to the integrated circuit die. | 2009-12-31 |
20090322438 | EXTENDED MULTI-MODULUS PRESCALER - Embodiments of apparatuses, articles, methods, and systems for a synthesizer with an extended multi-modulus prescaler are generally described herein. Other embodiments may be described and claimed. | 2009-12-31 |
20090322439 | PHASE LOCKED LOOP BASED FREQUENCY MODULATOR WITH ACCURATE OSCILLATOR GAIN ADJUSTMENT - A frequency modulator includes a tuning circuit configured to determine a nominal gain characteristic of a digitally controlled oscillator (DCO) in a first mode, and to determine an actual gain characteristic of the DCO in a second mode using the nominal gain characteristic. The frequency modulator also comprises a modulation circuit comprising the DCO coupled to the tuning circuit, configured to modulate a frequency of a DCO output signal with a modulation signal input, and to scale the modulated DCO output signal based on the actual gain characteristic in the second mode to provide gain compensation and frequency modulation of the DCO. The tuning circuit may include a select switch to couple a minimal and maximal tuning word to the DCO in the first mode and an actual operating point word in the second mode to the DCO to determine the nominal gain characteristic. | 2009-12-31 |
20090322440 | MICROWAVE CIRCULATORS - A microwave circulator having an outer metal housing with a cavity containing at least one magnet and an annular centring arrangement interposed between the outside of the magnet and the cavity. The centring arrangement includes first and second solid metal rings, the two rings having cooperating inclined faces arranged such that when a force is applied to urge the centring arrangement along the cavity, one ring is displaced outwardly into intimate contact with the inside of the cavity. | 2009-12-31 |
20090322441 | CHIP ON FILM TRACE ROUTING METHOD FOR ELECTRICAL MAGNETIC INTERFERENCE REDUCTION - A chip on film (COF) trace routing method for EMI reduction includes: providing a flexible circuit board; mounting a chip that has a first signal pad, a second signal pad and a ground pad on the flexible circuit board; and forming a first signal trace, a second signal trace, a first ground trace and a second ground trace on the flexible circuit board. The first signal trace and the second signal trace are electrically connected to the first signal pad and the second signal pad respectively. The first ground trace and the second ground trace are both electrically connected to the ground pad. The first signal trace and the second signal trace are disposed between the first ground trace and the second ground trace. The first ground trace and the second ground trace are immediately adjacent to the first signal trace and the second signal trace respectively. | 2009-12-31 |
20090322442 | ELECTRONIC CIRCUIT WITH AN ABSORPTIVE DISTRIBUTED LIMITING CIRCUIT - An electronic circuit comprising a power limiter circuit. The power limiter circuit comprises a plurality of cascaded transmission line sections, each transmission line section comprising a series arrangement of at least one diode and a dissipative element for absorbing excess input signal power connected in series. The series arrangement is connected between an output of the section and effective ground, a number of diodes connected in series in the series arrangements of the sections decreases with position of the section from an input of the power limiter to an output of the power limiter by steps of one or more diodes at least at part of the sections. | 2009-12-31 |
20090322443 | IMPEDANCE TUNER SYSTEMS AND PROBES - An impedance tuner may include a transmission media for propagating RF signals, a reflection magnitude control device mounted in a fixed position relative to a direction of signal propagation along said transmission media, and a phase shifter to control a reflection phase. A multi-section probe for an impedance tuner system may include a plurality of probe sections and a holder structure for mechanically supporting the plurality of probe sections. | 2009-12-31 |
20090322444 | RESONATOR DEVICE, FILTER INCLUDING THE SAME, AND DUPLEXER - A resonator device includes a plurality of resonators which are connected in series. An inductor and a capacitor are connected in parallel with at least one of the plurality of resonators. At least another one of the plurality of resonators has no inductor or capacitor connected in parallel therewith. Therefore, a sufficiently large attenuation outside the passband can be attained when the resonator device is used in a filter. Furthermore, the resonator device can be reduced in size. | 2009-12-31 |
20090322445 | DYNAMICALLY ADJUSTABLE Q-FACTORS - One embodiment relates to a circuit for active loss compensation. The circuit includes a parallel inductor-capacitive (LC) tank circuit having a first single-ended output. A first adjustable capacitor, which includes a first terminal and a second terminal, is coupled to the first single-ended output. The circuit also includes a first pair of transistors having sources coupled to a first common node. One transistor of the first pair of transistors has a drain coupled to the first single-ended output and the other transistor of the first pair of transistors has a gate coupled to the second terminal of the first adjustable capacitor. Other embodiments are also disclosed. | 2009-12-31 |
20090322446 | Methods of Fabricating a BEOL Wiring Structure Containing an On-Chip Inductor and an On-Chip Capacitor - Methods for fabricating a back-end-of-line (BEOL) wiring structure that includes an on-chip inductor and an on-chip capacitor, as well as methods for tuning and fabricating a resonator that includes the on-chip inductor and on-chip capacitor. The fabrication methods generally include forming the on-chip capacitor and on-chip inductor in different metallization levels of the BEOL wiring structure and laterally positioned to be substantially vertical alignment. The on-chip capacitor may serve as a Faraday shield for the on-chip inductor. Optionally, a Faraday shield may be fabricated either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the directly-connected electrodes of the on-chip capacitor for tuning, during circuit operation, a resonance frequency of an LC resonator that further includes the on-chip inductor. | 2009-12-31 |
20090322447 | BEOL Wiring Structures That Include an On-Chip Inductor and an On-Chip Capacitor, and Design Structures for a Radiofrequency Integrated Circuit - Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor. | 2009-12-31 |
20090322448 | MEMS FILTER WITH VOLTAGE TUNABLE CENTER FREQUENCY AND BANDWIDTH - A tamable MEMS filter is disclosed, having a substrate with first and second isolated substrate areas. First and second anchor points are coupled to the substrate. A base is coupled to the first and second anchor points by first and second coupling beams, respectively. A dielectric layer is coupled to the base. An input conductor is coupled to the at least one dielectric layer. An output conductor is coupled to the at least one dielectric layer. | 2009-12-31 |
20090322449 | Transversal type filter - To provide a transversal type filter having weighted finger electrodes of at least either of an input IDT and an output IDT provided on a piezoelectric substrate, in which a diffraction of elastic wave output from an end face of the weighted IDT electrode is suppressed, a band width is wide, and a high flatness and a high selectivity are realized. In at least either of an input IDT and an output IDT, an apodized region in which a weighting is performed by using an apodizing method with which an aperture of finger electrodes is continuously changed is formed on a center portion of the electrode with respect to a propagation direction of an elastic wave, and dog-leg regions in which a weighting is performed by using a dog-leg method with which the aperture is made into 1/n by floating electrodes to form n tracks are formed on both sides of the apodized region. Subsequently, finger electrodes in each track of the dog-leg region are further weighted by using the apodizing method. | 2009-12-31 |
20090322450 | ELECTROMAGNETIC BANDGAP STRUCTURE AND PRINTED CIRCUIT BOARD - An electromagnetic bandgap structure and a printed circuit board having the same are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a plurality of conductive layers, placed between two conductive layers; and a stitching via, configured to make an electrical connection between any two conductive layers of the conductive layers. Here, the stitching via can include a first via, one end part of the first via configured to any one of the two conductive plates; a second via, one end part of the second via configured to the other of the two conductive plates; and a connection pattern, placed on a planar surface that is different from the conductive plates, between the two conductive layers and configured to make an electrical connection between the other end part of the first via and the other end part of the second via. Any one of the first via and the second via can be formed to penetrate a same planar surface as at least one of the two conductive layers. | 2009-12-31 |
20090322451 | Signal Output Device, Signal Output Control Method, Program and Recording Medium - The present invention can control the power of an output from a device, which changes the amplitude of an input and outputs a result of the change, according to the frequency of the input so that the power is close to a desired value. An output control system ( | 2009-12-31 |
20090322452 | HANDLE ARM AND UNDERVOLTAGE RELEASE AND CIRCUIT INTERRUPTER INCORPORATING THE SAME - A handle arm assembly is for a circuit interrupter including an undervoltage release mechanism having a reset mechanism. The handle arm assembly includes a body portion rotatable through an arc between an on position, an off position, and a reset position beyond the off position and an arm portion projecting laterally from the body portion out of the plane of the arc through which the body portion rotates. The body portion and the arm portion are formed from a single piece of material wherein the body portion and the arm portion are different portions of the single piece of material. The arm portion is structured to engage the reset mechanism in a manner such that arcuate movement of the arm portion as the body portion moves to the off position is translated into actuation of the reset mechanism. | 2009-12-31 |
20090322453 | ELECTROMAGNET DEVICE - A polar electromagnet device has a drive shaft comprising an axis center supported so as to reciprocate in an axis center direction at a center hole of a spool wound with a coil, and a movable iron core attached to a lower end of the drive shaft on the axis center. The drive shaft is reciprocated with the movable iron core which reciprocates based on excitation and demagnetization of the coil. A permanent magnet is integrally arranged at the movable iron core on the same axis center. | 2009-12-31 |
20090322454 | ELECTROMAGNETIC RELAY - An electromagnetic relay has a movable contact arranged at one end of a drive shaft that reciprocates in an axis center direction based on excitation and demagnetization of an electromagnet block, and a pair of adjacently arranged fixed contacts with which the movable contact is operable to contact and separate. A first electromagnetic iron piece, a second electromagnetic iron piece and the movable contact are inserted to the drive shaft so that the first electromagnetic iron piece and the second electromagnetic iron piece sandwich the movable contact. The second electromagnetic iron piece is biased to one end side of the drive shaft with a coil spring inserted to the drive shaft. When the movable contact contacts to the pair of fixed contacts, the second electromagnetic iron piece forming a magnetic circuit with the first electromagnetic iron piece pushes the movable contact to the pair of fixed contacts. | 2009-12-31 |
20090322455 | CONTACT DEVICE - A contact device has a first yoke having a substantially U-shape, a second yoke bridged over both ends of the first yoke, a spool wound with a coil disposed between the first yoke and the second yoke, a movable iron core inserted into a center hole of the spool in a reciprocating manner, and a contact mechanism unit formed above the second yoke driven with a drive shaft having a lower end fixed to the movable iron core, which reciprocates based on excitation and demagnetization of the coil, and an upper end projecting out from an upper surface of the second yoke. An insertion hole communicating to the center hole of the spool and through which the movable iron core reciprocates is formed in the first yoke. An annular auxiliary yoke including an insertion hole communicating to the insertion hole of the first yoke and through which the movable iron core reciprocates is provided at a lower surface of the first yoke. | 2009-12-31 |
20090322456 | Starter Solenoid with Vibration Resistant Features - A starter solenoid comprises a solenoid cap defining a contact channel. A first terminal and a second terminal are provided on the solenoid cap. A contact is moveable within the channel between a first position where the contact touches the first and second terminals and a second position where the contact is removed from the first and second terminals. A shield is positioned in the channel to space the contact apart from the channel walls. The contact comprises a first terminal face connected to a second terminal face. The first and second terminal faces are configured to respectively contact the first and second terminals when the contact is in the first position. Opposing lips extend from opposite sides of the first terminal face with a curved shoulder provided between the first terminal face and each of the opposing lips. | 2009-12-31 |
20090322457 | Design Method of High Magnetic Field Superconducting Magnet - Disclosed is a method for designing a superconducting magnet for generating high magnetic fields with high uniformity for controlling a stray field to be within an allowable range and acquiring structural and magnetic stability by optimizing the arrangement of positions and shapes of coils configuring the superconducting magnet. Volumes of a main coil and a shielding coil are set to be variables, and the critical value of a wires related on the current and magnetic field, the heat transfer depth, and the quench strain are defined to be restriction conditions so that linear programming is applied to determine an initial shape of the shielding coil and division of the main coil based on the sum of total volumes, that is, an objective function. The initial shapes of the main coil and the shielding coil determined through the linear programming are revised and the shape of a shimming coil is determined by using non-linear programming based on the objective function. | 2009-12-31 |
20090322458 | MAGNETIC COMPONENT - A magnetic component includes at least one coil and a permeable structure. The coil is formed by a radially wound wire, and the thickness of the wire is various according to the distance from a portion of the wire to the center axis of the coil. The coil is covered by the permeable structure. | 2009-12-31 |
20090322459 | PERMANENT MAGNET AND METHOD OF MANUFACTURING SAME - A permanent magnet is provided which has formed a Dy, Tb film on a surface of an iron-boron-rare earth sintered magnet of a predetermined shape, with diffusion thereof into grain boundary phases, having a higher coercive force. The method of manufacturing a permanent magnet includes a film-forming step of evaporating metal evaporating material containing at least one of Dy and Tb and adhering evaporated metal atoms to a surface of the iron-boron-rare earth sintered magnet, and a diffusing step of performing heat treatment to diffuse metal atoms adhered to the surface into grain boundary phases of the sintered magnet. The metal evaporating material contains at least one of Nd and Pr. | 2009-12-31 |
20090322460 | HIGH-FREQUENCY SWITCHING-TYPE DIRECT-CURRENT RECTIFIER - The present invention relates to a novel structure of a transformer for a high-frequency switching-type direct-current (DC) rectifier, and particularly to an improved structure of a transformer applicable to a large-current low-voltage high-frequency switching-type rectifier, wherein the transformer is comprised of a ring-shaped iron core (made of materials such as dust core or nanometer crystalline silicon or amorphous silicone), which is provided with a primary side formed with winding(s) of copper wire(s), coupling with a secondary side that is formed with a newly-developed module or block, which replaces the secondary side that was constructed to provide output with copper wires or copper plate with wire wound thereon. A cooling water tube is arranged in the secondary-side module to remove heat with the water so as to maintain normal temperatures of the transformer in a pollution-free manner with reduced size and weight and easy assembling and reduced costs of the transformer. | 2009-12-31 |
20090322461 | PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD - An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil. | 2009-12-31 |
20090322462 | Foil Winding Pulse Transformer - A pulse transformer arrangement ( | 2009-12-31 |
20090322463 | DROPOUT FUSE ASSEMBLY AND FUSE HOLDER - A fuse holder ( | 2009-12-31 |
20090322464 | Method for manufacturing electric contact material, electric contact material, and thermal fuse - A method for manufacturing an electric contact material is provided which can prevent it from being adhesively melted even when being exposed to high temperatures resulting from an arc induced by an electric current being turned on or off. Also an electric contact material which is manufactured by the method and a thermal fuse are provided. | 2009-12-31 |
20090322465 | Potentiometer - The invention relates to a potentiometer comprising (a) at least two electrically conducting segments ( | 2009-12-31 |
20090322466 | FILM RESISTOR AND A METHOD FOR FORMING AND TRIMMING A FILM RESISTOR - A thin film resistor ( | 2009-12-31 |
20090322467 | RESISTOR, PARTICULARLY SMD RESISTOR, AND ASSOCIATED PRODUCTION METHOD - The invention relates to a resistor ( | 2009-12-31 |
20090322468 | Chip Resistor and Manufacturing Method Thereof - [Problem] To provide a chip resistor and a method for manufacturing thereof, the chip resistor keeping easily soldering strength even if mounted in a horizontal position, and never projects from a holding recess of a positioning jig in a mounting process, and further does not hinder miniaturization thereof from being promoted, while keeping a good appearance thereof. | 2009-12-31 |
20090322469 | Method for checking the switching region of a touch-free switching system - A method is disclosed for checking the switching region of a touch-free switching system with at least one sensor and at least one signal emitter, wherein the signal emitter sends data to the sensor. An extremely flexible and practical switching region check is achieved in at least one embodiment by the fact that a change in at least one system parameter of the switching system derives at least one first piece of information on the position of the signal emitter. The method represents an inexpensive possibility for checking a switching region, which has options for the definition and allocation of the switch-on, switch-off, and hysteresis regions. | 2009-12-31 |
20090322470 | SYSTEM AND METHOD FOR DRIVING A DRAWER OF A REFRIGERATOR AND REFRIGERATOR EMPLOYING SAME - A system and method for driving a drawer of a refrigerator and a refrigerator employing this system is provided. This system and method allows the drawer to substantially immediately and automatically stop when the drawer encounters an obstacle. This type of automatic control of the drawer may enhance the safe operation of the drawer, prevent injuries to users, and prevent overload and subsequent malfunction of a drive motor used to move the drawer. | 2009-12-31 |
20090322471 | SYSTEM, METHOD, AND APPARATUS FOR MANAGING WASTEWATER TREATMENT INSTALLATION - Apparatus for managing a residential wastewater treatment system includes an in situ control unit that monitors an individual system. The control unit provides local control and alarms, and also sends status reports and/or alarms to a remote monitoring center via a telemetry device. The remote monitoring center makes information concerning the individual system available through a website. | 2009-12-31 |
20090322472 | Temperature measurement in electronic devices - In one embodiment, a system comprises a portable computing device comprises a housing, at least one temperature sensitive radio frequency signal source proximate the housing and at least one radio frequency interface to receive a radio signal generated by the at least one temperature sensitive radio frequency signal source. | 2009-12-31 |
20090322473 | Remote controlled dead bolt door locking system - The remote controlled deadbolt door locking system (the “unit”) is designed to be an add-on safety mechanism for existing entry doors. The unit is designed to be mounted onto the bottom corner of a door, where in the engaged position, it prevents said door from being opened even if the main lock has been tampered with. The unit makes use of a small DC electric motor to move a steel shaft in the vertical direction into a steel bushing that is mounted into a drilled hole in the floor directly in front of the door and under the unit. The unit is mounted onto the door with four carriage bolts through the door, and a mounting plate from the outside of the door, through four matching holes in the unit itself. The unit is then simply tightened on with normal hex nuts. The unit is equipped with several safety circuits, which warn the user if any of the following occur: low battery or battery failure of either the main or backup batteries; the shaft does not fully engage upon closing; and if both batteries fall to a low condition. There is a built in triple redundancy to eliminate the possibility of the homeowner locking him/herself out. The operation of the unit is accomplished through a two-button remote control, or any commercially available remote entry system including but not limited to: fingerprint or voice recognition, or keypad entry. In this way, the unit acts just like a simple dead bolt, but one that can be locked while the homeowner is standing outside of the house. | 2009-12-31 |
20090322474 | System for turning on and off power using door card key - Disclosed herein is a system for turning on and off power using a door card key. Transmission means includes a switch unit turned on and off depending on the insertion of the door card key, a switch monitoring unit configured to generate a clock signal, a microcomputer unit configured to generate an RF signal, a transmission signal amplification unit configured to amplify the RF signal generated by the microcomputer unit, and a transmission unit configured to transmit the amplified RF signal. Reception means includes a reception unit configured to receive the RF signal from the transmission means, a reception signal amplification unit configured to amplify the RF signal from the reception unit, a drive signal generation unit configured to convert the RF signal into a drive signal and then output the drive signal, and a control switch unit turned on and off in response to the drive signal. | 2009-12-31 |
20090322475 | IN-VEHICLE WIRELESS SYSTEM - An in-vehicle wireless system, capable of operating at least in a copy mode and a transmission mode, comprises: at least one receiving unit receiving a wireless signal transmitted from a remote control transmitter and demodulates a control code signal; and at least one transmitting unit transmitting wireless signals at a plurality of carrier frequencies; and a control unit controlling so as to obtain a control code from the control code signal and store it in the copy mode, and so as to perform transmitting the modulated wireless signals at all carrier frequencies unique to a plurality of the garage door opening-closing mechanisms or the like. The receiving unit may include a detection circuit connected to a reception antenna directly. | 2009-12-31 |
20090322476 | SYSTEM AND METHOD FOR ASSOCIATING AN ELECTRONIC DEVICE WITH A REMOTE DEVICE HAVING A VOICE INTERFACE - The disclosure provides a system and method for associating an electronic device with a remote electronic device. In the method at the remote device, an authentication process is initiated to authenticate the remote device to the electronic device. The authentication process includes: generating a pass key according to an authentication protocol followed by the remote device; and providing the pass key to a user through an output device on the remote device. The method also includes: waiting for the user to provide the pass key to the electronic device; and if the remote device receives a timely message from the electronic device indicating that the remote device has been authenticated, activating additional applications on the remote device to allow it to communicate with the electronic device. | 2009-12-31 |