53rd week of 2015 patent applcation highlights part 64 |
Patent application number | Title | Published |
20150380210 | SCANNING PARTICLE MICROSCOPE AND METHOD FOR DETERMINING A POSITION CHANGE OF A PARTICLE BEAM OF THE SCANNING PARTICLE MICROSCOPE - The invention refers to a scanning particle microscope comprising: (a) at least one reference object which is fixedly arranged at an output of the scanning particle microscope for a particle beam so that the reference object can at least partially be imaged by use of the electron beam; (b) at least one scanning unit operable to scan a particle beam of the scanning particle microscope across at least one portion of the reference object; and (c) at least one setting unit operable to change at least one setting of the scanning particle microscope. | 2015-12-31 |
20150380211 | High - Resolution Amplitude Contrast Imaging - A method for performing high resolution electron microscopy of a soft matter object is described. The method comprises irradiating a soft matter object using an electron microscope having a spherical aberration correction with a substantially constant transfer function in a frequency band of thermal diffuse scattered electrons scattered at the soft matter object. The method comprises detecting the thermal diffuse scattered (TDS) electrons scattered at the soft matter, and using the detected thermal diffuse scattered electrons for deriving therefrom an image of the soft matter object. | 2015-12-31 |
20150380212 | ION IMPLANTATION COMPOSITIONS, SYSTEMS, AND METHODS - Ion implantation compositions, systems and methods are described, for implantation of dopant species. Specific selenium dopant source compositions are described, as well as the use of co-flow gases to achieve advantages in implant system characteristics such as recipe transition, beam stability, source life, beam uniformity, beam current, and cost of ownership. | 2015-12-31 |
20150380213 | CHARGED PARTICLE BEAM DRAWING APPARATUS AND CHARGED PARTICLE BEAM DRAWING METHOD - A charged particle beam drawing apparatus has a drawing unit that directs a charged particle beam and draws a pattern on a target and also has a control calculator that controls the drawing unit. The control calculator has a speed calculating unit configured to calculate a first drawing speed in a first area in a drawing area on the target according to a run-up start coordinate, a drawing start coordinate, and a predetermined first acceleration, and calculate the range of the first area according to the run-up start coordinate, the first acceleration, and a second drawing speed, and also has a drawing control unit configured to control the drawing unit so that, in the first area, drawing is performed at the first drawing speed and, in a second area that follows the first area, drawing is performed at the second drawing speed. | 2015-12-31 |
20150380214 | LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - Provided is a lithography apparatus that performs patterning on a substrate with a plurality of beams, the apparatus comprising: an optical system configured to irradiate the substrate with the plurality of beams; and a controller configured to control the optical system, wherein the controller is configured to control the optical system so as to form a first pattern for an article in a first region of the substrate and form a second pattern for an inspection of the plurality of beams in a second region, different from the first region, of the substrate. | 2015-12-31 |
20150380215 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer. | 2015-12-31 |
20150380216 | SUBSTRATE TREATING APPARATUS - The inventive concepts provide a substrate treating apparatus. The apparatus includes a process chamber, a substrate support unit, a gas supply unit, a microwave applying unit, an antenna plate, a slow-wave plate, a dielectric plate, and an exhaust baffle, and a liner. The liner includes a body having a ring shape facing an inner sidewall of the process chamber, and a flange extending from the body into a wall portion of the process chamber. The flange prevents an electric field of a microwave and a process gas from being provided into a gap between the process chamber and the body. Thus, it is possible to inhibit particles from being generated by damage of the inner sidewall of the process chamber by plasma, and drift distances of the particles can be reduced to inhibit the particles from reaching a substrate. | 2015-12-31 |
20150380217 | CHAMBER DESIGN FOR SEMICONDUCTOR PROCESSING - Embodiments described herein provide an apparatus for improving deposition uniformity by improving plasma profile using a tri-cut chamber liner. The apparatus also includes a lid assembly having a split process stack for reducing downtime and a bottom heater support for more efficient heating of chamber walls. | 2015-12-31 |
20150380218 | MULTIPLE POINT GAS DELIVERY APPARATUS FOR ETCHING MATERIALS - Implementations of the present disclosure relate to an electrode assembly for a processing chamber. In one implementation, the electrode assembly includes a cathode electrode having an inner volume and a ground anode electrode spaced apart from the cathode electrode. A first etchant gas is introduced through the cathode electrode and into the inner volume. The first etchant gas is ionized within the inner volume. The ionized first etchant gas is filtered to allow only radicals to flow from the inner volume into a mixing volume formed within the ground anode electrode. The mixing volume is separated from the inner volume by a gas injection ring. The radicals from the first etchant gas are mixed and reacted with a second etchant gas in molecular phase, which is introduced through the ground anode electrode into a sidewall of the gas injection ring before entering the mixing volume in an evenly distributed manner. | 2015-12-31 |
20150380219 | Mounting Stage and Plasma Processing Apparatus - According to one embodiment, in a mounting stage for mounting a target substrate subjected to processing with reducing radicals, the mounting stage includes a mounting surface covered with the target substrate in plan view, a non-mounting surface adjacent to the mounting surface, and a mounting part configured to hold the target substrate. The mounting part is projected from the mounting surface and holds the target substrate so as to form a space between a back surface of the target substrate and the mounting surface during the processing, and surface of the mounting surface and the non-mounting surface are covered with a material suppressing deactivation of reducing radicals. | 2015-12-31 |
20150380220 | CHAMBER APPARATUS FOR CHEMICAL ETCHING OF DIELECTRIC MATERIALS - Implementations of the disclosure generally provide an improved pedestal heater for a processing chamber. The pedestal heater includes a temperature-controlled plate having a first surface and a second surface opposing the first surface. The temperature-controlled plate includes an inner zone comprising a first set of heating elements, an outer zone comprising a second set of heating elements, the outer zone surrounding the inner zone, and a continuous thermal choke disposed between the inner zone and the outer zone, and a substrate receiving plate having a first surface and a second surface opposing the first surface, the second surface of the substrate receiving plate is coupled to the first surface of the temperature-controlled plate. The continuous thermal choke enables a very small temperature gradient to be created and manipulated between the inner zone and the outer zone, allowing center-fast or edge-fast etching profile to achieve on a surface of the substrate. | 2015-12-31 |
20150380221 | Hole Pattern For Uniform Illumination Of Workpiece Below A Capacitively Coupled Plasma Source - A plasma source assembly for use with a processing chamber includes a blocker plate with a first set of apertures within an inner electrical center of the blocker plate and smaller apertures around the outer peripheral edge. The apertures can decrease gradually in diameter from the electrical center outward to the peripheral edge or can be in discrete increments with the smallest at the outer peripheral edge. | 2015-12-31 |
20150380222 | ZINC OXIDE SPUTTERING TARGET - Provided is a zinc oxide-based sputtering target that enables production of a zinc oxide-based sputtered film having higher transparency and electrical conductivity. The zinc oxide-based sputtering target of the present invention is composed of a zinc oxide-based sintered body including zinc oxide crystal grains as a main phase and spinel phases as a dopant-containing grain boundary phase, and the zinc oxide-based sputtering target has a degree of (002) orientation of ZnO of 80% or greater at a sputtering surface, a density of the zinc oxide-based sintered body of 5.50 g/cm | 2015-12-31 |
20150380223 | HOLDING ASSEMBLY FOR SUBSTRATE PROCESSING CHAMBER - A holding assembly for retaining a deposition ring about a periphery of a substrate support in a substrate processing chamber, the deposition ring comprising a peripheral recessed pocket with a holding post. The holding assembly comprises a restraint beam capable of being attached to the substrate support, the restraint beam comprising two ends, and an anti-lift bracket. The anti-lift bracket comprises a block comprising a through-channel to receive an end of a restraint beam, and a retaining hoop attached to the block, the retaining hoop sized to slide over and encircle the holding post in the peripheral recessed pocket of the deposition ring. | 2015-12-31 |
20150380224 | ELECTRONIC AMPLIFYING SUBSTRATE AND METHOD OF MANUFACTURING ELECTRONIC AMPLIFYING SUBSTRATE - An electronic amplifying substrate, including: a glass base material having an insulating property; conductive layers formed on both main surfaces of the glass base material; and a plurality of through holes formed on a lamination body of the glass base material and the conductive layer, wherein an electric field is formed in the through hole by a potential difference between both conductive layers during application of a voltage to a surface of the conductive layer so that an electron avalanche amplification occurs in the through hole, and an insulation part is formed on at least one main surface of the glass base material, with one of the end portions of the insulation part formed to surround an opening part of the through hole of the glass base material, and the other end portion formed in contact with the end portions of the conductive layers. | 2015-12-31 |
20150380225 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device ( | 2015-12-31 |
20150380226 | IONIZATION CHAMBER - An ionization chamber | 2015-12-31 |
20150380227 | TWO ROTATING ELECTRIC FIELDS MASS ANALYZER - A mass analyzer includes two rotating electric field (REF) units, sinusoidal signal generators and a means for separation of dispersed ions. The REF units include a plurality of elongated electrodes surrounding a central axis, and are lined in tandem at elongated direction. Sinusoidal signals are applied to the electrodes to rotate electric fields within each REF unit. The means for separation is placed adjacent the downstream end of the 2 | 2015-12-31 |
20150380228 | AN ANALYTICAL APPARATUS UTILIZING ELECTRON IMPACT IONIZATION - An analytical apparatus ( | 2015-12-31 |
20150380229 | MASS SPECTROMETER - A mass spectrometer ( | 2015-12-31 |
20150380230 | M/Z Targeted Attenuation on Time of Flight Instruments - A method of mass spectrometry is disclosed comprising separating ions according to one or more physico-chemical properties. Ions which are onwardly transmitted to a Time of Flight mass analyser are controlled by attenuating ions which would otherwise be transmitted to the Time of Flight mass analyser and cause saturation of an ion detector and which have been determined or which are predicted to have a relatively high intensity. | 2015-12-31 |
20150380231 | Improved Efficiency and Precise Control of Gas Phase Reactions in Mass Spectrometers Using an Auto Ejection Ion Trap - A collision or reaction device for a mass spectrometer is disclosed comprising a first device arranged and adapted to cause first ions to collide or react with charged particles and/or neutral particles or otherwise dissociate so as to form second ions. The collision or reaction device further comprises a second device arranged and adapted to apply a broadband excitation with one or more frequency notches to the first device so as to cause the second ions and/or ions derived from the second ions to be substantially ejected from the first device without causing the first ions to be substantially ejected from the first device. | 2015-12-31 |
20150380232 | Device Allowing Improved Reaction Monitoring of Gas Phase Reactions in Mass Spectrometers Using an Auto Ejection Ion Trap - A collision or reaction device for a mass spectrometer is disclosed comprising a first device arranged and adapted to cause first ions to collide or react with charged particles and/or neutral particles or otherwise dissociate so as to form second ions. A second device is arranged and adapted to apply a broadband excitation with one or more frequency notches to the first device so as to cause the second ions and/or ions derived from the second ions to be substantially ejected from the collision or reaction region. The collision or reaction device further comprises a device arranged and adapted to determine the time when the second ions and/or ions derived from the second ions are substantially ejected from the first device. | 2015-12-31 |
20150380233 | Ion Trap Mass Spectrometer - A novel MS-MS apparatus utilizing electrostatic traps is disclosed, along with an associated method of analysis. The apparatus may include a chromatograph, an ion source, a first mass spectrometer, a fragmentation cell, an ion guide, a pulsed converter, and a Z-directional elongated electrostatic trap. The electrostatic trap, which may be Z-elongated into a cylindrical electrostatic trap, includes at least one of an image current detector and a time-of-flight detector. The pulsed converter is Z-directionally elongated to match the electrostatic trap. Ion selection from electrostatic traps may be accomplished with an electrode that ejects ion from an oscillation space to a time-of-flight detector, a fragmentation surface, or a passage between E-trap regions. | 2015-12-31 |
20150380234 | Socket and Discharge Lamp - According to one embodiment, a socket includes a main body section, a terminal provided in the main body section and assuming a cylindrical shape, a lead wire being welded to an end face provided at one end portion of the terminal, and an insulating section provided on the inside of the terminal, including a hole section through which the lead wire is inserted, and containing resin. When the cross sectional dimension of the lead wire is represented as W and the opening dimension of the hole section on the end face side is represented as “a”, the socket satisfies the following expression: | 2015-12-31 |
20150380235 | METHODS FOR BONDING SEMICONDUCTOR WAFERS - A method of bonding a cap wafer to a device wafer includes heating the device wafer and the cap wafer in the chamber, cooling the device wafer and the cap wafer in the chamber, pressurizing the chamber, introducing gas into the chamber while the chamber is pressurized to accelerate a rate of one of a group consisting of the heating and the cooling, and applying pressure to the device wafer and the cap wafer while a bond is formed between the device wafer and the cap wafer. | 2015-12-31 |
20150380236 | SUBSTRATE RECYCLING METHOD - Embodiments of the disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate. | 2015-12-31 |
20150380237 | METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer. | 2015-12-31 |
20150380238 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming an aluminum nitride layer on a surface of the nitride-based semiconductor layer at a forming temperature and in a growth atmosphere for aluminum nitride; and performing a thermal treatment on the nitride-based semiconductor layer and the aluminum nitride layer, at a treatment temperature that is higher than the forming temperature and in the growth atmosphere for aluminum nitride. For example, an n-GaN layer is formed on an n-GaN substrate, and thereafter the n-GaN layer is doped with an impurity. A cap layer of an epitaxial film made up of AlN is formed, by MOCVD, on the surface of the n-GaN layer. Thermal treatment for activation annealing activates the impurity in the n-GaN layer in an atmosphere that causes AlN to grow, or in an atmosphere in which growth and decomposition of AlN are substantially balanced. | 2015-12-31 |
20150380239 | BLOCK CO-POLYMER PHOTORESIST - An integrated circuit is made by depositing a pinning layer on a substrate. A block copolymer photoresist is formed on the pinning layer. The block copolymer has two blocks A and B that do not self-assemble under at least some annealing conditions. The exposed block copolymer photoresist is processed to cleave at least some block copolymer bonds in the exposed selected regions. The exposed pinning layer is processed to create a chemical epitaxial pattern to direct the local self assembly of the block copolymer. | 2015-12-31 |
20150380240 | GALLIUM LANTHANIDE OXIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition. | 2015-12-31 |
20150380241 | FIN FIELD-EFFCT TRANSISTOR AND FABRICATION METHOD THEREOF - A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins. | 2015-12-31 |
20150380242 | SILICON SUBSTRATES WITH COMPRESSIVE STRESS AND METHODS FOR PRODUCTION OF THE SAME - A heterostructure including: a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and an epitaxial layer disposed on the second primary surface of the substrate is disclosed along with methods for production of the same. | 2015-12-31 |
20150380243 | SILICON CARBIDE SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon-containing gas, carbon-containing gas, and chlorine-containing gas are introduced into a reacting furnace. Next, a SiC epitaxial film is grown on the front surface of a 4H-SiC substrate by a halide CVD method in a mixed gas atmosphere made of the plurality of gasses introduced. In the SiC epitaxial film growing, a SiC epitaxial film of a first predetermined thickness is grown at a first growth rate. The first growth rate is increased from an initial growth rate to a higher growth rate. Furthermore, the SiC epitaxial film is grown, at a second growth rate, until the thickness of the SiC epitaxial film reaches a second predetermined thickness. By so doing, it is possible to improve the crystallinity of a silicon carbide semiconductor film grown in a gas atmosphere containing halide. | 2015-12-31 |
20150380244 | ANISOTROPIC DEPOSITION IN NANOSCALE WIRES - The present invention generally relates to nanoscale wires, including anisotropic deposition in nanoscale wires. In one set of embodiments, material may be deposited on certain portions of a nanoscale wire, e.g., anisotropically. For example, material may be deposited on a first facet of a crystalline nanoscale wire but not on a isotropic second facet. In some cases, additional materials may be deposited thereon, and/or the portions of the nanoscale wire may be removed, e.g., to produce vacant regions within the nanoscale wire, which may contain gas or other species. Other embodiments of the invention may be directed to articles made thereby, devices containing such nanoscale wires, kits involving such nanoscale wires, or the like. | 2015-12-31 |
20150380245 | POLYSILICON MANUFACTURING METHOD THAT ENHANCES HOMOGENEITY OF POLYSILICON LAYER - The present invention provides a polysilicon manufacturing method that enhances homogeneity of a polysilicon layer, including (1) forming a amorphous silicon layer ( | 2015-12-31 |
20150380246 | DIMENSION-CONTROLLED VIA FORMATION PROCESSING - Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench. | 2015-12-31 |
20150380247 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element. | 2015-12-31 |
20150380248 | METHOD FOR MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR ELEMENT - An ion implantation mask, which is an inorganic insulating film, is formed on a silicon carbide substrate. A mask portion and two regions of an opened ion implantation portion are formed in the ion implantation mask by dry etching. At that time, a residual portion which is thinner than the mask portion is formed in the bottom of the opened ion implantation portion. Then, ions are implanted through the ion implantation mask to form a predetermined semiconductor region in the silicon carbide substrate. According to this structure, it is possible to prevent an increase in the roughness of the surface of the silicon carbide substrate and to improve breakdown voltage. | 2015-12-31 |
20150380249 | METHODS FOR FORMING A MOLECULAR DOPANT MONOLAYER ON A SUBSTRATE - Methods for forming a conformal dopant monolayer on a substrate are provided. In one embodiment, a method for forming a semi-conductor device on a substrate includes forming a charged layer on a silicon containing surface disposed on a substrate, wherein the charged layer has a first charge, and forming a dopant monolayer on the charged layer, wherein dopants formed in the dopant monolayer include at least one of a group III or group V atoms. | 2015-12-31 |
20150380250 | SEMICONDUCTOR CONTACTS AND METHODS OF FABRICATION - Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts. | 2015-12-31 |
20150380251 | BLOCK MASK LITHO ON HIGH ASPECT RATIO TOPOGRAPHY WITH MINIMAL SEMICONDUCTOR MATERIAL DAMAGE - A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (OPL) layer, a titanium-containing antireflective coating (TiARC) layer on the OPL layer and a photoresist layer on the TiARC layer. Employing a combination of an OPL having a high etch rate and a TiARC layer that can be easily removed by a mild chemical etchant solution in the trilayer stack can significantly minimize substrate damage during lithographic patterning processes. | 2015-12-31 |
20150380252 | SIDEWALL IMAGE TEMPLATES FOR DIRECTED SELF-ASSEMBLY MATERIALS - In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask. | 2015-12-31 |
20150380253 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of the substrate; forming a gate dielectric layer over the substrate; performing a post-treatment including a second hydrogen annealing on the substrate including the gate dielectric layer; and forming a gate electrode over the gate dielectric layer. | 2015-12-31 |
20150380254 | METHOD FOR FORMING A METAL SILICIDE USING A SOLUTION CONTAINING GOLD IONS AND FLUORINE IONS - A subject matter of the invention is a process for the formation of nickel silicide or of cobalt silicide, comprising the stages consisting in:
| 2015-12-31 |
20150380255 | WAFER POLISHING APPARATUS AND METHOD - Disclosed is a wafer processing apparatus. The wafer processing apparatus includes a first surface plate on which a plurality of carriers is arranged, a first gear arranged at the central region of the first surface plate and engaged with the plurality of carriers, a second gear arranged around the edge region of the first surface plate and engaged with the plurality of carriers, a motor rotating the first surface plate in a first direction, a fixing hanger arranged opposite the first surface plate, and a second surface plate hung on the fixing hanger such that a clearance between the first surface plate and the second surface plate may be varied. | 2015-12-31 |
20150380256 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench. | 2015-12-31 |
20150380257 | METHOD OF FORMING FINFET HAVING FINS OF DIFFERENT HEIGHT - A device is fabricated on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. A first mask is formed over the surface at a first portion of the wafer, leaving a second portion of the wafer unmasked. The wafer is etched at the unmasked second portion of the wafer to form a depression in the active silicon layer. A thermal oxide layer is formed to substantially fill the depression, the first mask is removed, and fins are formed at the first and second portions of the wafer. | 2015-12-31 |
20150380258 | METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE - Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights. | 2015-12-31 |
20150380259 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer. | 2015-12-31 |
20150380260 | SEMICONDUCTOR STRUCTURES INCLUDING SELF-ASSEMBLED POLYMER DOMAINS REGISTERED TO THE UNDERLYING SELF-ASSEMBLED POLYMER DOMAINS, TEMPLATES COMPRISING THE SAME, AND METHODS OF FORMING THE SAME - A semiconductor structure comprises a first self-assembled block copolymer material within a trench in a substrate and a second self-assembled block copolymer material overlying the first self-assembled block copolymer material. The first self-assembled block copolymer material comprises self-assembled polymer domains registered to sidewalls of the trench and extending a length of the trench. The second self-assembled block copolymer material comprises self-assembled polymer domains overlying and registered to the self-assembled polymer domains of the first self-assembled block copolymer material. The first self-assembled block copolymer material comprises a different material from the first self-assembled block copolymer material. A template comprises lines extending a length of a trench in a substrate and separated by openings exposing a floor of the trench in a substrate. Each of the lines comprises the first self-assembled block copolymer material and the second self-assembled block copolymer material overlying the first self-assembled block copolymer material. | 2015-12-31 |
20150380261 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. | 2015-12-31 |
20150380262 | SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH - Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. | 2015-12-31 |
20150380263 | CHEMICAL-MECHANICAL POLISHING COMPOSITIONS COMPRISING ONE OR MORE POLYMERS SELECTED FROM THE GROUP CONSISTING OF N-VINYL-HOMOPOLYMERS AND N-VINYL COPOLYMERS - Described is a chemical-mechanical polishing (CMP) composition comprising the following components: (A) surface modified silica particles having a negative zeta potential of −15 mV or below at a pH in the range of from 2 to 6 (B) one or more polymers selected from the group consisting of N-vinyl-homopolymers and N-vinyl copolymers (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6. | 2015-12-31 |
20150380264 | ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING - A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence. | 2015-12-31 |
20150380265 | POST TREATMENT FOR DIELECTRIC CONSTANT REDUCTION WITH PORE GENERATION ON LOW K DIELECTRIC FILMS - A method and apparatus for depositing a low K dielectric film with one or more features is disclosed herein. A method of forming a dielectric layer can include positioning a substrate in a processing chamber, delivering a deposition gas to the processing chamber, depositing a dense organosilicon layer using the deposition gas on the surface of the substrate, the dense organosilicon layer comprising a porogenic carbon, transferring a pattern into the dense organosilicon layer, forming a pore-forming plasma from a reactant gas, exposing the dense organosilicon layer to the pore-forming plasma to create a porous organosilicon layer, wherein the pore-forming plasma removes at least a portion of the porogenic carbon and exposing the porous organosilicon layer to a desiccating post treatment. | 2015-12-31 |
20150380266 | METHODS FOR PROVIDING LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - Causing a self-assemblable block copolymer (BCP) having first and second blocks to migrate from a region surrounding a lithography recess of the substrate and a dummy recess on the substrate to within the lithography recess and the dummy recess, causing the BCP to self-assemble into an ordered layer within the lithography recess, the layer having a first block domain and a second block domain, and selectively removing the first domain to form a lithography feature having the second domain within the lithography recess, wherein a width of the dummy recess is smaller than the minimum width required by the BCP to self-assemble, the dummy recess is within the region of the substrate surrounding the lithography recess from which the BCP is caused to migrate, and the width between portions of a side-wall of the lithography recess is greater than the width between portions of a side-wall of the dummy recess. | 2015-12-31 |
20150380267 | METHODS OF REMOVING A HARD MASK - In a method of removing a hard mask, a hard mask is formed on a substrate. A first plasma treatment is performed on the hard mask at a first temperature. A second plasma treatment is performed on the hard mask at a second temperature higher than the first temperature. | 2015-12-31 |
20150380268 | ETCHING METHOD AND STORAGE MEDIUM - An etching method includes: disposing a substrate to be processed within a chamber, the substrate to be processed having a silicon oxide film formed on a surface thereof and a silicon nitride film formed adjacent to the silicon oxide film; and selectively etching the silicon oxide film with respect to the silicon nitride film by supplying HF gas or HF gas and F | 2015-12-31 |
20150380269 | METHODS OF FORMING INTEGRATED CIRCUITS WITH A PLANARIZED PERMANET LAYER AND METHODS FOR FORMING FINFET DEVICES WITH A PLANARIZED PERMANENT LAYER - Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing. | 2015-12-31 |
20150380270 | METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE - A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench. | 2015-12-31 |
20150380271 | NEUTRAL BEAM ETCHING OF CU-CONTAINING LAYERS IN AN ORGANIC COMPOUND GAS ENVIRONMENT - A method and apparatus for dry etching pure Cu and Cu-containing layers for manufacturing integrated circuits. The invention uses a directional beam of O-atoms with high kinetic energy to oxidize the Cu and Cu-containing layers, and organic compound etching reagents that react with the oxidized Cu to form volatile Cu-containing etch products. The invention allows for low-temperature, anisotropic etching of pure Cu and Cu-containing layers in accordance with a patterned hard mask or photoresist. | 2015-12-31 |
20150380272 | LINER AND BARRIER APPLICATIONS FOR SUBTRACTIVE METAL INTEGRATION - Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate. | 2015-12-31 |
20150380273 | LIQUID COMPOSITION USED IN ETCHING MULTILAYER FILM CONTAINING COPPER AND MOLYBDENUM, MANUFACTURING METHOD OF SUBSTRATE USING SAID LIQUID COMPOSITION, AND SUBSTRATE MANUFACTURED BY SAID MANUFACTURING METHOD - The present invention provides a liquid composition used for etching a multilayer film containing copper and molybdenum, an etching method for etching a multilayer film containing copper and molybdenum, and a substrate. The present invention further provides a liquid composition for etching a multilayer-film wiring substrate which has an oxide layer (IGZO) including indium, gallium and zinc laminated on the substrate, and further a multilayer film including at least a layer containing molybdenum and a layer containing copper provided thereon, a method for etching a multilayer film containing copper and molybdenum from the substrate, and a substrate. According to the present invention, a liquid composition comprising (A) a maleic acid ion source, (B) a copper ion source, and (C) at least one type of amine compound selected from the group consisting of 1-amino-2-propanol, 2-(methylamino)ethanol, 2-(ethylamino)ethanol, 2-(butylamino)ethanol, 2-(dimethylamino)ethanol, 2-(diethylamino)ethanol, 2-methoxyethylamine, 3-methoxypropylamine, 3-amino-1-propanol, 2-amino-2-methyl-1-propanol, 1-dimethylamino-2-propanol, 2-(2-aminoethoxyl)ethanol, morpholine and 4-(2-hydroxyethyl)morpholine and having a pH value of 4-9 is used. | 2015-12-31 |
20150380274 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For this purpose, a semiconductor chip and a cylindrical electrode are mounted on one main surface of substrate. The substrate, the semiconductor chip, and the cylindrical electrode are sealed with resin material such that the cylindrical electrode has one end mounted to the substrate and the other opposite end at least exposed. After the step of sealing, an opening extending from the other end of the cylindrical electrode to a cavity in the cylindrical electrode is formed. Before performing the step of forming an opening, the other end of the cylindrical electrode is closed. | 2015-12-31 |
20150380275 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region. | 2015-12-31 |
20150380276 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip. | 2015-12-31 |
20150380277 | UNDERFILL SHEET, UNDERFILL SHEET INTEGRATED WITH TAPE FOR GRINDING REAR SURFACE, UNDERFILL SHEET INTEGRATED WITH DICING TAPE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object of the present invention is to provide an underfill sheet that enables suitable filling of unevenness of a circuit surface of a semiconductor element, a suitable connection of a terminal of the semiconductor element and a terminal of an adherend, and suppression of outgas. The present invention relates to the underfill sheet having a viscosity of 1,000 Pa·s to 10,000 Pa·s at 150° C. and 0.05 to 0.20 rotations/min; and a minimum viscosity of 100 Pa·s or more at 100 to 200° C. and 0.3 to 0.7 rotations/min. | 2015-12-31 |
20150380278 | HARDWARE FOR THE SEPARATION AND DEGASSING OF DISSOLVED GASES IN SEMICONDUCTOR PRECURSOR CHEMICALS - An apparatus for degassing gases having large gas molecules, such as argon, from liquids for use in semiconductor processing is provided. The apparatus includes a spool-free tubing in a cylindrical vessel with a removable lid and crystalline window. The apparatus is assembled by removing the lid, connecting the tubing via connectors to an inlet and outlet in the lid, and placing the tubing into the vessel with the lid, and securing the lid. | 2015-12-31 |
20150380279 | APPARATUS FOR TREATING SUBSTRATE - Disclosed is a substrate treating apparatus which includes a treating container having a treating space therein and including a plurality of collecting vessels surrounding the treating space and provided such that inlets for inputting a fluid in the treating space are vertically stacked on each other, a support unit supporting a substrate in the treating space, a solution supply unit supplying a treating solution to the substrate supported by the support unit, and elevation units respectively joined with the collecting vessels and lifting up and down the collecting vessels. Each of the elevation units includes a base having a ring shape and joined with a corresponding collecting vessel, an elevation load joined with the base, and a driver lifting up and down the elevation load. | 2015-12-31 |
20150380280 | FLOW-RATE REGULATOR DEVICE, DILUTED CHEMICAL-LIQUID SUPPLY DEVICE, LIQUID PROCESSING APPARATUS AND ITS OPERATING SYSTEM - A flow-rate regulator device for controlling a flow rate of a liquid includes a first flow-rate regulator component positioned on an upstream side of a liquid line, and a second flow-rate regulator component positioned on a downstream side of the liquid line and connected in series to the first flow-rate regulator component. The first flow-rate regulator component adjusts a degree of opening such that a flow rate of liquid flowing through the liquid line is set a specified number of times greater than a target flow rate when the second flow-rate regulator component has a full opening, and the second flow-rate regulator component adjusts a degree of opening such that the flow rate of the liquid flowing through the liquid line is to be at the target flow rate when the first flow-rate regulator component is adjusted to have the degree of opening. | 2015-12-31 |
20150380281 | CERAMIC SHOWERHEAD INCLUDING CENTRAL GAS INJECTOR FOR TUNABLE CONVECTIVE-DIFFUSIVE GAS FLOW IN SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS - An inductively coupled plasma processing apparatus comprises a vacuum chamber, a vacuum source, and a substrate support on which a semiconductor substrate is supported. A ceramic showerhead forms an upper wall of the vacuum chamber. The ceramic showerhead includes a gas plenum in fluid communication with a plurality of showerhead gas outlets for supplying process gas to the interior of the vacuum chamber, and a central opening configured to receive a central gas injector. A central gas injector is disposed in the central opening of the ceramic showerhead. The central gas injector includes a plurality of gas injector outlets for supplying process gas to the interior of the vacuum chamber. An RF energy source energizes the process gas into a plasma state to process the semiconductor substrate. The flow rate of the process gas supplied by the central gas injector and the flow rate of the process gas supplied by the ceramic showerhead can be independently controlled. | 2015-12-31 |
20150380282 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A controller disclosed herein drives, in a first step, a high frequency generating source at a first energy condition, and drives, in a second step, a high frequency generating source at a second energy condition. Prior to a switching time of the first step and the second step, the controller switches gas species supplied from the gas supply system into the processing container, and sets a gas flow rate in an initial period just after the switching to be larger than a gas flow rate in a stabilization period after lapse of the initial period. | 2015-12-31 |
20150380283 | PROCESSING APPARATUS - A processing apparatus including a holding unit that holds a workpiece and a grinding unit that grinds the workpiece held by the holding unit is provided. The processing apparatus includes a gettering capability determining unit that determines whether or not grinding distortion generated by grinding the workpiece held by the holding unit by the grinding unit has sufficient gettering capability. | 2015-12-31 |
20150380284 | APPARATUS FOR PROCESSING SUBSTRATE - Provided is a substrate processing apparatus. The substrate processing apparatus includes a process chamber having an inner space in which a substrate transferred from the outside is accommodated, and a process with respect to the substrate is performed, hot-wire heaters disposed in a sidewall of the process chamber, the hot-wire heaters being disposed around the inner space to heat the substrate, and a cooling tube in which a refrigerant supplied from the outside flows, the cooling tube being disposed between the hot-wire heaters along the sidewall of the process chamber. | 2015-12-31 |
20150380285 | HIGH THROUGHPUT HEATED ION IMPLANTATION SYSTEM AND METHOD - An ion implantation system has an ion implantation apparatus coupled to first and second dual load lock assemblies, each having a respective first and second chamber separated by a common wall. Each first chamber has a pre-heat apparatus configured to heat a workpiece to a first temperature. Each second chamber has a post-cool apparatus configured to cool the workpiece to a second temperature. A thermal chuck retains the workpiece in a process chamber for ion implantation, and the thermal chuck is configured to heat the workpiece to a third temperature. A pump and vent are in selective fluid communication with the first and second chambers. A controller is configured to heat the workpiece to the first temperature in an atmospheric environment via the pre-heat apparatus, to heat the workpiece to the second temperature via the thermal chuck, to implant ions into the workpiece via the ion implantation apparatus, and to transfer the workpiece between atmospheric and vacuum environments via a control of the pre-heat apparatus, post-cool apparatus, pump, vent, and thermal chuck. | 2015-12-31 |
20150380286 | SUBSTRATE TRANSFERRING ARM AND SUBSTRATE TRANSFERRING APPARATUS INCLUDING THE SAME - A substrate transporting arm and a substrate transporting apparatus including the same prevent a substrate from sliding and increase a process speed of the substrate, thereby improving productivity. The substrate transporting arm includes a body and a plurality of substrate supporters coupled to the body. Each of the plurality of substrate supporters includes a substrate holder and a substrate supporter pin, and an inner side of the substrate holder includes an inclined portion | 2015-12-31 |
20150380287 | METHOD AND SYSTEM FOR NATURALLY OXIDIZING A SUBSTRATE - A system and method for treating a substrate in a reaction chamber. A transfer chamber is arranged between a first lock and a second lock, wherein the second lock is provided between the transfer chamber and the reaction chamber. A substrate is transferred into the transfer chamber through the first lock, and the first lock is closed. In a next step, the transfer chamber is flooded with the same gas as in the reaction chamber and the pressure and temperature of the gaseous atmosphere in the transfer chamber is controlled to be the same as in the reaction chamber. Then, the second lock is opened and the substrate is transferred from the transfer chamber into the reaction chamber to treat the substrate. A computer program product for carrying out the above method. | 2015-12-31 |
20150380288 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - Provided is a substrate processing apparatus including a substrate container transfer device configured to transfer a substrate container accommodating a substrate and purge an inside of the substrate container; a purge gas supply unit installed at the substrate container transfer device and configured to supply a purge gas into the substrate container; a substrate container standby unit configured to accommodate the substrate container; a contact preventing unit installed at the substrate container standby unit and configured to prevent a contact between the purge gas supply unit and the substrate container standby unit when the substrate container is transferred to the substrate container standby unit by the substrate container transfer device; and a control unit configured to control the substrate container transfer device and the purge gas supply unit. | 2015-12-31 |
20150380289 | SMALL PRODUCTION DEVICE AND PRODUCTION SYSTEM USING THE SAME - [Problem to be Solved] | 2015-12-31 |
20150380290 | COMPOSITE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A composite substrate | 2015-12-31 |
20150380291 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A glass substrate is bonded to a front surface of a wafer on which a front surface element structure is formed, with an adhesive layer interposed therebetween. An adhesive layer is formed on the wafer to extend from the front surface of the wafer to a chamfered portion and a side surface of the wafer. The adhesive layer is formed on a first surface of the glass substrate and is not formed on a chamfered portion and a side surface of the glass substrate. After the rear surface of the wafer is ground, a rear surface element structure is formed on the ground rear surface. A laser beam is radiated to the glass substrate and the glass substrate is peeled from the adhesive layer. The adhesive layer is removed and the wafer is cut by dicing. In this way, a chip having a thin semiconductor device formed thereon is completed. | 2015-12-31 |
20150380292 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: bonding at least a part of the rear surface of a semiconductor wafer, and a supporting substrate in use of using a silane coupling agent; forming a functional structure on a front surface of the semiconductor wafer; placing a condensation point of laser light transmitted through the semiconductor wafer on a bonding interface between the semiconductor wafer and the supporting substrate, and irradiating the bonding interface with the laser light, thereby forming a fracture layer on at least a part of an outer circumferential section of the bonding interface; separating the bonding interface; and carrying out rear surface processing on the rear surface of the semiconductor wafer. | 2015-12-31 |
20150380293 | TRAY FOR A WAFER WITH TAPE FRAME - A tray for storing a wafer with a tape frame in a storage container includes a ring-shaped frame, a dicing tape and a semiconductor wafer. The dicing tape is stuck on the rear surface of the ring-shaped frame, and the semiconductor wafer is supported on the dicing tape. The tray has a substantially circular shape and is positioned on the upper side and the lower side of the wafer with tape frame. The front surface of the tray has a flat portion for mounting the wafer, and at least a portion of the outer peripheral portion of the front surface of the tray includes a convex portion. A projecting portion is formed on the rear surface so that the projection portion is positioned outside the outer periphery of the semiconductor wafer of the wafer with the tape frame when the tray is positioned on the wafer with tape frame. | 2015-12-31 |
20150380294 | Vacuum Chuck with Polymeric Embossments - A vacuum chuck with polymeric embossments is disclosed. The polymeric embossments are formed on the surface of a base substrate and are lapped to a flatness such that a wafer substrate clamped by the vacuum chuck has a peak to valley flatness that is less than a peak to valley flatness across the base substrate. Lapping of the polymeric embossments accommodates for variations in the flatness of the base substrate so long as the embossments are tall enough to stand over the peak to valley height variations in the base substrate. | 2015-12-31 |
20150380295 | CHEMICAL MECHANICAL POLISHING COMPOSITION AND METHOD FOR POLISHING TUNGSTEN - A composition and method for tungsten is provided comprising: a metal oxide abrasive; an oxidizer; a tungsten removal rate enhancing substance according to formula I; and, water; wherein the polishing composition exhibits an enhanced tungsten removal rate and a tungsten removal rate enhancement. | 2015-12-31 |
20150380296 | CLEANING OF CARBON-BASED CONTAMINANTS IN METAL INTERCONNECTS FOR INTERCONNECT CAPPING APPLICATIONS - Protective caps residing at an interface between copper lines and dielectric diffusion barrier layers are used to improve various performance characteristics of interconnects. The caps, such as cobalt-containing caps or manganese-containing caps, are selectively deposited onto exposed copper lines in a presence of exposed dielectric using CVD or ALD methods. The deposition of the capping material is affected by the presence of carbon-containing contaminants on the surface of copper, which may lead to poor or uneven growth of the capping layer. A method of removing carbon-containing contaminants from the copper surface prior to deposition of caps involves contacting the substrate containing the exposed copper surface with a silylating agent at a first temperature to form a layer of reacted silylating agent on the copper surface, followed by heating the substrate at a higher temperature to release the reacted silylating agent from the copper surface. | 2015-12-31 |
20150380297 | METHOD FOR MANUFACTURING MOSFET - Provided is a method for manufacturing a MOSFET, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the MOSFET; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions. | 2015-12-31 |
20150380298 | Air-Gap Assisted Etch Self-Aligned Dual Damascene - A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer. | 2015-12-31 |
20150380299 | METHODS FOR PROVIDING SPACED LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method of forming a plurality of regularly spaced lithography features, e.g. contact holes, including: providing a trench on a substrate, the trench having opposing side-walls and a base, with the side-walls having a width therebetween, wherein the trench is formed by photolithography including exposing the substrate using off-axis illumination whereby a modulation is provided to the side-walls of the trench; providing a self-assemblable block copolymer having first and second blocks in the trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in the trench, the layer having first domains of the first block and second domains of the second block; and selectively removing the first domain to form at least one regularly spaced row of lithography features having the second domain along the trench. | 2015-12-31 |
20150380300 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask. | 2015-12-31 |
20150380301 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of convex portions on a substrate, forming a first film on upper faces and side faces of the convex portions, and forming a second film on the upper faces and the side faces of the convex portions via the first film. The method further includes removing the second film formed on upper faces of the first film to expose the upper faces of the first film. The method further includes implanting impurities into the convex portions in a state where side faces of the first film are covered with the second film and the upper faces of the first film are exposed. The method further includes annealing the convex portions after implanting the impurities into the convex portions. | 2015-12-31 |
20150380302 | SELECTIVE FORMATION OF DIELECTRIC BARRIERS FOR METAL INTERCONNECTS IN SEMICONDUCTOR DEVICES - A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric. | 2015-12-31 |
20150380303 | CONDUCTIVE ELEMENT STRUCTURE AND METHOD - Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask. | 2015-12-31 |
20150380304 | TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT - Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner. | 2015-12-31 |
20150380305 | STRUCTURE AND METHOD TO FORM LINER SILICIDE WITH IMPROVED CONTACT RESISTANCE AND RELIABLITY - A contact structure with improved contact resistance and reliability is provided by forming an inner spacer between a contact liner and dielectric layers laterally surrounding the contact structure. The inner spacer severs as a barrier to prevent diffusion of metals from the contact liner into the dielectric layers. | 2015-12-31 |
20150380306 | Method for Forming a Vertical Electrical Conductive Connection - A method for forming a vertical electrical conductive connection includes forming an electrically insulating layer including at least one hole reaching vertically through the electrically insulating layer and depositing an electrically conductive layer. A surface of the electrically conductive layer includes a recess at the location of the at least one hole of the electrically insulating layer. Further, the method includes forming a smoothing layer on the electrically conductive layer and etching the smoothing layer and the electrically conductive layer until the electrically conductive layer is removed above at least a part of a surface of the electrically insulating layer and remains within the at least one hole. | 2015-12-31 |
20150380307 | METHODS OF FORMING OPENINGS IN SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. | 2015-12-31 |
20150380308 | MASKING METHOD FOR SEMICONDUCTOR DEVICES WITH HIGH SURFACE TOPOGRAPHY - The method comprises the steps of providing a semiconductor body or substrate ( | 2015-12-31 |
20150380309 | Metal-insulator-semiconductor (MIS) contact with controlled defect density - Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor. | 2015-12-31 |