53rd week of 2015 patent applcation highlights part 65 |
Patent application number | Title | Published |
20150380310 | Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation - A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die. | 2015-12-31 |
20150380311 | TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD - A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set. | 2015-12-31 |
20150380312 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed. | 2015-12-31 |
20150380313 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH HORIZONTAL GATE ALL AROUND STRUCTURE - A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0). The method also comprises removing the poly material, forming a plurality of channels from the channel layers, and forming a gate around the channels. | 2015-12-31 |
20150380314 | LOW RESISTANCE AND DEFECT FREE EPITAXIAL SEMICONDUCTOR MATERIAL FOR PROVIDING MERGED FinFETs - A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy. | 2015-12-31 |
20150380315 | Forming Crown Active Regions for FinFETs - A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions. | 2015-12-31 |
20150380316 | UNIFORM EXPOSED RAISED STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICES - The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures. | 2015-12-31 |
20150380317 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 2015-12-31 |
20150380318 | Integrated Circuit Having a Vertical Power MOS Transistor - A method includes forming a buried layer in a substrate, growing an epitaxial layer over the substrate, etching the epitaxial layer and the buried layer to form a first trench and a second trench, wherein the first trench and the second trench are of a same depth and a width of the second trench is greater than a width of the first trench, forming a dielectric layer in a bottom portion of the first trench, forming a first gate electrode in an upper portion of the first trench and filling the second trench with a gate electrode material, forming gate electrodes for a plurality of lateral transistors formed in the substrate, forming a body region, forming a first drain/source region over the body region and forming a second drain/source region over the epitaxial layer. | 2015-12-31 |
20150380319 | FIN-SHAPED FIELD-EFFECT TRANSISTOR PROCESS - A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. | 2015-12-31 |
20150380320 | TEST PATTERN FOR FEATURE CROSS-SECTIONING - A method includes forming a first plurality of instances of a first pattern on a substrate. The first pattern includes a plurality of features defining a first spacing between features in a first direction. The instances in the first plurality are offset from one another at least in a second direction other than the first direction. The substrate is cleaved along a cleavage line. At least a first critical dimension of a feature in the first plurality of instances intersected by the cleavage line is measured. | 2015-12-31 |
20150380321 | System and Method for Dark Field Inspection - A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data. | 2015-12-31 |
20150380322 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device includes providing a wafer including a substrate, a light emitting structure layer and a plurality of electrodes, forming a phosphor layer so as to cover a surface of the wafer on a side of the substrate, dividing the wafer and the phosphor layer so as to form a plurality of light emitting elements, measuring a luminescent chromaticity of the plurality of light emitting elements so as to classify into a first light emitting element having a luminescent chromaticity within a required chromaticity range and a second light emitting element having a luminescent chromaticity outside the required chromaticity range, and forming a second light emitting device that includes the plurality ones of the second light emitting element and the luminescent chromaticity within the required chromaticity range by using the second light emitting element. | 2015-12-31 |
20150380323 | WAFER ETCHING APPARATUS AND METHOD FOR CONTROLLING ETCH BATH OF WAFER - A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride. | 2015-12-31 |
20150380324 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 2015-12-31 |
20150380325 | PHYSICAL LAYOUT FEATURES OF INTEGRATED CIRCUIT DEVICE TO ENHANCE OPTICAL FAILURE ANALYSIS - An integrated circuit device includes an active silicon layer, and at least one passive metal layer placed in an input region and an output region of the device. The at least one passive metal layer has a surface area and thickness for at least one of the input region or the output region to provide a phase shift of an optical laser, the phase shift corresponding to an optimized visibility of the optical laser during an optic failure analysis of the device. | 2015-12-31 |
20150380326 | ELECTROMIGRATION MONITOR - A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect. | 2015-12-31 |
20150380327 | WAFER BONDING STRUCTURES AND WAFER PROCESSING METHODS - A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer. | 2015-12-31 |
20150380328 | Circuit Probing Structures and Methods for Probing the Same - A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component. | 2015-12-31 |
20150380329 | Contact Test Structure and Method - A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together. | 2015-12-31 |
20150380330 | PACKAGE SUBSTRATE, PACKAGE, AND ELECTRONIC DEVICE - A package substrate includes a recessed part and a step part disposed at a periphery thereof, and a lid body is bonded to the step part to cover the recessed part via a bonding layer containing a glass and an electromagnetic wave absorbent material. A ratio (w | 2015-12-31 |
20150380331 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a front electrode and a rear electrode; a conductive plate having a main surface connected to the rear electrode of the semiconductor chip; an insulating plate fixed to a surface of the conductive plate opposite to the main surface; and a ceramic case having first and second terminals buried therein, a cavity accommodating the semiconductor chip, the conductive plate, and the insulating plate, and an electrode surface opposite to an opening portion of the cavity. The first terminal has one end connected to the front electrode of the semiconductor chip, and another end exposed from the electrode surface. The second terminal has one end connected to the main surface of the conductive plate, and another end exposed from the electrode surface. The ceramic case and the insulating plate form a housing. | 2015-12-31 |
20150380332 | Substrate Design with Balanced Metal and Solder Resist Density - A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. | 2015-12-31 |
20150380333 | Glass/Ceramic Replacement of Epoxy for High Temperature Hermetically Sealed Non-Axial Electronic Packages - A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch. | 2015-12-31 |
20150380334 | Advanced Structure for Info Wafer Warpage Reduction - A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers. | 2015-12-31 |
20150380335 | SEMICONDUCTOR DEVICE - A semiconductor device includes a molded body obtained by sealing, with a sealing material, a member including a semiconductor element, an insulating substrate which is bonded to one surface of the semiconductor element, and a printed circuit board which is used for a connection to an external circuit and is bonded to another surface of the semiconductor element. The sealing material includes a first sealing material which is a nanocomposite resin including an epoxy base resin, a curing agent, and an inorganic filler with an average particle size of 1 nm to 100 nm; and a second sealing material which is a thermosetting resin, a thermoplastic resin, or a mixture thereof without an inorganic filler. The sealing material is less likely to be degraded by thermal oxidation, even when the semiconductor element operates at a high temperature of 175° C. or higher, is crack resistant, and has high reliability and durability. | 2015-12-31 |
20150380336 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 2015-12-31 |
20150380337 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 2015-12-31 |
20150380338 | SEMICONDUCTOR DEVICE - In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed. | 2015-12-31 |
20150380339 | Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMP - A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar. | 2015-12-31 |
20150380340 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices - Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width. | 2015-12-31 |
20150380341 | Three-Dimensional Semiconductor Device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 2015-12-31 |
20150380342 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor chip, a signal lead that is arranged in a periphery of the semiconductor chip and has a main surface and a rear surface opposed to the main surface, a wire that electrically connects the semiconductor chip and the main surface of the signal lead, and a sealing body made of sealing resin that seals the semiconductor chip, the signal lead and the wire. The signal lead has, in an extending direction of the signal lead, one end located inside the sealing body, the other end located outside the sealing body, and a wire connection region which is the main surface of the signal lead and to which the wire is connected, and an inner groove is provided in the main surface of the signal lead between the one end and the wire connection region. | 2015-12-31 |
20150380343 | FLIP CHIP MMIC HAVING MOUNTING STIFFENER - A flip-chip mounted semiconductor structure having a flip chip mounting pad and a circuit structure flip-chip mounted to the flip chip mounting pad. The circuit structure includes: a semiconductor die; and a stiffener structure attached to the die, the stiffener structure having a conduit passing through the stiffener structure between a front side of the stiffener structure and a hack side of the stiffener structure, the stiffener and attached die having a degree of rigidity greater than the die alone. | 2015-12-31 |
20150380344 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LEAD FRAME - The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc. | 2015-12-31 |
20150380345 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger. | 2015-12-31 |
20150380346 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface. | 2015-12-31 |
20150380347 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies. | 2015-12-31 |
20150380348 | SEMICONDUCTOR DEVICE PACKAGE WITH A REAR SIDE METALLIZATION OF A SEMICONDUCTOR CHIP CONNECTING AN INTERNAL NODE - A semiconductor package includes a semiconductor chip having a semiconductor body having a main surface and a rear surface opposite the main surface. Control terminals and output terminals are arranged on the main surface. A first metallization layer is formed along the rear surface. A bidirectional switching device is integrated in the semiconductor body and is configured to conduct or block current flowing between the first and second output terminals, based on a biasing of the control terminals. The first metallization layer electrically connects an internal node of the bidirectional switching device. The package further includes a chip-carrier comprising leads extending away from a chip mounting surface. The semiconductor chip is affixed and the main surface with the control terminals and output terminals connected to the lead frame. The package further includes an electrically insulating structure encapsulating the semiconductor chip and exposing the leads. | 2015-12-31 |
20150380349 | GOA CIRCUIT OF ARRAY SUBSTRATE AND DISPLAY APPARATUS - The embodiments of the present disclosure provide a GOA circuit of an array substrate and a display apparatus, which are used in the field of display technology, and enable reducing short-cut of a GOA unit due to ESD, and improving the yield of the GOA circuit. The GOA circuit includes a GOA unit and an STV signal wire electrically connected to the GOA unit, the STV signal wire including a first part and a second part; the GOA circuit further includes a first transparent electrode and an insulating layer located between the first transparent electrode and the first part, the first transparent electrode, the first part and the insulating layer forming a first capacitor. | 2015-12-31 |
20150380350 | Staggered Via Redistribution Layer (RDL) for a Package and a Method for Forming the Same - An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer. | 2015-12-31 |
20150380351 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 2015-12-31 |
20150380352 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop. | 2015-12-31 |
20150380353 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE, AND AN INTEGRATED CIRCUIT DEVICE THEREFROM - A method of fabricating an integrated circuit (IC) device includes mounting, via a first surface thereof, at least one semiconductor die on to a surface of an IC device package, mounting, via an interconnect surface thereof, at least one fuse component on to a second surface of the at least one semiconductor die, the second surface of the at least one semiconductor die having at least one terminal of the at least one active component. The at least one fuse component is mounted such that the interconnect surface of the at least one fuse component is thermally coupled to the second surface of the at least one semiconductor die and electrically coupled to the at least one terminal of the at least one active component. The at least one fuse component is electrically coupled to at least one external connection surface of the IC device package such that the at least one fuse component is electrically coupled in series between the at least one terminal of the at least one active component of the at least one semiconductor die and the at least one external connection surface of the IC device package. | 2015-12-31 |
20150380354 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole. | 2015-12-31 |
20150380355 | SELF-SIMILAR AND FRACTAL DESIGN FOR STRETCHABLE ELECTRONICS - The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical interconnects, electrodes and/or semiconductor components. Stretchability of some of the present systems is achieved via a materials level integration of stretchable metallic or semiconducting structures with soft, elastomeric materials in a configuration allowing for elastic deformations to occur in a repeatable and well-defined way. The stretchable device geometries and hard-soft materials integration approaches of the invention provide a combination of advance electronic function and compliant mechanics supporting a broad range of device applications including sensing, actuation, power storage and communications. | 2015-12-31 |
20150380356 | EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s). | 2015-12-31 |
20150380357 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation. | 2015-12-31 |
20150380358 | Methods and Apparatus Using Front-to-Back Alignment Mark and Placement for Narrow Wafer Scribe Lines - Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed. | 2015-12-31 |
20150380359 | SEMICONDUCTOR PACKAGE INCLUDING MARKING LAYER - A semiconductor package includes at least one semiconductor chip, an encapsulation layer encapsulating the at least one semiconductor chip, a marking layer formed on the encapsulation layer, and a product information mark formed in the marking layer. | 2015-12-31 |
20150380360 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with front-side main surface and a back-side main surface opposed, to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supp_ying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surfaces The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon. | 2015-12-31 |
20150380361 | SEMICONDUCTOR PACKAGE - A semiconductor device is provided. The semiconductor includes a semiconductor chip, a package substrate, and an electromagnetic interference (EMI) shielding layer. The package substrate, arranged under the semiconductor chip, is electrically connected to the semiconductor chip. The package substrate has a receiving groove. The EMI shielding layer is arranged in the receiving groove to shield EMI propagated from a lower surface of the semiconductor chip through the package substrate. | 2015-12-31 |
20150380362 | LEAD FINGER LOCKING STRUCTURE - Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction. | 2015-12-31 |
20150380363 | Methods and Apparatus to Reduce Semiconductor Wafer Warpage in the Presence of Deep Cavities - Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch. Additional methods and apparatus are also disclosed. | 2015-12-31 |
20150380364 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor. | 2015-12-31 |
20150380365 | INDIVIDUALISED VOLTAGE SUPPLY OF INTEGRATED CIRCUITS COMPONENTS AS PROTECTIVE MEANS AGAINST SIDE CHANNEL ATTACKS - A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first ( | 2015-12-31 |
20150380366 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench. | 2015-12-31 |
20150380367 | SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME - A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate. | 2015-12-31 |
20150380368 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device. | 2015-12-31 |
20150380369 | WAFER PACKAGING STRUCTURE AND PACKAGING METHOD - The present invention provides a wafer packaging structure and a wafer packaging method. The wafer packaging structure includes: a substrate, wherein grooves are formed in one surface of the substrate, and chips are arranged in the grooves; a material sealing layer formed on the substrate, wherein connecting components of the chips are exposed from the surface of the material sealing layer; a wiring layer formed on the material sealing layer and electrically connected with the connecting components; a protective film layer formed on the wiring layer, wherein the protective film layer is provided with openings for exposing the wiring layer; lower ball metal layers formed in the openings and connected with the wiring layer; and metal balls formed on the lower ball metal layers. The wafer packaging structure provided by the present invention can be used for packaging a plurality of chips, thereby having a higher integration level and a higher integration degree. | 2015-12-31 |
20150380370 | METHOD FOR ETCHING SEMICONDUCTOR STRUCTURES AND ETCHING COMPOSITION FOR USE IN SUCH A METHOD - A method of etching a semiconductor structure, comprises contacting an under bump metallization (UBM) with an etching composition. The UBM includes an underlying layer comprising titanium and an overlying layer comprising a second metal. The etching composition is a liquid comprising at least 0.1 wt % hydrofluoric acid and at least 0.1 wt % phosphoric acid. | 2015-12-31 |
20150380371 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE INCLUDING A PILLAR CAPPED BY BARRIER LAYER - A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer. | 2015-12-31 |
20150380372 | SEMICONDUCTOR DEVICE INCLUDING A PROTECTIVE FILM - A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion. | 2015-12-31 |
20150380373 | SOLDER BALLS AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME - A solder ball and a semiconductor device using the same are provided. In a Sn-based solder ball in which a first plating layer and a second plating layer are sequentially formed on a core ball, the second plating layer includes a Sn—Ag—Cu alloy, and Ag | 2015-12-31 |
20150380374 | SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating substrate including an insulating plate and a circuit plate; a semiconductor chip having a front surface formed with an electrode and a rear surface fixed to the circuit plate; a printed circuit board including a metal layer, and facing the insulating substrate; a conductive bonding material disposed on the electrode; and a conductive post having a leading end portion electrically and mechanically connected to the electrode through the bonding material, a base portion electrically and mechanically connected to the metal layer, and a central portion. In the conductive post, a wetting angle of a surface of the leading end portion with respect to the molten bonding material is less than the wetting angle of a surface of the central portion. | 2015-12-31 |
20150380375 | MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 2015-12-31 |
20150380376 | SURFACE FINISH FOR WIREBONDING - The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure. | 2015-12-31 |
20150380377 | Multiple bond via arrays of different wire heights on a same substrate - Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires. | 2015-12-31 |
20150380378 | Semiconductor Device - A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad. | 2015-12-31 |
20150380379 | SYSTEM AND METHOD FOR THERMO-COMPRESSION BONDING OF HIGH BUMP COUNT SEMICONDUCTORS - A system and method are provided for enabling the production of semiconductors requiring very high precision thermo-compression bonding, the system comprising a thermo-compression bonding system having force and/or distance measuring sensors configured to sense thermal expansion of system components and a controller configured to counteract such expansion by exercising appropriate control over such system. This system and method may be used for both constant force profile applications as well as those requiring variable force during a bonding operation. | 2015-12-31 |
20150380380 | SYSTEMS AND METHODS FOR DETERMINING AND ADJUSTING A LEVEL OF PARALLELISM RELATED TO BONDING OF SEMICONDUCTOR ELEMENTS - A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure configured to support a substrate; a bond head assembly, the bond head assembly including a bonding tool configured to bond a plurality of semiconductor elements to the substrate; and a calibration tool including a contact portion configured to be positioned between the bonding tool and the support structure, the contact portion configured to be contacted by each of the bonding tool and the support structure simultaneously during a calibration operation. | 2015-12-31 |
20150380381 | FLIP CHIP BONDER AND FLIP CHIP BONDING METHOD - Provided is a flip chip bonder including: a pickup flipping collet configured to flip a chip; and a bonding tool configured to receive the chip flipped with the pickup flipping collet from the pickup flipping collet and to bond the received chip to a circuit board. The pickup flipping collet includes a cooling channel through which cooling air flows to cool the pickup flipping collet. Thus, bonding time can be reduced without lowering bonding quality. | 2015-12-31 |
20150380382 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm. | 2015-12-31 |
20150380383 | METHOD FOR CARRYING OUT A CONDUCTIVE DIRECT METAL BONDING - A method includes a) Providing a first substrate covered by a metal layer and a second substrate covered by a metal layer, b) Bringing into direct contact the metal layers so as to form a bonding interface having metal material bridges separated by cavities which are fluidly connected to each other, d) Immersing the bonding interface in an oxidizing fluid so as to form a metal oxide which fills at least in part the cavities and metal/metal oxide/metal contact areas. A structure is also provided having a first substrate, a first metal layer, a second metal layer forming a bonding layer with the first metal layer, and a second substrate, the bonding interface having: metal material bridges separated by cavities, a metal oxide partially filling the cavities, and metal/metal oxide/metal contact areas. | 2015-12-31 |
20150380384 | Universal Surface-Mount Semiconductor Package - In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam. | 2015-12-31 |
20150380385 | STACKED IC CONTROL THROUGH THE USE OF HOMOGENOUS REGION - A package includes a semiconductor chip. The semiconductor chip includes a substrate, a plurality of dielectric layers underlying the substrate, a dielectric region penetrating through the plurality of dielectric layers, and a metal pad overlapped by the dielectric region. A conductive plug penetrates through the substrate, the dielectric region, and the metal pad. | 2015-12-31 |
20150380386 | MICROELECTRONIC PACKAGES HAVING EMBEDDED SIDEWALL SUBSTRATES AND METHODS FOR THE PRODUCING THEREOF - Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate. | 2015-12-31 |
20150380387 | STACKED CHIPS ATTACHED TO A HEAT SINK HAVING BONDING PADS - An integrated circuit comprises a heat sink devoid of electronic components and interposed between a back side of a bottom electronic chip and an upper exterior side of an encapsulation, the sink comprising a front side placed on the back side of the bottom electronic chip. The back side of the bottom electronic chip comprises pads and the front side of the sink comprises pads mechanically fastened to facing pads of the back side of the bottom electronic chip. | 2015-12-31 |
20150380388 | Fan-Out Package Structure and Methods for Forming the Same - A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. One of the device die and the plurality of dies includes a semiconductor substrate and a through-via penetrating through the semiconductor substrate, A polymer region includes portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first and the second plurality of metal pillars. Redistribution lines are formed over the first and the second plurality of metal pillars. | 2015-12-31 |
20150380389 | RED FLIP CHIP LIGHT EMITTING DIODE, PACKAGE, AND METHOD OF MAKING THE SAME - Flip chip LEDs comprise a transparent carrier and an active material layer such as AlInGaP bonded to the carrier and that emits light between about 550 to 650 nm. The flip chip LED has a first electrical terminal in contact with a first region of the active material layer, and a second electrical terminal in contact with a second region of the active material layer, wherein the first and second electrical terminals are positioned along a common surface of the active material layer. Chip-on-board LED packages comprise a plurality of the flip chip LEDs with respective first and second electrical terminals interconnected with one another. The package may include Flip chip LEDs that emit light between 420 to 500 nm, and the flip chip LEDs are covered with a phosphorus material comprising a yellow constituent, and may comprise a transparent material disposed over the phosphorus material. | 2015-12-31 |
20150380390 | SIMPLE LED PACKAGE SUITABLE FOR CAPACITIVE DRIVING - The invention relates to a LED package ( | 2015-12-31 |
20150380391 | PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME - A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided. | 2015-12-31 |
20150380392 | PACKAGE WITH MEMORY DIE AND LOGIC DIE INTERCONNECTED IN A FACE-TO-FACE CONFIGURATION - A semiconductor device package includes a logic die coupled to a memory die in a face-to-face configuration with small interconnect pitch (at most about 50 μm) and small distances between the die (at most about 50 μm). The logic die may be connected to a redistribution layer with terminals that are fanned out, or spaced out, to provide space for the face-to-face connections to the memory die. The memory die may be connected to the logic die before or after the logic die is connected to the redistribution layer. The logic die and the memory die may be at least partially encapsulated in an encapsulant. Routing in the redistribution layer may connect the logic die and/or the memory die to ball grid array terminals coupled to the bottom of the redistribution layer and/or discrete devices coupled to the redistribution layer. | 2015-12-31 |
20150380393 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including an insulating plate and a circuit plate disposed on a main surface of the insulating plate; a semiconductor chip having a front surface provided with an electrode and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate and including a metal layer; a conductive post having one end electrically and mechanically connected to the electrode and another end electrically and mechanically connected to the metal layer; a passive element fixed to the printed circuit board; and a plurality of positioning posts fixed to the printed circuit board to position the passive element. | 2015-12-31 |
20150380394 | SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME - A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode. | 2015-12-31 |
20150380395 | FLIP-CHIP ASSEMBLY PROCESS COMPRISING PRE-COATING INTERCONNECT ELEMENTS - A method of assembling a first and a second electronic components includes forming connection elements on an assembly surface of the first component and forming connection elements on an assembly surface of the second component. The method also includes depositing a liquid layer of electrically-insulating curable material on the assembly surface of the first and/or of the second component and arranging the first and second components on each other to place the connection elements of the second component in front of the connection elements of the first component. The method further includes applying a force along a predetermined direction and the first and/or the second components to create electric interconnects each formed of a connection element of the first component and of a connection element of the second component and curing the curable material. | 2015-12-31 |
20150380396 | SCRs with Checker Board Layouts - An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. | 2015-12-31 |
20150380397 | ESD Protection for Advanced CMOS Processes - Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit. | 2015-12-31 |
20150380398 | FORMING JFET AND LDMOS TRANSISTOR IN MONOLITHIC POWER INTEGRATED CIRCUIT USING DEEP DIFFUSION REGIONS - A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being formed using a first body region, and a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer with a channel being formed in a second body region. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region together with the firs body region establish a pinch off voltage of the JFET device; and a second deep diffusion region formed under the second body region and in electrical contact with the second body region where the second deep diffusion region forms a reduced surface field (RESURF) structure in the LDMOS transistor. | 2015-12-31 |
20150380399 | DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device. | 2015-12-31 |
20150380400 | SEMICONDUCTOR DEVICE - A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential. | 2015-12-31 |
20150380401 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first element portion including an IGBT and a second element portion including a circuit that controls the IGBT on the same semiconductor substrate. The novel structure reduces the size of the entire circuit and includes a drift region on a front surface of the substrate; a region in a surface layer of the drift region which is opposite to the substrate; an insulator layer that passes through the region in a depth direction and reaches the drift region, the insulator layer provided at a boundary between the first and second element portions, and separating the region into a first region in the first element portion and having the emitter potential of the IGBT and a second region in the second element portion; and a first contact electrode that contacts the second region, and that is electrically connected to an emitter electrode of the IGBT. | 2015-12-31 |
20150380402 | POWER INTEGRATED DEVICES, ELECTRONIC DEVICES INCLUDING THE SAME AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided. | 2015-12-31 |
20150380403 | Semiconductor Device with Thermally Grown Oxide Layer Between Field and Gate Electrode and Method of Manufacturing - A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material. | 2015-12-31 |
20150380404 | NON-PLANAR STRUCTURE WITH EXTENDED EXPOSED RAISED STRUCTURES AND SAME-LEVEL GATE AND SPACERS - A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication. | 2015-12-31 |
20150380405 | REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS - After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions. | 2015-12-31 |
20150380406 | GATE STRUCTURE HAVING SPACER WITH FLAT TOP SURFACE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate. The semiconductor structure includes a first spacer formed on a sidewall of the first gate structure. In addition, a top surface of the first spacer is parallel to a top surface of the substrate. | 2015-12-31 |
20150380407 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming a gate dielectric layer over a substrate; forming an etch stop layer over the gate dielectric layer; forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers a second portion of the etch stop layer; exposing the second portion of the etch stop layer by removing the sacrificial compound; and forming a second work function layer over the second portion of the etch stop layer and the first work function layer. | 2015-12-31 |
20150380408 | Method of Forming Different Voltage Devices with High-K Metal Gate - A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( | 2015-12-31 |
20150380409 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 2015-12-31 |