53rd week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150380410 | Structure and Method for SRAM FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer. | 2015-12-31 |
20150380411 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure, which comprises a semiconductor substrate and at least two semiconductor fins located on the semiconductor substrate, wherein: the at least two semiconductor fins are parallel to each other; and the parallel sidewall surfaces of the at least two semiconductor fins have different crystal planes. The present invention further provides a method for manufacturing aforesaid semiconductor structure. The technical solution provided in the present invention exhibits following advantages: it makes possible to form two parallel semiconductor fins with different sidewall crystal planes on the same substrate through changing crystal orientation of a part of the substrate; the two semiconductor fins individually have {100} sidewall crystal plane and {110} sidewall crystal plane, and are applied for forming NMOS and PMOS devices respectively; in this way, the overall performance of CMOS circuits is improved; besides, the two semiconductor fin structures are parallel to each other, such that it becomes less difficult to perform lithography and avoids wasting of wafer area. | 2015-12-31 |
20150380412 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 2015-12-31 |
20150380413 | COMPACT CMOS DEVICE ISOLATION - An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well. | 2015-12-31 |
20150380414 | Strained Channel Dynamic Random Access Memory Devices - DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. | 2015-12-31 |
20150380415 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line. | 2015-12-31 |
20150380416 | SEMICONDUCTOR DEVICE - Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another. | 2015-12-31 |
20150380417 | Field-Effect Transistor, and Memory and Semiconductor Circuit Including the Same - Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced. | 2015-12-31 |
20150380418 | THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF - A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line. | 2015-12-31 |
20150380419 | METHOD OF SELECTIVELY DEPOSITING FLOATING GATE MATERIAL IN A MEMORY DEVICE - Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material. | 2015-12-31 |
20150380420 | NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height - A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels. | 2015-12-31 |
20150380421 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench. | 2015-12-31 |
20150380422 | Vertical Floating Gate NAND with Selectively Deposited ALD Metal Films - A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide. | 2015-12-31 |
20150380423 | METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES - A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers. | 2015-12-31 |
20150380424 | METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES - A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses. | 2015-12-31 |
20150380425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode. | 2015-12-31 |
20150380426 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns. | 2015-12-31 |
20150380427 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers. | 2015-12-31 |
20150380428 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a source layer; a stacked body; a columnar section; and a contact section extending in the stacking direction and piercing through the stacked body and connected to the source layer. The columnar section including: a channel body extending in the stacking direction and including a lower end, the lower end projecting into the source layer; and a charge storage film provided between the channel body and each of the electrode layers. The source layer including: a first film including metal; and a second film having electric conductivity provided between the first film and the lower end of the channel body, the second film being in contact with the lower end and covering the lower end. | 2015-12-31 |
20150380429 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer. | 2015-12-31 |
20150380430 | JUNCTION FORMATION FOR VERTICAL GATE 3D NAND MEMORY - A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material. | 2015-12-31 |
20150380431 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL AND AIR GAP, AND METHOD OF MANUFACTURING THEREOF - A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure. | 2015-12-31 |
20150380432 | Methods Of Forming A Charge-Retaining Transistor - A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed. | 2015-12-31 |
20150380433 | Thin Film Transistor, Array Substrate and Display Device - The present invention provides a TFT, an array substrate and a display device. The TFT includes a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. The source electrode and the drain electrode are arranged on different layers. The semiconductor layer is in electrical connection to the source electrode and the drain electrode, respectively; wherein, a region on the semiconductor layer which is corresponding to a region between the source electrode and the drain electrode is a channel region. The present invention also provides an array substrate and a display device comprising the on TFT. | 2015-12-31 |
20150380434 | ARRAY SUBSTRATE AND A DISPLAY DEVICE - The embodiment of the present invention provides an array substrate and a display device, which relates to the field of display technology, where the aperture opening ratio can be increased; the array substrate comprises a plurality of subpixels, each of the subpixels comprising: at least one thin film transistor, an organic resin layer, and uncontacted first pixel electrode and second pixel electrode arranged along the data line direction; the first pixel electrode extends to the above of a first gate line, the second pixel electrode extends to the above of a second gate line, the first gate line and the second gate line are adjacent to each other; the first pixel electrodes of two adjacent subpixels located at two sides of the first gate line are connected above the first gate line, the second pixel electrodes of two adjacent subpixels located at two sides of the second gate line are connected above the second gate line; the first pixel electrodes of two adjacent subpixels are electrically connected with the drain of at least one thin film transistor, the second pixel electrodes are electrically connected with the drain of at least one thin film transistor. It is used in manufacture of an array substrate and a display device that need to increase the aperture opening ratio. | 2015-12-31 |
20150380435 | PIXEL STRUCTURE, LIQUID CRYSTAL DISPLAY ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - A pixel structure is disclosed. The pixel structure includes a plurality of data lines arranged in a first direction, and a plurality of gate lines arranged in a second direction. The plurality of data lines intersect with the plurality of gate lines near a plurality of sub-pixels. In addition, each of the plurality of sub-pixels includes a thin film transistor, and a pixel electrode. The plurality of sub-pixels includes a plurality of first rows of sub-pixels, and a plurality of second rows of sub-pixels, where the first rows of sub-pixels and the second rows of sub-pixels are interleaved, each sub-pixel in the first rows of sub-pixels is provided with a signal over a second-closest data line, and each sub-pixel in the second rows of sub-pixels is provided with a signal over a first-closest data line. | 2015-12-31 |
20150380436 | METHODS OF FORMING PRINTABLE INTEGRATED CIRCUIT DEVICES AND DEVICES FORMED THEREBY - Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. | 2015-12-31 |
20150380437 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, MANUFACTURING METHOD THEREFOR AND DISPLAY DEVICE THEREOF - A thin-film transistor array substrate is disclosed. The array substrate includes a support substrate, a plurality of scan lines on the support substrate, and a plurality of data lines on the support substrate, where the plurality of scan lines are insulated and intersect with the plurality of data lines. The array substrate also includes a plurality of pixel units located near intersections of the scan lines and the data lines, a first metal layer on the support substrate, and an insulating layer on the first metal layer, where the insulating layer includes a plurality of via holes, each exposing a portion of the first metal layer. The array substrate also includes a semiconductor layer on the insulating layer and electrically connected to the first metal layer, and a second metal layer on the semiconductor layer and electrically connected to the semiconductor layer. | 2015-12-31 |
20150380438 | TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation. | 2015-12-31 |
20150380439 | FLEXIBLE DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND FLEXIBLE DISPLAY DEVICE - The present invention provides a flexible display substrate, comprising a flexible base; an ultraviolet reflecting layer disposed on the flexible base and capable of reflecting ultraviolet light and transmitting visible light, comprising a stacked structure consisting of alternate first transparent material layers and second transparent material layers, wherein the numbers of the two kinds of transparent material layers are equal, and are at least two respectively, and the two kinds of transparent material layers also satisfy: 4nd=λ, wherein d is the thickness of any one of the transparent material layers, n is a refractive index of the transparent material layer and λ is the wavelength of ultraviolet light; and a display structure disposed above the ultraviolet reflecting layer. The present invention is applicable to flexible display substrates, particularly flexible array substrates comprising low-temperature polycrystalline silicon thin film transistors. | 2015-12-31 |
20150380440 | THIN-FILM AMBIPOLAR LOGIC - An ambipolar electronic device is disclosed. The device may include a field-effect transistor (FET), which may have a handle substrate layer, two contacts and an inorganic crystalline layer between the handle substrate layer and the contacts. The inorganic crystalline layer may have a doped channel region between the contacts. The FET may also have a dielectric layer between the contacts, attached to the inorganic crystalline layer, and a gate layer, attached to the dielectric layer. The FET may conduct current, in response to a first gate voltage applied to the gate layer, using electrons as a majority carrier, along the length of the channel region between the contacts. The FET may also conduct current, in response to a second gate voltage applied to the gate layer, using holes as a majority carrier, along the length of the channel region between the contacts. | 2015-12-31 |
20150380441 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, LIQUID CRYSTAL DISPLAY PANEL AND DISPLAY DEVICE - An array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device are provided, the array substrate comprises a base substrate, and thin film transistors and pixel electrodes provided on the base substrate, the pixel electrode and the active layer in the thin film transistor are provided in the same layer. The active layer is formed of transparent oxide semiconductor material, and the concentration of carriers in the oxide semiconductor material may be increased by performing a plasma process on the oxide semiconductor material, thus the pixel electrode may be manufactured by using the oxide semiconductor material used for manufacturing the active layer, thereby the pixel electrode and the active layer can be provided in the same layer, the number of the masks can be reduced, the manufacturing process is simplified, production cost is saved, the productivity is increased, and the manufacturing time is shortened. | 2015-12-31 |
20150380442 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device incorporating the array substrate are disclosed. The array substrate comprises a first material layer located on a thin film transistor, the first material layer having a first via hole; a conductive interlayer located on the first material layer, the conductive interlayer being electrically connected with the drain of the thin film transistor through the first via hole; and a second material layer located on the conductive interlayer, the second material layer having a second via hole staggered with the first via hole. A pixel electrode is located on the second material layer. The conductive interlayer is electrically connected with the pixel electrode through the second via hole, so as to form a storage capacitance with a common electrode. The array substrate has an increased storage capacitance and provides the display device with improved display stability, pixel opening ratio, and display quality. | 2015-12-31 |
20150380443 | METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of forming a metal pattern includes disposing a gate metal layer on a substrate; disposing a photoresist layer on the gate metal layer; etching portions of the photoresist layer to form a first photo pattern; etching portions of the gate metal layer to form a gate pattern including a gate electrode, in which the gate metal layer is patterned using the first photo pattern as a mask; ashing an end portion of the first photo pattern to form a second photo pattern; disposing a first gate insulating layer over the substrate and the second photo pattern; removing the second photo pattern and a portion of the first gate insulating layer disposed over the second photo pattern; and disposing a second insulating layer over the gate pattern and the remaining portions of the first gate insulating layer. | 2015-12-31 |
20150380444 | Active Array Substrate and Manufacturing Method Thereof - An active array substrate includes a flexible substrate, an inorganic barrier layer, and at least one active component. The inorganic barrier layer covers the flexible substrate. The inorganic barrier layer has a through hole therein. The through hole of the inorganic barrier layer exposes the flexible substrate. The active component is disposed on the inorganic barrier layer. | 2015-12-31 |
20150380445 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode. | 2015-12-31 |
20150380446 | MANUFACTURING METHOD OF SENSING INTEGRATED CIRCUIT - A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures. | 2015-12-31 |
20150380447 | DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE - Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device. | 2015-12-31 |
20150380448 | BACK SIDE ILLUMINATED SEMICONDUCTOR STRUCTURE WITH SEMICONDUCTOR CAPACITOR CONNECTED TO FLOATING DIFFUSION NODE - There is provided a back side illuminated semiconductor structure with a semiconductor capacitor connected to a floating diffusion node in which the semiconductor capacitor for reducing a dimension of the floating diffusion node is provided above the floating diffusion node so as to eliminate the influence thereto by incident light and enhance the light absorption efficiency. | 2015-12-31 |
20150380449 | SOLID-STATE IMAGE PICK-UP APPARATUS, IMAGE PICK-UP SYSTEM, AND METHOD OF DRIVING SOLID-STATE IMAGE PICK-UP APPARATUS - A solid-state image pick-up apparatus of an example includes a photoelectric conversion portion, a transfer transistor configured to transfer a charge in the photoelectric conversion portion, and a signal output circuit configured to supply selectively a first voltage to turn on the transfer transistor and a second voltage to turn off the transfer transistor to the transfer transistor. The signal output circuit is configured to supply the second voltage having a voltage value selected from two or more different voltage values based on an output signal from a pixel. | 2015-12-31 |
20150380450 | IMAGING DEVICE AND ELECTRONIC DEVICE - An imaging device with high productivity and improved dynamic range is provided. The imaging device includes a pixel driver circuit and a photoelectric conversion element including a p-type semiconductor, an n-type semiconductor, and an i-type semiconductor. In a plan view, the total area of a part of the i-type semiconductor overlapped with neither a metal material nor a semiconductor material constituting the pixel driver circuit is preferably greater than or equal to 65%, more preferably greater than or equal to 80%, and still more preferably greater than or equal to 90% of the area of the whole i-type semiconductor. Plural photoelectric conversion elements are provided in the same semiconductor, whereby a process for separating the photoelectric conversion elements can be omitted. The i-type semiconductors in the plural photoelectric conversion elements are separated from each other by the p-type semiconductor or the n-type semiconductor. | 2015-12-31 |
20150380451 | IMAGING DEVICE, MONITORING DEVICE, AND ELECTRONIC APPLIANCE - A highly accurate imaging device or a highly accurate imaging device capable of detecting differences is provided. A configuration including a circuit in which variation in threshold voltage among amplifier transistors of pixels is corrected is employed. The configuration reduces variation in difference data due to variation in the threshold voltage among the amplifier transistors of the pixels to obtain highly accurate imaging data. Furthermore, charge corresponding to difference data between imaging data in an initial frame and imaging data in a current frame is accumulated in pixels and the difference data is read from each pixel, whereby highly accurate difference data is obtained when whether there is a difference between the initial frame and the current frame is determined. | 2015-12-31 |
20150380452 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: an organic substrate; an integrated circuit and a chip part provided on the organic substrate; a molded section including a central portion and a peripheral portion, and forming, as a whole, a concave shape, the central portion sealing the integrated circuit and the chip part on the organic substrate, and the peripheral portion standing around the central portion; and a solid-state image pickup element provided on the central portion of the molded section, the solid-state image pickup element having a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section. | 2015-12-31 |
20150380453 | PHOTODETECTOR AND IMAGE SENSOR INCLUDING THE SAME - A photodetector may have a structure including conductive patterns and an intermediate layer interposed between the conductive patterns. A length L of at least one side of the second conductive pattern that overlaps the first conductive pattern and the intermediate layer satisfies the equation L=λ/2n | 2015-12-31 |
20150380454 | CAMERA MODULE AND METHOD OF MANUFACTURING THE SAME - Embodiments of the present invention provide a camera module and a method of manufacturing the same, the camera module comprising a sensor assembly, at least one semiconductor substrate, and a molding compound; wherein the sensor assembly comprises a semiconductor die, a sensor circuit disposed on the top surface of the semiconductor die, and a transparent cover coupled to the semiconductor die over the top surface of the semiconductor die; wherein each semiconductor substrate is disposed around the sensor assembly in a horizontal direction; and wherein the molding compound is filled between each semiconductor substrate and the sensor assembly. | 2015-12-31 |
20150380455 | SEMICONDUCTOR PHOTODETECTION DEVICE - A plurality of semiconductor photodetecting elements have a planar shape having a pair of first sides opposed to each other in a first direction and a pair of second sides being shorter than the pair of first sides and opposed to each other in a second direction perpendicular to the first direction, and are disposed on a base so as to be adjacent to each other in juxtaposition. A plurality of bump electrodes each are disposed on sides where the pair of first sides lie in each semiconductor photodetecting element, to electrically and mechanically connect the base to each semiconductor photodetecting element. A plurality of dummy bumps are disposed so that at least one dummy bump is disposed on each of sides where the pair of second sides lie in each semiconductor photodetecting element, to mechanically connect the base to each semiconductor photodetecting element. | 2015-12-31 |
20150380456 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion. | 2015-12-31 |
20150380457 | DETECTOR, PET SYSTEM AND X-RAY CT SYSTEM - Each semiconductor chip of a detector comprises a semiconductor substrate having a plurality of photodetector units, an insulating layer formed on a front face of the semiconductor substrate, a common electrode arranged on the insulating layer, a readout line for electrically connecting a quenching resistance of each photodetector unit and the common electrode to each other, and a through electrode extending from the common electrode to a rear face of the semiconductor substrate through a through hole of the semiconductor substrate. | 2015-12-31 |
20150380458 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF FABRICATING THE SAME, AND CAMERA MODULE - According to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion lements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed. | 2015-12-31 |
20150380459 | MESA STRUCTURE DIODE WITH APPROXIMATELY PLANE CONTACT SURFACE - Electronic device with mesa structure diodes connected in series, each comprising:
| 2015-12-31 |
20150380460 | LIGHT-EMITTING DEVICE, METHOD FOR DESIGNING LIGHT-EMITTING DEVICE, METHOD FOR DRIVING LIGHT-EMITTING DEVICE, ILLUMINATION METHOD, AND METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - An object of the present invention is to provide a light-emitting device that can implement a natural, vivid, highly visible and comfortable appearance of colors and appearance of objects as if the objects are seen outdoors, and to provide a light-emitting device that can change the appearance of colors of the illuminated objects so as to satisfy the requirements for various illuminations, and a method for designing thereof. Another object of the present invention is to improve the appearance of colors of a light-emitting device which currently exists or is in use, and which includes a semiconductor light-emitting device of which appearance of colors is not very good. Moreover, another object of the present invention is to provide a method for driving the light-emitting device, an illumination method by the device, and a method for manufacturing the light-emitting device. | 2015-12-31 |
20150380461 | P-N JUNCTION OPTOELECTRONIC DEVICE FOR IONIZING DOPANTS BY FIELD EFFECT - An optoelectronic device comprising a mesa structure including:
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20150380462 | METHOD OF COMBINING LEDS IN A PACKAGING UNIT - A method of combining LEDs in a packaging unit includes determining a color locus of a multiplicity of LEDs, classifying the LEDs into a plurality of different color locus ranges, each LED classified into a color locus range including the determined color locus of the respective LED, and arranging the LEDs in the packaging unit such that the packaging unit contains a plurality of successive sequences respectively of a plurality of LEDs, wherein each sequence respectively has exactly one LED from each of the color locus ranges, and the LEDs of the different color locus ranges are respectively arranged in the same order within the sequences, wherein the LEDs are arranged in the packaging unit such that they are removable from the packaging unit. | 2015-12-31 |
20150380463 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening. | 2015-12-31 |
20150380464 | MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes. | 2015-12-31 |
20150380465 | SERIAL MODULE OF ORGANIC SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a serial module of organic solar cells and the method for manufacturing the same. The structure comprises a transparent conductive layer composed by a plurality of conductive blocks, an active layer having notches on the periphery, and a metal layer composed by a plurality of metal blocks. The active layer according to the present invention is a complete layer except the notches on the periphery for exposing a portion of the transparent conductive layer. The metal blocks can contact the conductive blocks of adjacent organic solar cell via the exposure areas and thus connecting the organic solar cells in series. The present invention can improves the power generating efficiency of organic solar cells in a limited space, which is beneficial to the development of promotion of future organic solar cells. | 2015-12-31 |
20150380466 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are an organic light emitting display device and a method for manufacturing the same. A color filter is disposed on a substrate. An overcoating layer is disposed on the color filter and includes a plurality of protrusions or a plurality of recesses. The plurality of protrusions and the plurality of recesses are disposed on the color filter to be overlapped with the color filter. A buffer layer for reducing step difference is disposed on the overcoating layer. The buffer layer has a higher refractive index than the overcoating layer and reduces a step difference caused by the plurality of protrusions and the plurality of recesses. An organic light emitting element including an anode, an organic light emitting layer, and a cathode is disposed on the buffer layer. Since the buffer layer has a higher refractive index than the overcoating layer, light extraction efficiency can be increased. | 2015-12-31 |
20150380467 | TOUCH DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A touch display device and a method for manufacturing the same are provided. The touch display device includes a first substrate, a second substrate disposed opposite to the first substrate, and at least one touch signal transmission unit. The touch signal transmission unit includes: a first conductive layer located above a side of the first substrate facing the second substrate; a second conductive layer located above a side of the second substrate facing the first substrate; a touch signal transmission layer, located between the second conductive layer and the second substrate and electrically connected to the first conductive layer via the second conductive layer; and a spacer located between the first substrate and the second substrate, where a vertical projection of the spacer onto the first substrate at least partially overlaps vertical projections of the first conductive layer and the second conductive layer onto the first substrate. | 2015-12-31 |
20150380468 | WHITE ORGANIC LIGHT EMITTING DEVICE - A white organic light emitting device is disclosed. The device includes a first light emitting unit, which has first, second, and third light emitting element. The first light emitting element includes a blue light emitting material, the second light emitting element includes a yellow light emitting material, and the third light emitting element includes a yellow light emitting material. In addition, the first light emitting unit, the second light emitting unit and the third light emitting unit are arranged in parallel. | 2015-12-31 |
20150380469 | METHOD FOR MANUFACTURING DISPLAY DEVICE - The present invention provides a display device which inhibits deterioration in display quality caused by color mixture of luminescent layers. In a case where vapor deposition particles are deposited onto a substrate, P+2Lc≧{(Ts×M+0.96×G×Wn)/(Ts−G)}+2Dm and 3 μm≦Dm≦5 μm are satisfied, where “M” is a width of a mask opening, “Wn” is a width of an injection hole, “G” is a distance between the TFT substrate and a vapor deposition mask, “Ts” is a distance between the TFT substrate and a vapor deposition source, “P” is a width of a first pixel opening, and “Lc” is a width of a non-display region. | 2015-12-31 |
20150380470 | Organic Light-Emitting Diode Display With White and Blue Diodes - An organic light-emitting diode display may have an array of pixels with sets of pixels arranged in rows and columns. Each set of pixels includes a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixels each have a white diode and a red color filter element to impart a red color to white light from that white diode. The green pixels each have a white diode and a green color filter element to impart a green color to white light from that white diode. The white pixels each have an unfiltered white diode. The blue pixels each have an unfiltered blue diode. The unfiltered white and blue diodes do not have color filters and emit white and blue light for the white and blue pixels, respectively. The white and blue diodes may be tandem diodes having two or more emissive layers. | 2015-12-31 |
20150380471 | PIXEL ARRANGEMENT STRUCTURE, DISPLAY DEVICE AND DISPLAY METHOD THEREOF - A pixel arrangement structure according to the present disclosure may include pixel units parallel to each other. The pixel units each includes a plurality of first pixels and second pixels spaced from each other. The first pixels each include a first sub-pixel located in a first row, a second sub-pixel located in a second row, and a third sub-pixel located in third and fourth rows. The second pixels each include a third sub-pixel located in the first and second rows, a first sub-pixel located in the third row, and a second sub-pixel located in the fourth row. The first sub-pixels and second sub-pixels are arranged horizontally, while the third sub-pixels are arranged longitudinally. | 2015-12-31 |
20150380472 | AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR - An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light. | 2015-12-31 |
20150380473 | PORTABLE ELECTRONIC APPARATUS - A portable electronic apparatus comprises a substrate comprising a first surface and a second surface; a plurality of pixel electrodes arranged over the first surface of the substrate; a pixel-defining layer arranged over the first surface of the substrate such that at least a portion of each of the plurality of pixel electrodes is exposed; a plurality of protrusions formed over the pixel-defining layer; and an electronic component arranged over the second surface of the substrate and attached to the substrate, the electronic component having a polygonal shaped surface facing and substantially parallel to the second surface of the substrate. When viewed in a direction perpendicular to the second surface, imaginary straight lines that pass the plurality of protrusions are substantially parallel to at least one among sides of the polygonal shaped surface and do not pass the exposed portions of the plurality of pixel electrodes. | 2015-12-31 |
20150380474 | DISPLAY DEVICE - A display device includes a display panel having an encapsulation substrate over a display substrate, at least one film on the display panel, a black matrix on the at least one functional film, and a viewing angle controller on the display panel and overlapping at least the black matrix. | 2015-12-31 |
20150380475 | BOTTOM-EMITTING SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD OF SUBSTRATE - A bottom-emitting substrate, a display device and a method for manufacturing the bottom emitting substrate are provided. The bottom-emitting substrate comprises: a base substrate ( | 2015-12-31 |
20150380476 | ARRAY SUBSTRATE, MANUFACTURE METHOD THEREOF, AND DISPLAY PANEL - An array substrate, a manufacture method of the array substrate, and a display panel are configured to achieve a combination of solar energy technology and the OLED display technology. The array substrate includes substrate, scanning lines, data lines, a thin film transistor (TFT), a common electrode and a pixel electrode. The array substrate further includes a light-emitting structure configured to provide a backlight source, a solar cell structure and a power output line. The light-emitting structure is provided between the common electrode and the pixel electrode. The solar cell structure is provided between the substrate and the common electrode. The power output line is provided in a same layer as the common electrode and is electrically connected to the solar cell structure so as to transmit electric energy generated by the solar cell structure to an external circuit. | 2015-12-31 |
20150380477 | MIM/RRAM Structure with Improved Capacitance and Reduced Leakage Current - Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix. | 2015-12-31 |
20150380478 | SEMICONDUCTOR DEVICE WITH METAL EXTRUSION FORMATION - Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material. | 2015-12-31 |
20150380479 | SEMICONDUCTOR DEVICE FABRICATING METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film. | 2015-12-31 |
20150380480 | SEMICONDUCTOR DEVICE - A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [μm | 2015-12-31 |
20150380481 | CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR - Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator. | 2015-12-31 |
20150380482 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode. | 2015-12-31 |
20150380483 | COMPACT GUARD RING STRUCTURE FOR CMOS INTEGRATED CIRCUITS - An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings are formed in P-wells. The interleaving deep N-wells and P-wells of the N-type guard ring may be connected to ground or be left floating. By integrating P-well contacts in the N-type guard ring, P-well contacts, or P-taps, for the P-type guard ring can be eliminated. | 2015-12-31 |
20150380484 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench. | 2015-12-31 |
20150380485 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view. | 2015-12-31 |
20150380486 | ELECTRONIC DEVICE - An electronic device includes: a substrate; a nanowire mesh formed on the substrate and including a plurality of crossing points cross-coupled with a plurality of unit nanowires; and a first electrode and a second electrode electrically connected to the nanowire mesh. | 2015-12-31 |
20150380487 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends. | 2015-12-31 |
20150380488 | JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer. | 2015-12-31 |
20150380489 | LOW RESISTANCE AND DEFECT FREE EPITAXIAL SEMICONDUCTOR MATERIAL FOR PROVIDING MERGED FinFETs - A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy. | 2015-12-31 |
20150380490 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A MISFET has a threshold voltage that is not undesirably increased due to channel narrowing of the MISFET, and the MISFET is reduced in size and increased in withstand voltage. An anti-inversion p-type channel stopper region provided below an element isolation trench has an end that projects toward a channel region below a gate oxide film, and terminates short of the channel region. That is, the end is offset from the end of the channel region (the end of the element isolation trench). This suppresses diffusion in a lateral direction (channel region direction) of an impurity in the p-type channel stopper region, and thus suppresses a decrease in carrier concentration at the end of the channel region. As a result, a local increase in threshold voltage is suppressed. | 2015-12-31 |
20150380491 | METHOD FOR PRODUCING A MICROELECTRONIC DEVICE - A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: | 2015-12-31 |
20150380492 | Semiconductor Device Containing Chalcogen Atoms and Method of Manufacturing - A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm | 2015-12-31 |
20150380493 | MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER - An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 mΩ·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter. | 2015-12-31 |
20150380494 | SEMICONDUCTOR DEVICE - A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature. | 2015-12-31 |
20150380495 | NITRIDE SEMICONDUCTOR LAYER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor layer spreading along a first surface is provided. The nitride semiconductor layer includes a first region and a second region. A length of the first region in a first direction parallel to the first surface is longer than a length of the first region in a second direction parallel to the first surface and perpendicular to the first direction. The second region is arranged with the first region in the second direction. A length of the second region in the first direction is longer than a length of the second region in the second direction. A c-axis being is tilted with respect to the second direction for the first region and the second region. The c-axis intersects a third direction perpendicular to the first surface. | 2015-12-31 |
20150380496 | GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, LAMINATED GROUP III NITRIDE COMPOSITE SUBSTRATE, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate and a group III nitride film with a thickness of 50 nm or more and less than 10 μm that are bonded to each other. A ratio s | 2015-12-31 |
20150380497 | Group III-V Device with a Selectively Modified Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 2015-12-31 |
20150380498 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE PRODUCED THEREBY - A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming a first nitride-based semiconductor layer of Al | 2015-12-31 |
20150380499 | P-TYPE TRANSPARENT OXIDE SEMICONDUCTOR, TRANSISTOR HAVING THE SAME, AND MANUFACTURE METHOD OF THE SAME - A p-type transparent oxide semiconductor includes tin oxide compounds represented by below chemical formula 1: | 2015-12-31 |
20150380500 | Ga2O3-BASED SINGLE CRYSTAL SUBSTRATE | 2015-12-31 |
20150380501 | -Ga2O3-BASED SINGLE CRYSTAL SUBSTRATE | 2015-12-31 |
20150380502 | METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET - Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs. | 2015-12-31 |
20150380503 | SEMICONDUCTOR DEVICE AND METHOD FOR MANURACTURING THE SAME - A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region. | 2015-12-31 |
20150380504 | DEVICE AND METHOD FOR MANUFACTURING SAME - One device includes a substrate which contains a well region of one conductivity type, an element isolation insulating film which is arranged within the well region, an island-shaped active region which is surrounded by the element isolation insulating film, two first gate structures which are arranged on the island-shaped active region, and each of which is configured by sequentially laminating a lower gate insulating film, a gate insulating film having a high dielectric constant, a first gate electrode film containing a metal material, and a second gate electrode film, and a second gate structure which includes a second gate electrode film that is in contact with and covers cover a part of the element isolation insulating film. The two first gate structures and the second gate structure are successively arranged in the order of one first gate structure, the second gate structure and the other first gate structure. | 2015-12-31 |
20150380505 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts. | 2015-12-31 |
20150380506 | REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. | 2015-12-31 |
20150380507 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line. | 2015-12-31 |
20150380508 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole. | 2015-12-31 |
20150380509 | IMPROVED FORMATION OF SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES - Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions. | 2015-12-31 |