Patent application number | Description | Published |
20150161004 | READ BUFFER ARCHITECTURE SUPPORTING INTEGRATED XOR-RECONSTRUCTED AND READ-RETRY FOR NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) SYSTEMS - According to one embodiment, a system includes a read butter memory configured to store data to support integrated XOR reconstructed data and read-retry data and logic configured to receive data units and read command parameters used to read the data units from a non-volatile random access memory (NVRAM) device, determine which read buffers from the read buffer memory to store the data units, determine an error status for each of the data units, wherein the error status indicates whether each data unit includes errored data or error-free data, store each error-free data unit and the read command parameters to a corresponding read buffer, reject each errored data unit without affecting a corresponding read buffer, and retry to read only errored data units from the NVRAM device until each of the data units is stored in the read buffer memory. | 06-11-2015 |
20150161035 | RETIREMENT OF PHYSICAL MEMORY BASED ON DWELL TIME - In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of regions of physical memory. The data storage system further includes a controller that controls read and write access to the memory array and retires selected ones of the plurality of regions of physical memory from use. The controller determines whether or to not to retire a particular region among the plurality of regions of physical memory from use based on a dwell time of data stored in the particular region. | 06-11-2015 |
20150161036 | PROGRAMMING NON-VOLATILE MEMORY USING A RELAXED DWELL TIME - In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including multiple pages. The data storage system further includes a controller that maintains a data structure identifying blocks of physical memory in the memory array that currently do not store valid data. The controller, responsive to receipt of a write input/output operation (IOP) specifying an address and write data, selects a particular block from among the blocks identified in the data structure prior to a dwell time threshold for the particular block being satisfied, programs a page within the selected block with the write data, and associates the address with the selected block. | 06-11-2015 |
20150178190 | DETECTING HOT SPOTS THROUGH FLASH MEMORY MANAGEMENT TABLE SNAPSHOTS - Decisions about how to correlate logical address to physical addresses in a flash memory (or other non-volatile random access memory) is based at least in part upon how frequently a logical address is accessed over time. Accordingly, software tracks accesses, by logical address, to the stored data using a flash memory metadata structure, and calculates a frequency-of-access value for each logical address of the set of logical addresses corresponding to the relative frequency with which the corresponding logical address is accessed, based, at least in part, on the flash memory metadata structure. For example, logical addresses with low frequency may be grouped together so that the frequency of erasure operations (which are often done on a block by block basis) will tend to be reduced. | 06-25-2015 |
20160092352 | REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES - In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments. | 03-31-2016 |
20160110124 | DETECTING ERROR COUNT DEVIATIONS FOR NON-VOLATILE MEMORY BLOCKS FOR ADVANCED NON-VOLATILE MEMORY BLOCK MANAGEMENT - Non-volatile memory block management. A method according to one embodiment includes determining a block health of at least some non-volatile memory blocks of a plurality of non-volatile memory blocks that are configured to store data. An error count margin threshold is calculated for each of the at least some non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the non-volatile memory blocks has been exceeded. | 04-21-2016 |
20160110248 | STORAGE ARRAY MANAGEMENT EMPLOYING A MERGED BACKGROUND MANAGEMENT PROCESS - In at least one embodiment, a controller of a non-volatile memory array iteratively performs a merged background management process independently of any host system's demand requests targeting the memory array. During an iteration of the merged background management process, the controller performs a read sweep by reading data from each of a plurality of page groups within the memory array and recording page group error statistics regarding errors detected by the reading for each page group, where each page group is formed of a respective set of one or more physical pages of storage in the memory array. During the iteration of the merged background management process, the controller employs the page group error statistics recorded during the read sweep in another background management function. | 04-21-2016 |
20160141048 | BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY - In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS | 05-19-2016 |