Patent application number | Description | Published |
20090064978 | Crossbow - A crossbow includes a trigger mechanism having a trigger housing for receiving a bowstring of a crossbow and a bowstring catch mounted with respect to the housing and adapted to releasably engage a crossbow bowstring brought within the trigger housing. The crossbow further includes a trigger adapted to releasably engage the bowstring catch, the trigger being further adapted to be selectively actuated by a user so as to cause the trigger to release the bowstring catch, thereby causing the bowstring catch to release a crossbow bowstring. Optionally, the crossbow may include a ball disposed between the bowstring catch and the trigger, the ball being adapted to bear and react to forces arising between the bowstring catch and the trigger during at least one of the trigger so engaging the bowstring catch and the trigger so releasing the bowstring catch. | 03-12-2009 |
20110197869 | BOW HAVING IMPROVED LIMBS, TRIGGER RELEASES, SAFETY MECHANISMS AND/OR DRY FIRE MECHANISMS - The present disclosure provides improved bows (e.g., crossbows and/or vertical bows). More particularly, the present disclosure provides advantageous bows having improved limbs, trigger releases, safety mechanisms and/or dry fire mechanisms. In exemplary embodiments, the present disclosure provides for systems and methods for fabricating bows (e.g., crossbows/vertical bows) having improved limbs (e.g., crossbow limbs), trigger releases, safety mechanisms and/or dry fire mechanisms, and wherein the bows provide increased arrow speed and/or more efficient release of stored energy. | 08-18-2011 |
Patent application number | Description | Published |
20100195777 | METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS - Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal. | 08-05-2010 |
20100219996 | DC OFFSET DETECTION AND CORRECTION FOR USER TRAFFIC - In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic. | 09-02-2010 |
Patent application number | Description | Published |
20080204171 | METHODS AND APPARATUS FOR PROGRAMMABLE ACTIVE INDUCTANCE - Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance. | 08-28-2008 |
20090115536 | PROGRAMMABLE LINEAR TRIMMING METHOD AND SYSTEM FOR PHASE LOCKED LOOP CIRCUIT CALIBRATION - The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process. | 05-07-2009 |
20100054386 | METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION - Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal. | 03-04-2010 |
20100220776 | METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES - Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock. | 09-02-2010 |
20120287983 | METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES - Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock. | 11-15-2012 |