Patent application number | Description | Published |
20100238047 | Method of Confirming that a Control Device Complies with a Predefined Protocol Standard - A control device, such as a digital ballast controller, is adapted to be coupled to an electronic ballast, such as a DALI ballast, via a communication link, and is operable to determine whether the ballast is operating within the specifications of a predefined protocol standard, e.g., the DALI standard. For example, the control device may measure the bit times of a digital message received from the ballast and to determine if the bit times fall within the limits set by the standard. The control device may also determine the minimum delay time required between two digital messages received by the ballast and determine if the minimum delay time falls within the limit set by the standard. The control device may adapt its normal operation (e.g., how digital messages are received and transmitted) or may provide feedback (e.g., by flashing a lamp) in response to determining that the ballast is operating outside of the specifications of the standard. | 09-23-2010 |
20110187286 | Switching Circuit Having Delay For Inrush Current Protection - A two-wire switching circuit can handle a large inrush current, but does not require a neutral connection or a heavy-duty mechanical switch or relay. The switching circuit comprises a mechanical air-gap switch, a first controllably conductive device (e.g., a bidirectional semiconductor switch), and a second controllably conductive device (e.g., a latching relay), which are all adapted to be coupled between an AC power source and an electrical load when the air-gap switch is in a first position. First and second delay circuits control the semiconductor switch and the latching relay to be conductive at different times after the air-gap switch is changed to the first position. Specifically, the semiconductor switch is rendered conductive before the latching relay is rendered conductive, such that the semiconductor switch conducts the large inrush current. The latching relay conducts current from the AC power source to the electrical load after the inrush current has subsided. | 08-04-2011 |
Patent application number | Description | Published |
20160085884 | SYSTEM AND METHOD FOR MODELING A LIGHTING CONTROL SYSTEM - A system and method for modeling a lighting control system for an enterprise is provided comprising an application (App) on a mobile device, or laptop, or personal computer, or other like device, that can communicate electronically with a webpage accessible by the internet or local area network or wide area network, wherein the webpage represents a program, and the program provides for the receiving, storing, and processing of lighting control system specified information on a space-by-space basis, and further wherein a unique part number for the space-based lighting control system can be generated for the particular space, such that delivery of individual, but substantially integrated space-based lighting control systems, can be delivered to the spaces for installation in the enterprise location. | 03-24-2016 |
20160086242 | SYSTEM AND METHOD FOR MODELING A LIGHTING CONTROL SYSTEM - A system and method for modeling a lighting control system for an enterprise is provided comprising an application (App) on a mobile device, or laptop, or personal computer, or other like device, that can communicate electronically with a webpage accessible by the internet or local area network or wide area network, wherein the webpage represents a program, and the program provides for the receiving, storing, and processing of lighting control system specified information on a space-by-space basis, and further wherein a unique part number for the space-based lighting control system can be generated for the particular space, such that delivery of individual, but substantially integrated space-based lighting control systems, can be delivered to the spaces for installation in the enterprise location. | 03-24-2016 |
Patent application number | Description | Published |
20140162176 | SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK - A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed. | 06-12-2014 |
20140264334 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 09-18-2014 |
20140268090 | CROSS TECHNOLOGY RETICLE (CTR) OR MULTI-LAYER RETICLE (MLR) CDU, REGISTRATION, AND OVERLAY TECHNIQUES - Methods for reducing reticle transmission differences and for optimizing layer placement for overlay in MTRs and CTRs are disclosed. Embodiments include providing a reticle having a prime area and a frame area surrounding the prime area; determining RT differences across the prime area; and providing RT adjustment structures on the reticle to decrease the RT differences. Other embodiments include grouping multiple layers of a semiconductor production flow, the layers for each group having an RT difference less than a predetermined value; and placing the layers on plural ordered reticles of a reticle set, each reticle having multiple image fields, by selecting, for each reticle, layers from a single group and optimizing placement of the layers for overlay. Other embodiments include selectively rotating image fields on a reticle having multiple image fields to improve overlay, or optimizing placement of DDLs on CTRs by placing each design orientation on a different reticle. | 09-18-2014 |
20140273310 | MONITORING PATTERN FOR DEVICES - Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer. | 09-18-2014 |
20140353843 | CIRCUIT STRUCTURES AND METHODS OF FABRICATION WITH ENHANCED CONTACT VIA ELECTRICAL CONNECTION - Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via. | 12-04-2014 |
20140370447 | SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK - A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed. | 12-18-2014 |
20150017803 | CUSTOMIZED ALLEVIATION OF STRESSES GENERATED BY THROUGH-SUBSTRATE VIA(S) - Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure. | 01-15-2015 |
20150028482 | DEVICE LAYOUT FOR REDUCING THROUGH-SILICON-VIA STRESS - Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix). | 01-29-2015 |
20150028500 | FORMING ALIGNMENT MARK AND RESULTING MARK - Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry. | 01-29-2015 |
20150192866 | EFFICIENT OPTICAL PROXIMITY CORRECTION REPAIR FLOW METHOD AND APPARATUS - A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process. | 07-09-2015 |
20150221565 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 08-06-2015 |
20150278426 | METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF - A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process. | 10-01-2015 |
20150287651 | OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION - A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer. | 10-08-2015 |
20150310157 | MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION - Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio. | 10-29-2015 |
20160079180 | OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION - A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer. | 03-17-2016 |