Patent application number | Description | Published |
20150261583 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC CLOCK AND VOLTAGE SCALING (DCVS) AWARE INTERPROCESSOR COMMUNICATION - Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic. | 09-17-2015 |
20150277536 | Apparatus, System and Method for Dynamic Power Management Across Heterogeneous Processors in a Shared Power Domain - Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency. | 10-01-2015 |
20150309552 | ENHANCEMENT IN LINUX ONDEMAND GOVERNOR FOR PERIODIC LOADS - An enhanced OnDemand Governor is disclosed that computes a steady-state frequency based on prior recommended CPU frequencies and applies a steady-state frequency when available. When not available, a turbo frequency or a computed lower frequency is applied. For increased loads, the steady-state frequency can be applied for one or more cycles until it becomes apparent that gradual frequency increases are not sufficient to meet a large CPU load, at which point the turbo frequency is applied and the history of CPU frequencies can be flushed. The enhanced OnDemand Governor can be turned on where periodic loads are detected while the traditional OnDemand Governor can be used in all other use cases. | 10-29-2015 |
20150323975 | SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER - The present disclosure relates to synchronization and parallel operation of two or more cores within a multi-core computing system so as to reduce an amount of time that all cores are operating during a processing period and thereby increase an amount of idle time per processing period. In this way deeper sleep and/or idle states for the cores and the system can be entered. | 11-12-2015 |
20160119874 | DETECTION OF SPURIOUS TCP CONTROL PACKETS - Systems and methods for managing communications on a communication device are disclosed. A method may include receiving a communication packet at the communication device via a network connection and determining, at the communication device, whether the communication packet is an unsolicited control packet. Dormancy of the network connection is triggered after a first time period if the communication packet is not an unsolicited control packet, and dormancy of the network connection is triggered after a second time period if the communication packet is an unsolicited control packet wherein the second time period is less than the first time period. | 04-28-2016 |
20160124778 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC CLOCK AND VOLTAGE SCALING (DCVS) AWARE INTERPROCESSOR COMMUNICATION - Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic. | 05-05-2016 |