Patent application number | Description | Published |
20090094570 | Configurable Asic-based Sensing Circuit - A sensing circuit based on an application-specific integrated circuit (ASIC) sensor which includes a sensor portion and a processor portion which are integrated on an ASIC. The sensor portion outputs raw output in response to a stimulus. The output of the sensor portion is processed by the processor portion. The sensor portion and the processor portion together form at least two blocks which are configurable together by interconnections in two or more ways to produce differentiated sensing products. | 04-09-2009 |
20090141931 | Digital Watermarking CMOS Sensor - The subject matter of this specification can be implemented in, among other things, an imaging system including an active pixel sensor imaging array configured to capture an image, said imaging array being in electronic communication with a watermark embedder. | 06-04-2009 |
20100026838 | OPTICAL PIXEL AND IMAGE SENSOR - A photosensitive pixel includes a photosensor and an externally loadable flag. The photosensor outputs a signal indicative of an intensity of incident light. The externally loadable flag indicates the pixel reset state, and is preferably stored in an in-pixel memory. Pixel reset logic resets the photosensor in accordance with the reset state and an externally applied reset signal. | 02-04-2010 |
20100194439 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal. | 08-05-2010 |
20100231263 | Logic Circuit and Method of Logic Circuit Design - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor. | 09-16-2010 |
20120005639 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor. | 01-05-2012 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |