Patent application number | Description | Published |
20140344598 | Enabling A Non-Core Domain To Control Memory Bandwidth - In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed. | 11-20-2014 |
20150095620 | ESTIMATING SCALABILITY OF A WORKLOAD - In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed. | 04-02-2015 |
20150095666 | CONSTRAINING PROCESSOR OPERATION BASED ON POWER ENVELOPE INFORMATION - In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed. | 04-02-2015 |
20150241949 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS - One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor. | 08-27-2015 |
20150241954 | Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor - A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state. | 08-27-2015 |
20150269108 | METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP - Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information. | 09-24-2015 |
Patent application number | Description | Published |
20120095607 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems - According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information. | 04-19-2012 |
20120144217 | Dynamically Modifying A Power/Performance Tradeoff Based On Processor Utilization - In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed. | 06-07-2012 |
20120173907 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING - Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption. | 07-05-2012 |
20120185706 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CONTROL OF ENERGY CONSUMPTION IN POWER DOMAINS - An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit. | 07-19-2012 |
20120185709 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING THREAD CONSOLIDATION - An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment. | 07-19-2012 |
20120204042 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 08-09-2012 |
20120221873 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices - According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device. | 08-30-2012 |
20130061064 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 03-07-2013 |
20130080803 | Estimating Temperature Of A Processor Core In A Low Power State - In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed. | 03-28-2013 |
20130111120 | Enabling A Non-Core Domain To Control Memory Bandwidth | 05-02-2013 |
20130111121 | Dynamically Controlling Cache Size To Maximize Energy Efficiency | 05-02-2013 |
20130111226 | Controlling A Turbo Mode Frequency Of A Processor | 05-02-2013 |
20130111236 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor | 05-02-2013 |
20130173941 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 07-04-2013 |
20130173946 | CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS - Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed. | 07-04-2013 |
20130179704 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 07-11-2013 |
20130179705 | Controlling A Turbo Mode Frequency Of A Processor - In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. | 07-11-2013 |
20130179706 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 07-11-2013 |
20130179709 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 07-11-2013 |
20130339777 | MICROPROCESSOR-ASSISTED AUTO-CALIBRATION OF VOLTAGE REGULATORS - Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system. | 12-19-2013 |
20140006761 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS | 01-02-2014 |
20140068293 | Performing Cross-Domain Thermal Control In A Processor - In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed. | 03-06-2014 |
20140089688 | Sharing Power Between Domains In A Processor Package - In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed. | 03-27-2014 |
20140095904 | Apparatus and Method For Determining the Number of Execution Cores To Keep Active In A Processor - A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope. | 04-03-2014 |
20140115351 | DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 04-24-2014 |
20140157021 | ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed. | 06-05-2014 |
20140281612 | MEASUREMENT OF PERFORMANCE SCALABILITY IN A MICROPROCESSOR - A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability. | 09-18-2014 |
20150095673 | Controlling A Turbo Mode Frequency Of A Processor - In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. | 04-02-2015 |
Patent application number | Description | Published |
20090170247 | MAGNETIC PARTICLES FOR LOW TEMPERATURE CURE OF UNDERFILL - Electronic devices and methods for fabricating electronic devices are described. One embodiment includes a method comprising providing a first body and a second body, and electrically coupling the first body to the second body using a plurality of solder bumps, wherein a gap remains between the first body and the second body. The method also includes placing an underfill material into the gap between the first body and the second body, the underfill material comprising magnetic particles in a polymer composition. The method also includes curing the underfill material in the gap by applying a magnetic field powered by alternating current, to induce heat in the magnetic particles, wherein the heat in the magnetic particles heats the polymer composition, and the magnetic field is applied for a sufficient time to cure the polymer composition. Other embodiments are described and claimed. | 07-02-2009 |
20100078806 | MICROELECTRONIC PACKAGE WITH WEAR RESISTANT COATING - A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die. | 04-01-2010 |
20120074597 | FLEXIBLE UNDERFILL COMPOSITIONS FOR ENHANCED RELIABILITY - Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed. | 03-29-2012 |
20130263446 | FLUXING-ENCAPSULANT MATERIAL FOR MICROELECTRONIC PACKAGES ASSEMBLED VIA THERMAL COMPRESSION BONDING PROCESS - A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250° C.-300° C. at a ramp rate of 50° C./second-100° C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5. | 10-10-2013 |
20140061902 | TECHNIQUES AND CONFIGURATIONS FOR SURFACE TREATMENT OF AN INTEGRATED CIRCUIT SUBSTRATE - Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed. | 03-06-2014 |
20140175634 | METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein. | 06-26-2014 |
20140177149 | REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed. | 06-26-2014 |
20140264827 | METHODS OF FORMING WAFER LEVEL UNDERFILL MATERIALS AND STRUCTURES FORMED THEREBY - Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die. | 09-18-2014 |
20140264957 | ROBUST INK FORMULATIONS FOR DURABLE MARKINGS ON MICROELECTRONIC PACKAGES AND ITS EXTENDIBILITY AS A BARRIER MATERIAL FOR THERMAL AND SEALANT MATERIALS - Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. | 09-18-2014 |
20140332966 | EPOXY-AMINE UNDERFILL MATERIALS FOR SEMICONDUCTOR PACKAGES - Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality of conductive contacts couples the surface of the semiconductor die to the surface of the semiconductor package substrate. An epoxy-amine underfill material is disposed between the surface of the semiconductor die and the surface of the semiconductor package substrate and surrounds the plurality of conductive contacts. The epoxy-amine underfill has high adhesion and is based on a low volatility multi-functional amine species. | 11-13-2014 |
20150179478 | NARROW-GAP FLIP CHIP UNDERFILL COMPOSITION - An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles. | 06-25-2015 |
20150284503 | FLEXIBLE UNDERFILL COMPOSITIONS FOR ENHANCED RELIABILITY - Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed. | 10-08-2015 |
Patent application number | Description | Published |
20120182881 | Routing Protocols for Power Line Communications (PLC) - Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method may include transmitting a one-hop broadcast request message to a plurality of PLC devices in a mesh network and receiving a response from each of the devices. The method may also include selecting one of the devices as a bootstrapping agent, sending a join request to a bootstrapping server through the bootstrapping agent, and, in response to successfully joining the network, setting the bootstrapping agent as a next hop toward a bootstrapping server. In another embodiment, a method may include maintaining a routing table for a plurality of PLC devices in a mesh network, receiving a join request from a PLC device, accepting the request, and updating the table to add a record corresponding to the PLC device; the record setting the bootstrapping agent as a penultimate hop toward the PLC device. | 07-19-2012 |
20130094459 | Beacon Slot Allocation in Prime - Systems and methods for efficiently allocating beacon slot among multiple nodes on multiple levels within a power line communication network are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include performing, by a communications device, assigning beacon transmission times to nodes within the communication device's network. The assigned beacon transmission times comprise a beacon slot and frame pattern. The beacon slot and frame pattern ensure that each node does not transmit a beacon in a beacon slot that is adjacent to a beacon slot assigned to a parent or child node. A beacon transmission slot is reserved for a base node in every frame. The frames may be organized into thirty-two-frame superframes, wherein each frame comprises a base node beacon slot and four switch node beacon slots. | 04-18-2013 |
20130104117 | Data Concentrator Initiated Multicast Firmware Upgrade - Systems and methods for implementing data concentrated initiated multicast firmware upgrade in power line communications (PLC) are described. In an illustrative embodiment, a method performed by a PLC device may include forming a group of PLC devices to receive a transmission of a data set, the group being organized according to a hierarchical structure, transmitting the data set to the group of PLC devices, determining whether a PLC device in the lowest level of the hierarchical structure is missing one or more portions of the data set, and retransmitting at least the missing portions of the data set until the lowest level of PLC devices each have the full data set. | 04-25-2013 |
20130194975 | Switch Table Update using Demotion Command in PRIME - Embodiments of methods and systems for switch table update using demotion command in PRIME are presented. In one embodiment, the method is performed by a power line communication (PLC) device. For example, the PLC device may be a data concentrator. In such an embodiment, the method may include receiving a request for registration from a node in a PLC network. The method may also include determining whether the node was previously included in the network according to an alternate network topology configuration. Additionally, the method may include issuing a notification to a group of switch nodes in the network instructing the switch nodes to update respective switch tables in response to a determination that the node was previously included in the network according to an alternate network topology configuration. | 08-01-2013 |
20150163134 | ROUTING PROTOCOLS FOR POWER LINE COMMUNICATIONS (PLC) - Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method may include transmitting a one-hop broadcast request message to a plurality of PLC devices in a mesh network and receiving a response from each of the devices. The method may also include selecting one of the devices as a bootstrapping agent, sending a join request to a bootstrapping server through the bootstrapping agent, and, in response to successfully joining the network, setting the bootstrapping agent as a next hop toward a bootstrapping server. In another embodiment, a method may include maintaining a routing table for a plurality of PLC devices in a mesh network, receiving a join request from a PLC device, accepting the request, and updating the table to add a record corresponding to the PLC device; the record setting the bootstrapping agent as a penultimate hop toward the PLC device. | 06-11-2015 |