Patent application number | Description | Published |
20080218916 | SYSTEM AND METHOD FOR COMPONENT FAILURE PROTECTION - A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold. | 09-11-2008 |
20080263255 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20080263391 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20080301345 | MULTI-CHARACTER ADAPTER CARD - One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data. | 12-04-2008 |
20080301529 | APPARATUS AND METHOD FOR DISTINGUISHING SINGLE BIT ERRORS IN MEMORY MODULES - An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise. | 12-04-2008 |
20080301530 | APPARATUS AND METHOD FOR DISTINGUISHING TEMPORARY AND PERMANENT ERRORS IN MEMORY MODULES - An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator. | 12-04-2008 |
20080313369 | MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS - Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes. | 12-18-2008 |
20100161902 | METHOD, SYSTEM, AND PROGRAM FOR AN ADAPTOR TO READ AND WRITE TO SYSTEM MEMORY - Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device. | 06-24-2010 |
20100268986 | MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS - Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes. | 10-21-2010 |
20100274965 | REDUNDANT SOLID STATE DISK SYSTEM VIA INTERCONNECT CARDS - A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card. | 10-28-2010 |
20100332749 | WEAR LEVELING OF SOLID STATE DISKS DISTRIBUTED IN A PLURALITY OF REDUNDANT ARRAY OF INDEPENDENT DISK RANKS - A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present. | 12-30-2010 |
20110066882 | WEAR LEVELING OF SOLID STATE DISKS BASED ON USAGE INFORMATION OF DATA AND PARITY RECEIVED FROM A RAID CONTROLLER - A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure. The controller sends the data structures to the plurality of solid state disks, wherein the plurality of solid state disks allocate a storage area that is estimated to have a relatively greater life expectancy in comparison to other storage areas to store the block that includes the parity information. | 03-17-2011 |
20120159004 | REDUNDANT SOLID STATE DISK SYSTEM VIA INTERCONNECT CARDS - A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card. | 06-21-2012 |
20120260029 | WEAR LEVELING OF SOLID STATE DISKS BASED ON USAGE INFORMATION OF DATA AND PARITY RECEIVED FROM A RAID CONTROLLER - A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure. The controller sends the data structures to the plurality of solid state disks, wherein the plurality of solid state disks allocate a storage area that is estimated to have a relatively greater life expectancy in comparison to other storage areas to store the block that includes the parity information. | 10-11-2012 |