Patent application number | Description | Published |
20090167771 | Methods and apparatuses for Configuring and operating graphics processing units - A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed. | 07-02-2009 |
20120331189 | SYSTEM AND METHOD FOR PERFORMING ISOCHRONOUS DATA BUFFERING - A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device. | 12-27-2012 |
20130201998 | HEADER REPLICATION IN ACCELERATED TCP (TRANSPORT CONTROL PROTOCOL) STACK PROCESSING - In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers. | 08-08-2013 |
20140006763 | INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM | 01-02-2014 |
20140006767 | BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT | 01-02-2014 |
20140156896 | ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT - Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID. | 06-05-2014 |
20140180457 | ELECTRONIC DEVICE TO ALIGN AUDIO FLOW - An electronic device is provided that includes an input device to provide first audio signals, an output device to receive second audio signals, and logic to receive the first audio signals and to provide an audio input flow. The logic to further receive an audio output flow and to provide the second audio signals to the output device based on the audio output flow. The audio device to further align the audio input flow relative to the audio output flow. | 06-26-2014 |
20150085873 | HEADER REPLICATION IN ACCELERATED TCP (TRANSPORT CONTROL PROTOCOL) STACK PROCESSING - In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers. | 03-26-2015 |