Bernardo Gallegos, The Colony US
Bernardo Gallegos, The Colony, TX US
Patent application number | Description | Published |
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20090091024 | Stable Gold Bump Solder Connections - A metallic interconnect structure ( | 04-09-2009 |
20090302463 | SEMICONDUCTOR DEVICE HAVING SUBSTRATE WITH DIFFERENTIALLY PLATED COPPER AND SELECTIVE SOLDER - A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip | 12-10-2009 |
20100007015 | INTEGRATED CIRCUIT DEVICE WITH IMPROVED UNDERFILL COVERAGE - An integrated circuit device ( | 01-14-2010 |
20100007032 | FLIP CHIP SEMICONDUCTOR DEVICE HAVING WORKPIECE ADHESION PROMOTER LAYER FOR IMPROVED UNDERFILL ADHESION - A semiconductor device assembly ( | 01-14-2010 |
20100301493 | PACKAGED ELECTRONIC DEVICES HAVNG DIE ATTACH REGIONS WITH SELECTIVE THIN DIELECTRIC LAYER - A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 μm. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region. | 12-02-2010 |
20110108980 | STABLE GOLD BUMP SOLDER CONNECTIONS - A metallic interconnect structure ( | 05-12-2011 |
20110177686 | Stable Gold Bump Solder Connections - A metallic interconnect structure ( | 07-21-2011 |
20120252170 | PACKAGED ELECTRONIC DEVICES HAVING DIE ATTACH REGIONS WITH SELECTIVE THIN DIELECTRIC LAYER - A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region. | 10-04-2012 |