Biles
Brian Biles, Palo Alto, CA US
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20150127975 | Distributed virtual array data storage system and method - Embodiments of a distributed virtual array data storage system and method are disclosed. Storage nodes made up of relatively unsophisticated disks with associated processors are scalable to store very large amounts of data. The storage nodes communicate with servers directly over a network through, for example, an Ethernet connection. Control of the storage nodes and access to the storage nodes is handled entirely on the server side of the system by distributed virtual array (DVA) software running on the server side and employing a particular protocol over the standard network connection. In an embodiment, server-side virtual machine (VM) hosts host application VMs that are associated with vDisks. The DVA software distributes data for the vDisk over the storage nodes. In the case of failure of one or more of the storage nodes, the DVA software reconstructs the data, for example by reading redundant data from surviving storage nodes. | 05-07-2015 |
Brian Biles, San Carlos, CA US
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20150248402 | DATA STORAGE WITH A DISTRIBUTED VIRTUAL ARRAY - A data storage system includes a plurality of hosts, each of which includes at least one processor and communicates over a network with a plurality of storage nodes, at least one of which has at least one storage device, at least one storage controller, and at least one non-volatile memory. At least one process within a host issues data storage read/write requests. At least one of the hosts has a cache for caching data stored in at least one of the storage nodes. The host writes data corresponding to a write request to at least one remote non-volatile memory and carries out at least one storage processing function; data in the written-to node may then be made available for subsequent reading by a different one of the hosts. Examples of the storage processing function include compression, ECC computation, deduplicating, garbage collection, write logging, reconstruction, rebalancing, and scrubbing. | 09-03-2015 |
Brian E. Biles, Cedar Falls, IA US
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20080296115 | PTO Clutch With Lubrication Oil Shut-Off Valve And Integrated Relief Valve - A PTO clutch includes a lubrication shut-off valve that can slide between a first position blocking a port for lubrication oil to lubricate the PTO clutch, and a second position opening the port to lubricate the clutch. A relief valve is provided in the lubrication shut off valve, which opens in response to pressure spikes of activation oil and isolates the pressure spikes from the clutch piston. | 12-04-2008 |
Jonathan R. Biles, Vancouver, WA US
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20090114266 | High concentration, spectrum spitting, broad bandwidth, hologram photovoltaic solar collector - An improved method of converting solar energy into electricity by spreading the solar spectrum and concentrating it onto solar cells that are band-gaped in the corresponding wavelength range. The spectrally separated solar energy can be concentrated into a normal rainbow line or spread out to individual regions. A low cost solar energy conversion collector results because concentration reduces the quantity of photovoltaic cells needed and spectral splitting increases the energy collected by using multiple appropriately band-gaped solar cells in the different wavelengths. | 05-07-2009 |
Mark Rockwell Biles, Long Beach, CA US
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20140035296 | PRESSURE RELIEF LATCH MECHANISM - A latch mechanism having a mounting bracket, a body portion, and a flange portion. The latch mechanism is used for connecting a first and second members. The body portion has walls extending from a flange portion defining a chamber therein. A detent mechanism is positioned in the chamber. A bolt, movably carried on the latch mechanism, has connected front and rear bolt portions and may include a spring biased ball for engaging a recess on the rear bolt in the latched position. A receptacle is defined in the mounting bracket. A head portion of the rear bolt is positioned relative to the receptacle in the latched position. A portion of the rear bolt travels through the receptacle when unlatching and engages the detent mechanism in the latched position. A gasket provided between the head and the receptacle seals the head in the receptacle in the latched position. | 02-06-2014 |
Nathan P. Biles, Rochester, MN US
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20140115134 | RECOMMENDING A POLICY FOR AN IT ASSET - When a policy for an IT asset is created in a system manager that manages one or more IT assets, other IT assets that are related to the selected IT asset are determined based on at least one relation criteria related to system topology. The system administrator is prompted to apply the same policy to the related systems. When the system administrator accepts the recommendation to apply the same policy to the related systems, a system group is defined that includes the selected computer system and the related systems, and the system group and its corresponding policy are displayed to the system administrator. | 04-24-2014 |
20140115138 | RECOMMENDING A POLICY FOR AN IT ASSET - When a policy for an IT asset is created in a system manager that manages one or more IT assets, other IT assets that are related to the selected IT asset are determined based on at least one relation criteria related to system topology. The system administrator is prompted to apply the same policy to the related systems. When the system administrator accepts the recommendation to apply the same policy to the related systems, a system group is defined that includes the selected computer system and the related systems, and the system group and its corresponding policy are displayed to the system administrator. | 04-24-2014 |
Phillip Herzog Biles, Anaheim, CA US
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20080218330 | KIT AND SYSTEM FOR PROVIDING SECURITY ACCESS TO A DOOR USING POWER OVER ETHERNET WITH DATA PERSISTENCE AND FIRE ALARM CONTROL PANEL INTEGRATION - The present disclosure describes embodiments of a power-over-ethernet (“POE”) controller and an access control system comprising the same. In an embodiment, the access control system includes a POE controller configured to couple with a Fire Access Control Panel of an automated Fire Detection System. The access control system may further include one or more peripheral devices coupled with the POE controller and configured to be powered with electrical power received via an ethernet port of the POE controller. The peripheral devices may include an access device, a door strike, and a digital output device. Embodiments of a kit containing one or more partially or fully assembled components of the access control system are also described. | 09-11-2008 |
Stewart David Biles, Little Thurlow GB
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20100094613 | Device emulation support within a host data processing apparatus - A data processing apparatus | 04-15-2010 |
Stuart D. Biles, Green Gincer GB
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20100185821 | Local cache power control within a multiprocessor system - A data processing system including a plurality of processors | 07-22-2010 |
Stuart David Biles, Bury St. Edmunds GB
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20110307664 | Cache device for coupling to a memory device and a method of operation of such a cache device - A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions. | 12-15-2011 |
20130013889 | Memory management unit using stream identifiers - A memory management unit includes a translation buffer unit for storing memory management attribute entries that originate from a plurality of different memory management contexts. Context disambiguation circuitry responds to one or more characteristics of a received memory transaction to form a stream identifier and to determine which of the memory management context matches that memory transaction. In this way, memory management attribute entries stored within the translation lookaside buffer are formed under control of the appropriate matching context. When the translation buffer unit receives a further transaction, then a further stream identifier is formed therefrom and if this matches the stream identifier of stored memory management attribute entries then those memory management attribute entries may be used (if appropriate) for that further memory transaction. | 01-10-2013 |
20130103972 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus - A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus. | 04-25-2013 |
20130268930 | PERFORMANCE ISOLATION WITHIN DATA PROCESSING SYSTEMS SUPPORTING DISTRIBUTED MAINTENANCE OPERATIONS - A data processing system | 10-10-2013 |
20140156949 | FAULT HANDLING IN ADDRESS TRANSLATION TRANSACTIONS - A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations. | 06-05-2014 |
20140223229 | DATA PROCESSING APPARATUS AND METHOD FOR ANALYSING TRANSIENT FAULTS OCCURRING WITHIN STORAGE ELEMENTS OF THE DATA PROCESSING APPARATUS - A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus. | 08-07-2014 |
Stuart David Biles, Great Barton GB
Patent application number | Description | Published |
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20110093750 | Hardware resource management within a data processing system - A processor | 04-21-2011 |
20120079211 | Coherency control with writeback ordering - Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry. | 03-29-2012 |
Stuart David Biles, Cambridge GB
Patent application number | Description | Published |
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20130132737 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 05-23-2013 |
20140052921 | STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION - A data processing system includes a plurality of transaction masters ( | 02-20-2014 |
20140075581 | SECURE MECHANISM TO SWITCH BETWEEN DIFFERENT DOMAINS OF OPERATION IN A DATA PROCESSOR - A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction. | 03-13-2014 |
20150121036 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 04-30-2015 |
20150154045 | CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY - A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction. | 06-04-2015 |