Patent application number | Description | Published |
20100118424 | MEASUREMENT OF ROUND TRIP LATENCY IN WRITE AND READ PATHS - A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path. | 05-13-2010 |
20100118426 | WRITE CLOCK CONTROL SYSTEM FOR MEDIA PATTERN WRITE SYNCHRONIZATION - A write clock control system comprises a clock controller that determines a phase offset based on a phase difference between a write clock signal and a media pattern corresponding to a given timing synchronization field being read, and a phase interpolator that produces an updated write clock signal by updating the phase of the write clock signal in accordance with control signals that are based on the phase offset signal. | 05-13-2010 |
20100118427 | ELIMINATING SECTOR SYNCHRONIZATION FIELDS FOR BIT PATTERNED MEDIA - Clock synchronization techniques are described for data storage media, particularly for the tolerances of efficient use of bit patterned media (BPM) capacity. In particular, techniques are described where position of a read-write head and timing of a write and/or read clock is determined within a fraction of a dot of the underlying media. The techniques obviate the requirement for the fields conventionally written preceding a data sector to provide bit synchronization and symbol framing (sector synchronization fields). | 05-13-2010 |
20100118428 | INTERSPERSED PHASE-LOCKED LOOP FIELDS FOR DATA STORAGE MEDIA SYNCHRONIZATION - Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium, | 05-13-2010 |
20100118429 | REDUCED READ/WRITE TRANSITION OVERHEAD FOR STORAGE MEDIA - A technique is described for reducing overhead in a magnetic medium utilizing interspersed timing synchronization fields. In particular, a reader reads timing synchronization fields interspersed within data fields of the medium to obtain timing measurements. The reader is separated from a writer by a distance greater than a distance of the reader to traverse a select timing synchronization field. As such, the writer may perform a direct current (DC) write to the medium to suspend transitional write operations while the reader is reading the select timing synchronization field, and/or while the writer is over a unipolar field (e.g., a timing synchronization field). | 05-13-2010 |
20100118433 | WRITE PRECOMPENSATION SYSTEM - A write precompensation system comprises a write precompensation processor that calculates time shift information for the timing of individual write current transitions at a write head to coincide with a media pattern under the write head and a write precompensation controller that shifts the individual write current transitions in accordance with the time shift information. | 05-13-2010 |
20100202079 | WRITE SYNCHRONIZATION PHASE CALIBRATION FOR STORAGE MEDIA - A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media. | 08-12-2010 |
20110231596 | Multi-Tiered Metadata Scheme for a Data Storage Array - Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group. | 09-22-2011 |
20110252289 | ADJUSTING STORAGE DEVICE PARAMETERS BASED ON RELIABILITY SENSING - In general, this disclosure is directed to techniques for adjusting storage device parameters based on reliability sensing. According to one aspect, a method includes retrieving a codeword from a plurality of data blocks within a storage device, wherein each of the data blocks stores a respective portion of the codeword, generating a detected value for a bit within a first portion of the codeword based on information related to a reliability of a data block associated with the first portion, and performing error correction on a second portion of the codeword based on the detected value for the bit within the first portion of the codeword. According to another aspect, a method includes obtaining information related to a reliability of a data block within a storage device, and adjusting a data capacity for the storage device based on the information related to the reliability of the data block. | 10-13-2011 |
20110258380 | FAULT TOLERANT STORAGE CONSERVING MEMORY WRITES TO HOST WRITES - A data storage apparatus and associated method involving a memory with a plurality of storage elements defining an associated set of stored data, and memory control logic that, responsive to a request to store first data in a first storage element of the plurality of storage elements, computes without storing to any of the plurality of storage elements first redundancy data for the associated set of stored data inclusive of the first data. | 10-20-2011 |
20130124591 | RANDOM NUMBER GENERATION USING SWITCHING REGULATORS - Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data. | 05-16-2013 |
20130242428 | WRITE DELAY STABILIZATION - Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory. | 09-19-2013 |
20140016221 | PIN-EFFICIENT READER BIAS ENABLE CONTROL - Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal. | 01-16-2014 |
20140016222 | GAIN CONTROL FOR LATENCY TESTING - Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency. | 01-16-2014 |
20140029396 | HEAT ASSISTED MAGNETIC RECORDING DEVICE WITH PRE-HEATED WRITE ELEMENT - An apparatus includes a write element configured to apply a magnetic field to write data on a portion of a heat-assisted magnetic recording media in response to an energizing current. An energy source is configured to heat the portion of the media being magnetized by the write element. A preheat energizing current is applied to the write element during an interval before writing the data to the portion of the media. The preheat energizing current does not cause data to be written to the media and brings at least one of the write element and driver circuitry into thermal equilibrium prior to writing the data on the portion. | 01-30-2014 |
20140192435 | OFFSET CORRECTION VALUES ON A DATA STORAGE MEDIA - A memory system includes a storage medium having tracks arranged on the storage medium. The tracks include data track portions configured to store data. The tracks have a data track width and offset correction portions having a width that is greater than the data track width of the associated data track. Each offset correction portion stores one or both of positional offset correction values and timing offset correction values. The positional offset correction values are configured to correct for errors that occur in cross track positioning relative to the medium and the timing offset correction values are configured to correct for errors that occur in down track timing relative to the medium. | 07-10-2014 |
20150029613 | PIN-EFFICIENT READER BIAS ENABLE CONTROL - Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal. | 01-29-2015 |
20150074486 | TRANSFER UNIT MANAGEMENT - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved. | 03-12-2015 |
20150074487 | Memory Device with Variable Code Rate - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location. | 03-12-2015 |
20150089278 | VARIABLE DATA RECOVERY SCHEME HIERARCHY - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines. | 03-26-2015 |