Patent application number | Description | Published |
20100060501 | RAIL TO RAIL FLASH - An analogue to digital converter comprising: a first set comprising nodes defined by circuitry such that each node is at a respective voltage, the voltages on the nodes being in an orderly progression between the voltage of a first current source and the voltage of a first input node; a second set comprising nodes defined by circuitry such that each node is at a respective voltage, the voltages on the nodes being in an orderly progression between the voltage of a second current source and the voltage of a second input node; a plurality of comparators, each comparator being arranged to compare the voltage on a node in the first set with the voltage on a respective node in the second set; and a pair of switching devices arranged between the first current source and the first set of nodes, the first switching device of the pair connected so as to supply the current from the first current source to all said nodes in the first set, and the second switching device of the pair connected so as to supply the current from the first current source to a subset of said nodes in the first set which are closest in voltage to the voltage of the first input node; wherein control voltages of the first and second switching devices of the pair are set such that: (a) when the potential difference between the voltage at the first current source and the voltage at the first input node is greater than a predetermined potential difference the first switching device is in a first state and the current from the first current source flows through the first switching device; and (b) when the potential difference between the voltage at the first current source and the voltage at the first input node is less than the predetermined potential difference the first switching device is in a second state and the current from the first current source flows through the second switching device. | 03-11-2010 |
20110115662 | High Speed Low Voltage Flash - An analog-to-digital converter comprising: first and second sets of ordered nodes, each first node having a corresponding second node; for each first node, a respective first resistor and current source pair, the resistor of each pair being connected to a first converter input and the current source of each pair being coupled to the respective first node; for each second node, a respective second resistor and current source pair, the resistor of each pair being connected to a second converter input and the current source of each pair being coupled to the respective second node; and a plurality of first comparators, each first comparator having its first input connected to a first node and its second input connected to the corresponding second node; wherein each of the first resistor and current source pairs are configured so as to provide an orderly progression of voltages at the first nodes and each of the second resistor and current source pairs are configured so as to provide an orderly progression of voltages at the second nodes. | 05-19-2011 |
20110188555 | Architecture to Remove a Bimodal Dynamic DC Offset in Direct Conversion Receiver - Apparatus for controlling the generation of a DC signal at the output of a mixer, so that the DC signal is predictable, enabling a static offset compensation voltage to offset the DC signal. The apparatus comprises a mixer configured to receive a first and a second input signal, the mixer being such as to generate a first DC signal at the output of the mixer when the first and second input signal have the same frequency and a first relative phase, a phase detector for determining the relative phase of the first and second signals, and a phase modifier configured to modify the phase of the second signal relative to the first signal in dependence on the determination of the relative phase between the first and second signals such that the resulting DC signal at the output of the mixer is the first DC signal. | 08-04-2011 |
20110205786 | MEMORY DESIGN - An improved memory design is described which removes the need to read firmware from ROM into RAM on start-up. A SRAM memory element comprises an influencing element which sets the state of the memory cells within the memory element on start-up to defined values. These defined values are set at the design stage such that on start-up the volatile memory contains firmware or other data. Dependent upon the implementation of the influencing element, the values of stored in the memory cells may be fixed or may subsequently be overwritten during operation of the device. In an example, the memory cell comprises two cross-coupled inverters and the influencing element comprises at least one transistor arranged to connect the input to one of the inverters to ground or a power supply rail when voltage is applied to a controlling node of the transistor. | 08-25-2011 |
20110261866 | Loop-Through Circuit - An integrated circuit includes a digital interface for connection to a host controller; an antenna connection for connection to an antenna; a radio frequency transceiver for communicating data in accordance with one or more radio communication protocols, the radio frequency transceiver being configured to communicate radio frequency signals over the antenna connection in response to data exchanged over the digital interface; and radio loop-through circuitry for exchanging radio frequency signals with another integrated circuit, the radio loop-through circuitry being configured to provide radio frequency signals received at the antenna connection to an output connection of the integrated circuit. | 10-27-2011 |
20120295559 | Transmit/Receive Switch - A transceiver includes a first circuit having a connector for connection to an antenna and receiving circuitry, and a second circuit having transmitting circuitry. The first and second circuits are coupled using a balun, where the balun is arranged so that its unbalanced side is in the first circuit and its balanced side is in the second circuit. | 11-22-2012 |
20140210542 | POWER SPLITTER AND COMBINER - An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes. | 07-31-2014 |
20140211896 | Receiver and Methods for Calibration Thereof - There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards. | 07-31-2014 |
Patent application number | Description | Published |
20090157797 | DATA DISTRIBUTION SYSTEM - A data processing system for distributing a package of data from a source to a plurality of data processing machines arranged in a plurality of sites. The data is transmitted from the source to the plurality of data processing machines by means of a multicast. At each site, a local data processing machine is designated as a site master; the other local data processing machines report missing data portions to the site master; and the site master consolidates reports of missing data portions, and requests missing data portions from the source. The source then transmits the missing data portions to the plurality of data processing machines by means of a further multicast. If the site master receives a report of missing data that the site master has stored locally, the site master provides that missing data to the local machines by means of a site multicast. Reports of missing data received by the source from site masters at different sites are consolidated at the source before the source transmits the missing data to the plurality of sites by means of the further multicast. If a local machine is missing data from the multicast from the source, and is not aware that a site master has been designated, that local machine broadcasts to machines at that site information indicating that a site master is required. If a site master is already designated, that site master notifies that local machine that it is the site master; but if no site master is already designated, an election process is instigated to designate one of the machines at that site as site master. | 06-18-2009 |
20100131785 | POWER MANAGEMENT OF COMPUTERS - A method of controlling power consumption in a computer uses a power management program installed on the computer to detect the identities of processes running on the computer which maintain the computer in a high power state in the absence of input activity. The program compares the identity of the or each process running on the computer with a set of identities of previously identified processes and causes the computer to adopt a low power state if the detected identity of a process, or the detected identities of all the processes, running on the computer is/are in the set of previously identified processes. | 05-27-2010 |
20110054846 | Monitoring the Performance of a Computer - A computer implemented method of monitoring the performance of a computer comprises monitoring the computer to determine the values of a plurality of activity metrics of the monitored computer. A weighted combination of functions of the determined values is calculated as a measure of performance of the monitored computer. The weighted combination may be a weighted combination of net values of activity metrics. In one embodiment, the net values are calculated as the said values of the plurality of activity metrics of the monitored computer excluding contributions to the values from the one or more predetermined activities. In another embodiment, the net values are calculated as follows. The total values of the respective activity metrics of the monitored computer are determined. The contribution(s) to the said total values of the said one or more predetermined activities are determined The said contribution(s) are subtracted from the said total values to provide net values. The weighted combination may be used to control power consumption or otherwise take action in relation to the computer. | 03-03-2011 |
20110055609 | Controlling the Power State of a Computer - A computer implemented method of controlling a computer comprises periodically determining the total value of at least one activity metric of the controlled computer. The contribution(s) to the said total value(s) of one or more predetermined activities are determined. In one embodiment, the said contribution(s) are subtracted from the said total value(s) to provide respective net value(s). The net values are compared with respective preset values and the power state of the computer is controlled in dependence on the comparison. The one or more predetermined activities may be identified using a predetermined data set. In another embodiment the net value of at least one activity metric of the monitored computer is a net value excluding contributions to the said value(s) from the said one or more predetermined activities identified from the said data set. | 03-03-2011 |
20110093588 | Monitoring the performance of a Computer - A computer implemented method of monitoring the performance of a computer comprises determining the value of an activity metric of the monitored computer. The contribution(s) to the said value of one or more predetermined activities is/are determined In one embodiment, the said contribution(s) are subtracted from the said total value to provide a net value representing a measure of the performance of the computer. A predetermined data set may be used to identify the one or more predetermined activities. In another embodiment, the value of at least one activity metric of the monitored computer is determined excluding contributions to that value from the said one or more predetermined activities identified from the said data set to provide a net value representing a measure of the performance of the computer. The net value may be used to control the power consumption of the computer. | 04-21-2011 |
20110161707 | POWER MANAGEMENT OF COMPUTERS - A method of controlling power consumption in a computer by detecting whether or not there is any user activity, and also the identity of each process running on the computer. The identity of each process running on the computer is compared with a set of identities of previously identified processes, these having been deemed to be processes for which it is desirable that the computer maintains a high power state. The computer adopts a low power state if all the detected identities of processes are not in the set of high power state processes or no user activity is detected. The low power state is a state in which the computer is able to service requests. The computer freely adopts any available higher power state if user activity is detected or a detected process is in the set of high power state processes. The power state selected may depend on workload. | 06-30-2011 |
20110264931 | POWER CONTROL SYSTEM FOR WORKSTATIONS - A power control system for workstations ( | 10-27-2011 |