Patent application number | Description | Published |
20100308469 | METHOD AND APPARATUS OF FORMING A VIA - The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line. | 12-09-2010 |
20110070738 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 03-24-2011 |
20110207329 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well. | 08-25-2011 |
20110215477 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material. | 09-08-2011 |
20110275218 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 11-10-2011 |
20120215044 | METHOD FOR REFINING OIL - In one embodiment of the disclosure, a method for refining oil is provided. The method includes contacting an oil with hydrogen to perform a hydrodeoxygenation reaction using iron oxide as a catalyst, wherein the iron oxide comprises ferrous oxide (FeO), ferrum dioxide (FeO | 08-23-2012 |
20130150630 | METHOD FOR PREPARING PHENOLIC COMPOUNDS - In an embodiment of the disclosure, a method for preparing a phenolic compound is provided. The method includes providing a lignin depolymerization product, and hydrogenating the lignin depolymerization product under iron oxide and hydrogen gas to prepare a phenolic compound. The prepared phenolic compound is a crude phenolic composition including phenol, methylphenol, dimethylphenol or a combination thereof. | 06-13-2013 |
20130217208 | Method of Processing Wafers for Saving Material and Protecting Environment - A method of processing wafers for saving material and protecting environment is implemented to collect defective or incomplete wafers and perform cutting operation to create a plurality of separate dies. According to the requirement of a specification, the backs of the dies are grinded to allow each die to have a predetermined thickness. Thereafter, the grinded dies with completeness are sequentially placed onto a carrying means. With the method, the defective or incomplete wafers, which would be discarded in general wafer manufacturing, may be reclaimed to go through cutting, grinding, and selecting operations, so that the dies with completeness on the defective wafers can be picked out and processed again, so as to increase the yield, lower the manufacturing cost, reduce the amount of the wafer waste, increase the wafer utilization, and meet the demands of energy saving, carbon reduction, and environmental protection. | 08-22-2013 |
20130217310 | Wafer Processing Equipment - A wafer processing equipment, for use in operations of cutting and grinding wafers, comprises a driving device and at least one processing wheel. The driving device has a spindle extending therefrom, which can be fitted with a locking member. The processing wheel is coupled to the spindle of the driving device. The processing wheel defines a through hole at a center thereof, whereby the spindle of the driving device can be inserted through the through hole of the processing wheel to be fitted with the locking member, so that the processing wheel can be securely coupled to the spindle. The processing wheel can be selected to be a cutting wheel or a grinding wheel. As such, only one set of wafer processing equipment is adequate in performing both of cutting and grinding operations, thereby reducing the working space required for processing wafers and lowering the manufacturing cost. | 08-22-2013 |
20130221541 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit which includes an interconnect structure disposed at least partially in at least one opening of a dielectric layer. The integrated circuit further includes at least one air gap disposed between the dielectric layer and the interconnect structure. The integrated circuit further includes at least one first liner material disposed under the at least one air gap, the at least one first liner material extending along a bottom portion of a sidewall of the at least one opening of the dielectric layer. | 08-29-2013 |
20140261397 | METHOD OF SEPARATING CARBOHYDRATE - Disclosed is a method of separating carbohydrate, including: mixing formic acid with heteropoly acid, chloride or bromide of lithium, magnesium, calcium, zinc, or iron, or combinations thereof to form a mixing liquid. The method also includes dissolving a cellulose biomass by the mixing liquid to form a solution, mixing water and the solution to hydrolyze the cellulose biomass for forming a carbohydrate solution, and mixing an extractant and the carbohydrate solution to extract the formic acid out of the carbohydrate solution. The heteropoly acid, the chloride or bromide of lithium, magnesium, calcium, zinc, or iron, or combinations thereof in the carbohydrate solution is separated out of the carbohydrate solution by ion exclusion chromatography separation to obtain a carbohydrate. | 09-18-2014 |
20140264923 | INTERCONNECT STRUCTURE WITH KINKED PROFILE - Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape. | 09-18-2014 |
20150044865 | METHODS OF MAKING INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES - A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap. | 02-12-2015 |
Patent application number | Description | Published |
20100080059 | PAGE BUFFER USED IN A NAND FLASH MEMORY AND PROGRAMMING METHOD THEREOF - A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified. | 04-01-2010 |
20100304782 | METHOD AND SYSTEM FOR COORDINATING PROTOCOL STACK ENTITIES TO SHARE SINGLE RADIO RESOURCE - The invention discloses a method for coordinating protocol stack entities to share a single radio resource, executed by a processor of a mobile station, including the step of: after a first protocol stack entity for a first subscriber identity card enters a TALKING mode or enables a dial-up service, forcing a second protocol stack entity for a second subscriber identity card to release the radio resource or suspend utilization of the radio resource, and enabling the radio resource to be utilized to perform requisite operations or procedures of the TALKING mode or the dial-up service. | 12-02-2010 |
20110173661 | INTERACTIVE SYSTEM - An interactive system including a display device and a universal remoter is provided. An interactive application program is embedded into the display device, and the universal remoter is used for manipulating the display device. When the interactive application program is activated by a user through the universal remoter, the display device displays an interactive patterned interface so as to guide the user to set the universal remoter for learning the behaviors of a remoter corresponding to at least one peripheral equipment which is or is not linked with the display device. | 07-14-2011 |
20120008421 | DATA OUTPUTING METHOD OF MEMORY CIRCUIT AND MEMORY CIRCUIT AND LAYOUT THEREOF - A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6. | 01-12-2012 |
Patent application number | Description | Published |
20100154880 | DYE-SENSITIZED SOLAR CELL, ANODE THEREOF, AND METHOD OF MANUFACTURING THE SAME - A dye-sensitized solar cell (DSSC), anode thereof, and method of manufacturing the same are disclosed. The anode has a titanium dioxide layer mixed with a desired ratio of carbon black nanoparticles to increase the conductivity of the anode. Thereby, the conversion efficiency of the solar energy to electricity for the DSSC is effectively improved. | 06-24-2010 |
20140185167 | HIGH VOLTAGE OPEN-DRAIN ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current. | 07-03-2014 |
20150145557 | SERIAL TRANSMISSION DRIVING METHOD - The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends. | 05-28-2015 |
Patent application number | Description | Published |
20080311756 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 12-18-2008 |
20110195576 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 08-11-2011 |
20140299901 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light-emitting diode, comprising: a substrate, the substrate comprising an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer comprises a first portion and a second portion, and the second portion comprises an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion comprising a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge. | 10-09-2014 |
20150228856 | LIGHT-EMITTING DIODE HAVING A ROUGHENED SURFACE - A method of manufacturing a light-emitting diode comprises the steps of providing a substrate comprising an upper surface and a bottom surface opposite to the upper surface; providing a semiconductor stack layer on the upper surface, wherein the semiconductor stack layer comprises a first type semiconductor layer having a first surface, a light-emitting layer on the first type semiconductor layer for emitting light, and a second type semiconductor layer on the light-emitting layer; treating the first surface to form a second surface, wherein the second surface is flatter than the first surface; and providing a laser beam through the second surface to cut the substrate. | 08-13-2015 |
Patent application number | Description | Published |
20110109831 | LIQUID CRYSTAL DISPLAY WITH DISPLAY SCREEN EXTENDING OUT OF CASING - An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing. | 05-12-2011 |
20140111737 | LIQUID CRYSTAL DISPLAY WITH DISPLAY SCREEN EXTENDING OUT OF CASING - An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing. | 04-24-2014 |
20150185535 | LIQUID CRYSTAL DISPLAY WITH DISPLAY SCREEN EXTENDING OUT OF CASING - An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing. | 07-02-2015 |
20150185536 | LIQUID CRYSTAL DISPLAY WITH DISPLAY SCREEN EXTENDING OUT OF CASING - An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing. | 07-02-2015 |
Patent application number | Description | Published |
20110263127 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 10-27-2011 |
20130119533 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 05-16-2013 |
20130122689 | Methods for De-Bonding Carriers - A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape. | 05-16-2013 |
20130207306 | Methods for Molding Integrated Circuits - A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature. | 08-15-2013 |
20130337651 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 12-19-2013 |
20140300000 | Semiconductor Device and Method - A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect. | 10-09-2014 |
20140322866 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 10-30-2014 |
20150054170 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface of the via portion of each conductive feature. The barrier layer includes a dielectric layer. A first insulating material layer is disposed beneath a portion of the conductive line portion of each conductive feature. A second insulating material layer is disposed between the conductive features. A third insulating material layer is disposed beneath the first insulating material layer and the second insulating material layer. A lower portion of the via portion of each of the conductive features is formed within the third insulating material layer. The second insulating material layer has a lower dielectric constant than a dielectric constant of the first insulating material layer and a dielectric constant of the third insulating material layer. | 02-26-2015 |
Patent application number | Description | Published |
20110299241 | STYLUS RECEIVING MECHANISM AND PORTABLE COMPUTER THEREWITH - A stylus receiving mechanism includes a handle whereon a first opening and a second opening are formed on two ends. A chamber is formed inside the handle for receiving a stylus. The stylus receiving mechanism further includes a fastening part installed on an inner wall of the handle and disposed on a side of the chamber for pressing the stylus in a third direction perpendicular to a first direction for fastening the stylus inside the chamber after the stylus passes through the first opening in the first direction or passes through the second opening in the second direction opposite to the first direction to be received inside the chamber. | 12-08-2011 |
20120105391 | DRIVING CIRCUIT FOR A THREE-DIMENSIONAL LIQUID CRYSTAL LENS - A driving circuit for a three-dimensional liquid crystal lens provides a storage to store a high output value and a low output value of the channel output signal; the high and low output values are converted by a digital analog converter as the high output signal, the low output signal and the common signal which are driven by the driving circuit to produce the high driven output signal, the low driven output signal and the common output signal which are selectively output by the select logic circuit as the channel output signal according to the select signal; Thus, less operation amplifiers are needed, and the speed of response of the circuit can be enhanced. Power consumption can be reduced as well. | 05-03-2012 |
20120162136 | OPTICAL TOUCH PANEL AND METHOD OF DETECTING TOUCH POINT POSITIONS ON AN OPTICAL TOUCH PANEL - An optical touch panel and a method of detecting touch point positions on an optical touch panel are provided. The optical touch panel includes a processing unit, and at least three optical detectors divided into at least two detector groups. Each of the optical detectors is configured to output a signal indicating intensities of light detected thereby, and is associated with a detection range. The processing unit is configured to receive the signals from the optical detectors, to determine which of the optical detectors detect touch points within the respective detection range according to the signals received by the processing unit, and to obtain an optimum set of coordinates for at least one of the touch points with respect to an optimum detector group which is one of the detector groups formed by the optical detectors that detect the touch points. | 06-28-2012 |
20130010417 | KEYBOARD FIXING STRUCTURE FOR FIXING A KEYBOARD AND PORTABLE ELECTRONIC DEVICE THEREWITH - A keyboard fixing structure for fixing a keyboard in an opening of a housing is disclosed. The keyboard fixing structure includes an engaging portion, a first fixing portion, a first flexible connecting portion, a second fixing portion and a second flexible connecting portion. The engaging portion presses a first side of the keyboard in the opening. The first fixing portion is fixed on the housing, and the first flexible connecting portion is connected to the first fixing portion and the engaging portion. The second fixing portion is fixed on the housing, and the second flexible connecting portion is connected to the second fixing portion and the engaging portion. The first flexible connecting portion and the second flexible connecting portion cooperatively provide resilient force to the engaging portion in a first direction for driving the engaging portion to press the first side of the keyboard. | 01-10-2013 |
20130039222 | Ring-Based Network and Construction Thereof - A ring-based network and a construction method thereof, comprising a plurality of nodes and a plurality of links. In an initial status, each node compares each first link-up packet and fills a priority value in the first link-up packet with the higher priority value to form a second link-up packet. The priority value of each node and the highest priority value of each adjacent node recorded in each node are compared with each second link-up packet. When the priority value of the node and the highest priority values of adjacent nodes recorded in the node are smaller than the second link-up packet, the ring port of the node is situated at a forward status. According to the forward status or a blocked status of the ring port, these links form a plurality of forward links and a blocked link respectively. | 02-14-2013 |
20130043570 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate. | 02-21-2013 |
20130051617 | METHOD FOR SENSING MOTION AND DEVICE FOR IMPLEMENTING THE SAME - A method for sensing a motion of an object is to be implemented by a motion recognition device that includes an image acquiring unit and a processor. In the method, the image acquiring unit is configured to acquire a series of image frames by detecting intensity of light received thereby. The processor is configured to receive at least one of the image frames and to determine whether an object is detected in the at least one of the image frames. When an object is detected, the processor is further configured to receive the image frames from the image acquiring unit, and to determine a motion of the object with respect to a three-dimensional coordinate system according to the image frames thus received. | 02-28-2013 |
20130064069 | Recovery Method for Ring-Based Network - A recovery method for ring-based network comprises following steps: when an error occurs at first node, second and third nodes adjacent to the first node transmit a link-down packet respectively; after the first node is repaired, the first, second and third nodes transmit a link-up packet respectively, and each link-up packet includes a priority value of the first, second or third node; the priority values of the first, second and third nodes are compared with each link-up packet to enter the ring port of the first node, the second node or the third node into a forward status or a blocked status; and a forward link or a blocked link is formed among the ring ports of the first, second and third nodes. | 03-14-2013 |
20130169168 | METHOD FOR CONTROLLING GROUPED DEVICES - A method for controlling grouped devices is disclosed. The method includes receiving a group setting from a group switch on each of the electronic devices, the electronic devices being divided into a plurality of groups according to the group setting of the group switch; a control device emitting a wireless signal comprising group data and operation data to the electronic devices; each of the electronic devices determining whether the group data matches the group setting of the group switch; and if the group data matches the group setting of the group switch, the electronic devices with the group setting matching the group data performing an operation according to the operation data. | 07-04-2013 |
20140169757 | METHOD FOR QUICKLY DETERMINING A COMPRESSION FORMAT OF AN AUDIO OR VIDEO FILE AND RELATED PLAYBACK DEVICE THEREOF - A method for quickly determining a compression format of an audio-video file by a playback device, where the playback device includes a receiver, a detector, a register, and a processor, is disclosed. The method includes receiving an audio-video file by the receiver; using the detector to detect whether a tag portion exists behind a header of the audio-video file; using the processor to skip the tag portion to set a starting point for loading the audio-video file when the detector detects the tag portion; using the processor to filter out audio-video compression formats not compatible with the tag portion; and using the processor to load a first part to the buffer from the starting point, and determine a compression format of the audio-video file according to the first part. | 06-19-2014 |
20150058613 | METHOD OF BOOTING SYSTEM HAVING NON-VOLATILE MEMORY DEVICE WITH ERASE CHECKING AND CALIBRATION MECHANISM AND RELATED MEMORY DEVICE - A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device. | 02-26-2015 |
20160025640 | PORTABLE ELECTRONIC ASSAY DEVICE, PORTABLE ASSAY DEVICE AND KIT THEREOF - The present invention is related to a portable electronic assay device, a portable assay device and a kit thereof. The portable electronic assay device is used for determining a result of an assay performed using a test strip comprises a casing, an optical module, a light detector, and a processor. The casing comprises a transmissive part. The optical module emits a detecting light signal and display light signal. The detecting light signal is illuminated to the test strip and the display light signal is illuminated to the transmissive part. The light detector detects light from the test strip so as to obtain a detecting signal. The processor receives the detecting signal compared with a default value so as to obtain an assay result. The assay result is displayed on the transmissive part. Therefore, it provides simple structure of the assay device for displaying the assay result rapidly and correctly. | 01-28-2016 |
20160078961 | METHOD OF ERASING A NONVOLATILE MEMORY FOR PREVENTING OVER-SOFT-PROGRAM - A method of erasing a nonvolatile memory for preventing over-soft-program comprises performing an erase operation on at least one cell among a plurality of cells in the nonvolatile memory; applying a first soft program verify operation; applying a second soft program verify operation, wherein the second verify voltage is lower than the first verify voltage; determining whether the threshold voltage of the cell is lower than the first verify voltage or the second verify voltage; performing a soft program operation with a first soft program voltage when the threshold voltage of the cell is lower than the first verify voltage and higher than the second verify voltage; and performing the soft program operation with a second soft program voltage higher than the first soft program voltage when the threshold voltage of the cell is lower than both of the first verify voltage and the second verify voltage. | 03-17-2016 |