Patent application number | Description | Published |
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 04-09-2009 |
20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 04-05-2012 |
20130120329 | DISPLAY PANEL - A display panel includes a display area, a non-display area, a plurality of signal pads and a passive covering layer. The non-display area is adjacent to the display area. The signal pads are disposed within the non-display area. The passive covering layer is disposed on the display area and extends to cover at least a portion of the non-display area. The passive covering layer has a first thickness within the display area. The passive covering layer has a second thickness within the non-display area. The first thickness is greater than the second thickness. | 05-16-2013 |
20140197456 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 07-17-2014 |
20140197457 | FinFET Device and Method of Fabricating Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure. | 07-17-2014 |
20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 09-18-2014 |
20150132901 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 05-14-2015 |