Patent application number | Description | Published |
20100238631 | SECURING DEVICE AND THERMAL MODULE INCORPORATING THE SAME - A thermal module includes a fin assembly, a heat spreader, a heat pipe connected between the fin assembly and the heat spreader, and a securing plate. The securing plate has at least three resilient members secured on a bottom surface thereof. Each of the resilient members has a capability to deform resiliently along a direction perpendicular to the bottom surface of the securing plate to resiliently press the heat spreader to an electronic component. | 09-23-2010 |
20130014918 | HEAT DISSIPATION DEVICEAANM LIN; CHIH-HSUNAACI Tu-ChengAACO TWAAGP LIN; CHIH-HSUN Tu-Cheng TW - A heat dissipation device includes a plurality of fins connected to each other and two heat pipes extending through the fins. Each fin includes a plate, an upper flange extending from a top side of the plate, a lower flange extending from a bottom side of the plate and an inner flange extending from an inner periphery of a groove defined in the plate. The fins include first fins and second fins having lengths larger than that of the first fins. The two heat pipes include a wide heat pipe and a narrow heat pipe. The wide heat pipe extends through the grooves and contacts the inner flanges of the first fins and the second fins. The narrow heat pipe extends through the grooves and contacts the inner flanges of the second fins. | 01-17-2013 |
20130070418 | HEAT DISSIPATION MODULE - An electronic device includes printed circuit board having an electronic component and a heat dissipation module mounted the printed circuit board. The heat dissipation module includes a base with a heat absorbing plate and two elastic pieces extending from the heat absorbing plate. The heat absorbing plate thermally engages on the electronic component. The elastic pieces are fixed on the printed circuit board. The base is made of one of copper-nickel-silicon alloy, beryllium copper, a titanium copper or phosphor bronze. | 03-21-2013 |
Patent application number | Description | Published |
20090108787 | MOTOR DRIVING SYSTEM - The present invention relates to a motor driving system. The motor driving system includes a motor, a transmission member, a follower member, a position-detecting light emitter, a position-detecting light receiver, and a positioning-status sensing element. The positioning-status sensing element includes a plurality of notches or openings. The positioning-status sensing element is moved between the position-detecting light emitter and the position-detecting light receiver such that a light beam emitted from the position-detecting light emitter is successively penetrated through the notches or openings to be received by the position-detecting light receiver. According to the light-receiving status of the position-detecting light receiver, the speed of the motor is reduced. | 04-30-2009 |
20120250259 | COOLING SYSTEM FOR AN ELECTRONIC RACK - The present creation discloses a cooling system for an electronic rack, comprising: an electronic rack comprising at least one side wall; at least one electronic chassis comprising a top wall and at least one side wall and disposed inside the electronic rack for housing at least one modular electronics equipment comprising a plurality of electronic components and at least one stationary thermal interface arranged above the plurality of electronic components; a first detachable thermal interface arranged between the top wall of the at least one electronic chassis and the at least one modular electronic equipment; and at least one second detachable thermal interface arranged between the at least one side wall of the electronic rack and the at least one side wall of the at least one electronic chassis. | 10-04-2012 |
20140362531 | COOLING SYSTEM FOR AN ELECTRONIC RACK - The present invention discloses a cooling system for an electronic rack, comprising: an electronic rack comprising at least one side wall; at least one electronic chassis comprising a top wall and at least one side wall and disposed inside the electronic rack for housing at least one modular electronics equipment comprising a plurality of electronic components and at least one stationary thermal interface arranged above the plurality of electronic components; a first detachable thermal interface arranged between the top wall of the at least one electronic chassis and the at least one modular electronic equipment; and at least one second detachable thermal interface arranged between the at least one side wall of the electronic rack and the at least one side wall of the at least one electronic chassis. | 12-11-2014 |
Patent application number | Description | Published |
20080318170 | Method of making an optical disc - A method of making an optical disc is disclosed, in which, a flexible imprint mold is made from a fluid-state flexible silicone and has a reversal pattern of a first pattern on a surface. Also, a substrate is provided and has a second pattern on the surface with a semi-reflective layer deposited thereon. A dye or UV curable resin layer is formed on the semi-reflective layer. The flexible imprint mold is used to imprint the dye or UV curable resin layer and allowed to stay on it. After the dye or UV curable resin layer is cured, the flexible imprint mold is released from the cured dye or UV curable resin layer, such that the dye or UV curable resin layer has the first pattern. | 12-25-2008 |
20090017270 | DISC HAVING RELIEF PATTERN AND TRANSPRINT METHOD THEREOF - A disc having a relief pattern and a transprint method thereof are provided. The transprint method for transprinting the relief pattern on a substrate of the disc includes the following steps. First, a transprint template is provided. A first surface of the transprint template has a complementary pattern corresponding to the relief pattern. Next, a pattern layer is formed on the substrate. Then, the transprint template is placed on and covers the pattern layer until the first surface of the transprint template closely contacts a second surface of the pattern layer, so that the relief pattern is formed on the second surface. Afterward, the pattern layer is cured by irradiation. Later, the transprint template is removed for exposing the second surface with the relief pattern. | 01-15-2009 |
20090047462 | THREE-LEVEL RECORDING PHASE-CHANGE OPTICAL DISC - A three-level recording phase-change optical disc including a first recording layer, a second recording layer, a third recording layer, a reflective layer, and a dielectric layer is provided. The first recording layer, the second recording layer, and the third recording layer can form three recording regions with three different reflective indexes respectively so as to increase the recording density of the optical disc. | 02-19-2009 |
Patent application number | Description | Published |
20120181657 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 07-19-2012 |
20130020717 | INTEGRATED CIRCUIT HAVING A STRESSOR AND METHOD OF FORMING THE SAME - An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed. | 01-24-2013 |
20130043590 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING - The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature. | 02-21-2013 |
20130069162 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 03-21-2013 |
20130071995 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 03-21-2013 |
20130111419 | METHOD AND SYSTEM FOR MODIFYING DOPED REGION DESIGN LAYOUT DURING MASK PREPARATION TO TUNE DEVICE PERFORMANCE | 05-02-2013 |
20130200442 | SALICIDE FORMATION USING A CAP LAYER - A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack. | 08-08-2013 |
20130234217 | MOS Devices Having Non-Uniform Stressor Doping - A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations. | 09-12-2013 |
20130267069 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate. | 10-10-2013 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 10-31-2013 |
20130299987 | SEMICONDUCTOR STRUCTURE HAVING ETCH STOP LAYER - A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer. | 11-14-2013 |
20140038384 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 02-06-2014 |
20140053869 | Maranagoni Dry with Low Spin Speed for Charging Release - A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen. | 02-27-2014 |
20150041857 | SEMICONDUCTOR STRUCTURE HAVING STRESSOR - A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate. | 02-12-2015 |
Patent application number | Description | Published |
20120264302 | CHEMICAL MECHANICAL POLISHING PROCESS - A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step. | 10-18-2012 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 12-06-2012 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 01-10-2013 |
20130015524 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOFAANM Hsu; Chun-WeiAACI Taipei CityAACO TWAAGP Hsu; Chun-Wei Taipei City TWAANM Huang; Po-ChengAACI Chiayi CityAACO TWAAGP Huang; Po-Cheng Chiayi City TWAANM Tsai; Teng-ChunAACI Tainan CityAACO TWAAGP Tsai; Teng-Chun Tainan City TWAANM Hsu; Chia-LinAACI Tainan CityAACO TWAAGP Hsu; Chia-Lin Tainan City TWAANM Lin; Chih-HsunAACI Ping-Tung CountyAACO TWAAGP Lin; Chih-Hsun Ping-Tung County TWAANM Chen; Yen-MingAACI New Taipei CityAACO TWAAGP Chen; Yen-Ming New Taipei City TWAANM Chen; Chia-HsiAACI Kao-Hsiung CityAACO TWAAGP Chen; Chia-Hsi Kao-Hsiung City TWAANM Kung; Chang-HungAACI Kaohsiung CityAACO TWAAGP Kung; Chang-Hung Kaohsiung City TW - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 01-17-2013 |
20130045594 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer. | 02-21-2013 |
20130052825 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer. | 02-28-2013 |
20130075874 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure. | 03-28-2013 |
20130105912 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20140094017 | MANUFACTURING METHOD FOR A SHALLOW TRENCH ISOLATION - A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided. | 04-03-2014 |
20140106558 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 04-17-2014 |
20140273371 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank. | 09-18-2014 |