Patent application number | Description | Published |
20090323442 | SEMICONDUCTOR MEMORY DEVICE AND RESET CONTROL CIRCUIT OF THE SAME - The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal. | 12-31-2009 |
20100290298 | FUSE CIRCUIT AND REDUNDANCY CIRCUIT - A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to detect a voltage level of the output node based on a critical voltage adjusted according to a test mode signal, thereby generating a fuse condition signal. | 11-18-2010 |
20110002180 | CIRCUIT FOR GENERATING DATA STROBE SIGNAL AND METHOD - A circuit for generating a data strobe signal includes: a control signal generation unit configured to generate a strobe control signal defining an activation time period where a first data strobe signal and a second data strobe signal, which is an inverted signal of the first data strobe signal, are toggled; and a strobe signal output unit configured to output the first and second data strobe signals as a final strobe signal in the activation time period where the strobe control signal is activated. | 01-06-2011 |
20110204953 | LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit. | 08-25-2011 |
20110211413 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals. | 09-01-2011 |
20110242923 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CLOCK CONTROL CIRCUIT AND METHOD FOR OPERATING THE SAME - A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits. | 10-06-2011 |
20110267098 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM, AND METHOD FOR CONTROLLING TERMINATION OF THE SAME - A semiconductor device includes a plurality of first input units configured to receive a command, a second input unit configured to receive a termination command, a termination control unit configured to be enabled by the termination command and decode the command to control a termination operation, and a termination unit configured to be controlled by the termination control unit and terminate an interface pad. | 11-03-2011 |
20110292739 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal, a latching operation control unit configured to receive the data strobe signal, and generate a latching control signal after an interval between a write operation and a next write operation elapses, a data latching unit configured to latch output signals of the data alignment unit in response to the latching control signal, and a data synchronization output unit configured to synchronize output signals of the data latching unit in response to a data input strobe signal, and output the synchronized signals to a plurality of data lines. | 12-01-2011 |
20120025871 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a first buffer element configured to buffer a first mode signal inputted from the outside of the semiconductor device, and a second buffer element configured to buffer a second mode signal inputted from the outside by being enabled in response to an output signal of the first buffer element. | 02-02-2012 |
20120030497 | CONTROL CIRCUIT AND OPERATING METHOD THEREOF - A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal, and a clock supply block configured to sequentially supply the clock signals to the plurality of clock synchronization units. | 02-02-2012 |
20120106227 | INTEGRATED CIRCUIT - An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively. | 05-03-2012 |
20120110423 | COMMAND CONTROL CIRCUIT, INTEGRATED CIRCUIT HAVING THE SAME, AND COMMAND CONTROL METHOD - A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal. | 05-03-2012 |
20130083617 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a plurality of address input blocks configured to respectively receive a plurality of addresses that are related to burst ordering and a control circuit configured to selectively disable all or a part of the address input blocks in response to a burst length information during a write operation mode. | 04-04-2013 |
20130162342 | REFERENCE VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - A reference voltage generation circuit for a semiconductor integrated circuit includes a first reference voltage generation unit configured to generate a reference voltage in mode other than a self-refresh mode, and a second reference voltage generation unit configured to additionally drive an output terminal of the first reference voltage generation unit in an initial reference voltage setting period. | 06-27-2013 |
20130163354 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a command delay section configured to delay a command signal applied through a command input pad by a parity delay amount in synchronization with an operating clock and output a parity command signal in a parity operation mode, wherein the command delay section is further configured to be controlled in response to an error determination signal, a command decoder configured to decode the parity command signal and transfer a resultant signal to a plurality of memory banks, and an error determination unit configured to determine whether an error has occurred in the command signal and generate an error determination signal. | 06-27-2013 |
20130249608 | CONTROL SIGNAL GENERATOR FOR USE WITH A COMMAND DECODER - A semiconductor device includes a control signal generator configured to generate a control signal that is enabled in a predetermined duration in response to an enabling of a chip selection signal, a clock controller configured to transfer a clock as a decoding clock in a duration for enabling of the control signal and disable the decoding clock in a duration for disabling of the control signal, and a command decoder configured to generate an internal command by decoding the chip selection signal and one or more command signals in synchronization with the decoding clock. | 09-26-2013 |
20130335115 | INTEGRATED CIRCUIT AND METHOD FOR OPERATING THE SAME - A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock. | 12-19-2013 |
20130336075 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A memory device includes a decoder circuit configured to activate a setting signal and a write signal if a setting command is applied when a reference mode is set; a delay circuit configured to delay and to generate a delayed write signal; and a setting circuit configured to perform a setting operation in response to the delayed write signal and an input signal of a predetermined pad at the time of setting of the reference mode and to perform the setting operation in response to the setting signal when the reference mode is not set. | 12-19-2013 |
20130346836 | MEMORY DEVICE - A memory device includes a parity circuit configured to detect presence or absence of an error using a plurality of command signals and a plurality of address signals, a command shift circuit configured to shift the plurality of command signals by a preset delay value in synchronization with a control clock, a clock control circuit configured to deactivate the control clock when there is no valid command signal in command signals being shifted in the command shift circuit, and a decoder circuit configured to decode a plurality of command signals output from the command shift circuit. | 12-26-2013 |
20140002164 | DELAY CIRCUIT AND DELAY METHOD USING THE SAME | 01-02-2014 |
20140003174 | INTEGRATED CIRCUIT CHIP AND MEMORY DEVICE HAVING THE SAME | 01-02-2014 |
20140003178 | SEMICONDUCTOR MEMORY DEVICE | 01-02-2014 |
20140003183 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME | 01-02-2014 |
20140006886 | MEMORY AND METHOD FOR TESTING THE SAME | 01-02-2014 |
20140063994 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes first to N | 03-06-2014 |
20140063995 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory may comprise a first bank configured to include first to N | 03-06-2014 |
20140078845 | CELL ARRAY, MEMORY, AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines. | 03-20-2014 |
20140177376 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines. | 06-26-2014 |
20140317338 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF MEMORY DEVICE - A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information. | 10-23-2014 |
20140355368 | SEMICONDUCTOR DEVICE - An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation. | 12-04-2014 |
20140355371 | ADDRESS DETECTION CIRCUIT, MEMORY SYSTEM INCLUDING THE SAME - An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at least a threshold number of times in each period that the active command is activated M (1≦M≦N) number of times, based on the N number of addresses stored in the address storage unit. | 12-04-2014 |
20140359208 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a plurality of word lines each of which are connected to one or more memory cells, an address detection unit suitable for detecting a target address of a target word line among the plurality of word lines, wherein the target word line has an activation history satisfying a predetermined condition, and a control unit suitable for activating one or more word line among the plurality of word lines each time a refresh command is applied, and activating one or more adjacent word lines in response to a refresh command after detection of the target address, wherein the adjacent word line is adjacent to the target word line and identified by the target address. | 12-04-2014 |
20140368238 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code. | 12-18-2014 |
20150016201 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode. | 01-15-2015 |
20150043292 | MEMORY, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING MEMORY - A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines. | 02-12-2015 |
20150043293 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer. | 02-12-2015 |
20150049566 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section. | 02-19-2015 |
20150067201 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (DBI) calculator suitable for calculating DBI information for the training data input from the data storage through global transmission lines, generating a DBI flag signal based on the DBI information and outputting a DBI data, which is the training data inverted according to the DBI flag signal, in response to a DBI signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI data to a first channel in response to a training signal and the DBI signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI flag signal to a second channel. | 03-05-2015 |