Patent application number | Description | Published |
20080233709 | METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR - A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material. | 09-25-2008 |
20080254204 | DIELECTRIC APPARATUS AND ASSOCIATED METHODS - In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material. | 10-16-2008 |
20080290425 | Method for Fabricating a Semiconductor Element, and Semiconductor Element - In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms. | 11-27-2008 |
20090085110 | SEMICONDUCTOR DEVICE EMPLOYING PRECIPITATES FOR INCREASED CHANNEL STRESS - A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region. | 04-02-2009 |
20090114955 | Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure - A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin. | 05-07-2009 |
20090179308 | Method of Manufacturing a Semiconductor Device - According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner. | 07-16-2009 |
20100297818 | Semiconductor Devices Having pFET with SiGe Gate Electrode and Embedded SiGe Source/Drain Regions and Methods of Making the Same - In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask. | 11-25-2010 |
20150137309 | Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof - Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device. | 05-21-2015 |