Patent application number | Description | Published |
20110049583 | Recessed contact for multi-gate FET optimizing series resistance - A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h | 03-03-2011 |
20110063019 | DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR - A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt | 03-17-2011 |
20110065244 | ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE - A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region. | 03-17-2011 |
20110084315 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 04-14-2011 |
20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
20110115044 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-19-2011 |
20110298058 | FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET - FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds. | 12-08-2011 |
20120112310 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-10-2012 |
20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 11-22-2012 |
20130023093 | RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE - A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h | 01-24-2013 |