Dalton, CT
Andrew S. Dalton, New Milford, CT US
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20080270081 | NON-DESTRUCTIVE, BELOW-SURFACE DEFECT RENDERING USING IMAGE INTENSITY ANALYSIS - Non-destructive, below-surface defect rendering of an IC chip using image intensity analysis is disclosed. One method includes providing an IC chip delayered to a selected layer; determining a defect location below a surface of the selected layer using a first image of the IC chip obtained using an CPIT in a first mode; generating a second image of the IC chip with the CPIT in a second mode, the second image representing charged particle signal from the defect below the surface of the selected layer; and rendering the defect by comparing an image intensity of a reference portion of the second image not including the defect with the image intensity of a defective portion of the second image including the defect, wherein the reference portion and the defective portion are of structures expected to be substantially identical. | 10-30-2008 |
20090125829 | AUTOMATED YIELD SPLIT LOT (EWR) AND PROCESS CHANGE NOTIFICATION (PCN) ANALYSIS SYSTEM - Disclosed are an automated data analysis system and method. They system provides a standardized data analysis request form that allows a user to select an experiment (e.g., a wafer-level based yield split lot (EWR) analysis, a lot-level based process change notification (PCN) analysis, and lot-level based tool/mask qualification analysis) and a data analysis for a specific process module of interest. For each specific data analysis request, the system identifies critical test parameters, which are grouped depending on in-line test levels and photolithography levels. The system links the analysis request to test data sources and automatically monitors the test data sources, searching for the critical test parameters. When the critical test parameters become available, the system automatically performs the requested analysis, generates a report of the analysis and publishes the report with optional drill downs to more detailed results. The system further provides automatic e-mail notification of the published report. | 05-14-2009 |
James L. Dalton, East Hartford, CT US
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20150314302 | METHOD AND APPARATUS FOR RECYCLING LAMINATED WINDSHIELDS - A method for separating glass from a laminate of glass and binder, comprising the steps of breaking sheets of laminated glass into pieces; placing the pieces into a chamber with water; and then pressurizing the chamber, whereby the glass separates from binder; and removing the separated glass from the chamber. The separation can be enhanced by agitating and alternately pressurizing the chamber and freezing the water in the chamber. | 11-05-2015 |
Luke Dalton, Cromwell, CT US
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20150233000 | ELECTROCHEMICAL CELL - A separator plate and a frame member for an electrochemical cell are provided. The separator plate includes a plurality of protrusions extending therefrom to define a flow field. A pair of end features arranged along opposite sides of the flow field, each end feature extending substantially the length of the flow field. A periphery portion is provided having a first set of openings and a second set of openings. Wherein the plurality of protrusions and pair of end features extend from a plane defined by the periphery portion. The frame member includes features for facilitating assembly and reducing the risk of an over constrained condition. The frame member further having ports divided by a bridge member to support the frame member under operating pressures. | 08-20-2015 |
20150236360 | ELECTROCHEMICAL CELL WITH PROTECTOR GASKET ARRANGEMENT - An electrochemical cell is provided. The electrochemical cell includes a first frame, the frame having at least one first cleat feature arranged on one side, the at least one first cleat feature having a first height. A second frame is provided having at least one second cleat feature arranged on one side, the at least one second cleat feature having a second height. A membrane electrode assembly (MEA) is disposed between the first and second frame, the MEA having a first electrode disposed on a first side of a membrane and a second electrode disposed on a second side opposite the first electrode. A first gasket is disposed between the membrane and the first frame, the first gasket engaging the at least one first cleat feature. A second gasket is disposed between the membrane and the second frame, the second gasket engaging the at least one second cleat feature. | 08-20-2015 |
Luke T. Dalton, Middletown, CT US
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20090181281 | ELECTROCHEMICAL CELL BIPOLAR PLATE - A bipolar plate for an electrochemical cell is disclosed. The bipolar plate includes a unitary plate having first and second inlet ports, first and second outlet ports. The bipolar plate further includes a plurality of protrusions on each surface that forms a first plurality of flow channels, and second plurality flow channels. A first frame inlet header channel at one end of the first flow channels is in fluid communication with the first inlet port, and a first outlet header channel at the other end of the first flow channels is in fluid communication with the first outlet port. A second frame inlet header channel at one end of the second flow channels is in fluid communication with the second inlet port, and an outlet header channel at the other end of the second flow channels is in fluid communication with the second outlet port. Each of the header channels provides a fluid flow channel from one end of the respective header channel to the other end. | 07-16-2009 |
Thimothy Dalton, Ridgefield, CT US
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20080261128 | Methods and structures for protecting one area while processing another area on a chip - Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. | 10-23-2008 |
Thomas Joseph Dalton, Ridgefield, CT US
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20080308948 | WAFER-TO-WAFER ALIGNMENTS - Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10 | 12-18-2008 |
Timothy Dalton, Ridgefield, CT US
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20080254643 | STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER - An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO | 10-16-2008 |
20090065925 | DUAL-SIDED CHIP ATTACHED MODULES - An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate. | 03-12-2009 |
20090312046 | INTELLIGENT WIRELESS POWER CHARGING SYSTEM - A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging. | 12-17-2009 |
20100044759 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 02-25-2010 |
20100237467 | Interconnect Structures, Methods for Fabricating Interconnect Structures, and Design Structures for a Radiofrequency Integrated Circuit - Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature. | 09-23-2010 |
20120292741 | INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT - Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature. | 11-22-2012 |
20130179853 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 07-11-2013 |
Timothy J. Dalton, Ridgefiled, CT US
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20120183736 | PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL - In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order. | 07-19-2012 |
20120183742 | PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL - In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order. | 07-19-2012 |
William H. Dalton, Amston, CT US
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20120207626 | Thermally efficient multiple stage gear pump - A multiple stage pump for delivering fuel to an engine is disclosed which includes a pump housing, a boost stage operable at engine start to draw fuel into the pump housing at a boost stage pressure, a first pumping stage operable upon engine start for receiving fuel from the boost stage and delivering the fuel from the pump housing to a fuel metering unit, a second pumping stage operable upon engine start and during engine cruise operation for receiving fuel from the boost stage and delivering the fuel from the pump housing to said fuel metering unit, and a switching valve in fluid communication with the first and second pumping stages, and configured to control fuel flow through the first pumping stage in dependence on changes in boost stage conditions such as pressure or shaft speed. | 08-16-2012 |
20130000318 | ECOLOGY SYSTEM FOR DRAINING THE MANIFOLD OF A GAS TURBINE ENGINE - A fuel system including a fuel pump metering unit (FPMU) for delivering fuel to an engine manifold with an ecology valve for draining and storing fuel from the engine manifold. The ecology valve includes a housing having a piston dividing the housing into a first side in fluid communication with an output of the FPMU and a second side in fluid communication with the engine manifold. An assembly connected between the FPMU and engine manifold selectively creates a pressure differential across the first and second side of the housing when the FPMU delivers fuel to the engine manifold. In a run position, the piston moves to decrease a volume within the housing interior as a result of the pressure differential. In a drain position, the piston moves to increase the housing volume within the interior and thereby pull and store fuel from the engine manifold. | 01-03-2013 |