Patent application number | Description | Published |
20080272652 | Virtual power rail modulation within an integrated circuit - An integrated circuit | 11-06-2008 |
20080272809 | Integrated circuit power-on control and programmable comparator - An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output. | 11-06-2008 |
20090027099 | Output driver circuit having a clamped mode and an operating mode - An output driver circuit | 01-29-2009 |
20090051388 | Reducing leakage power in low power mode - Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal. | 02-26-2009 |
20090066164 | Power Controlling Integrated Circuit Cell - A power controlling integrated circuit cell is provided within an integrated circuit power grid to selectively couple an unswitched power supply input to a switched power supply output. The power controlling integrated circuit cell also includes a power control signal input and a power control signal output for supporting the distribution through the integrated circuit of the power control signal. The power controlling integrated circuit cell has a power switching circuit responsive to a power control input signal received at the power control signal input to selectively connect the switched power supply output to the unswitched power supply input, and a power control signal buffer circuit responsive to the switched power supply output to drive a power control output signal from the power control signal output. | 03-12-2009 |
20090115256 | Dynamically changing control of sequenced power gating - Power control circuitry for controlling connection of a voltage source to a switched power rail powering an associated circuit is provided. A plurality of switch blocks are connected in parallel between the switched power rail and the voltage source, each switch block being controlled by an enable signal provided by a switch controller. The switch controller performs a turn-on sequence providing a series of enable signal patterns to the switch blocks. The switch controller applies a time varying generation operation to at least one sequence stage of a predetermined turn-on sequence to produce a corresponding enable signal pattern for that sequence stage. When the turn-on sequence is later repeated, the enable signal pattern produced for at least one of the sequence stages differs from the enable signal pattern previously produced for that sequence stage. | 05-07-2009 |
20090115258 | Power control circuitry, circuitry for analysing a switched power rail, and method of controlling connection of a power source to a switched power rail - Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail. | 05-07-2009 |
20100269004 | State Retention using a variable retention voltage - A data processing apparatus is provided with state retention circuits 14 into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry | 10-21-2010 |
20110101998 | Operating parameter monitoring circuit and method - A monitoring circuit | 05-05-2011 |
20110102072 | Power management of an integrated circuit - An integrated circuit | 05-05-2011 |
20110181343 | Power controlling integrated circuit and retention switching circuit - A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device. | 07-28-2011 |
20120023382 | Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system - A data processing system and method for regulating a voltage supply to functional circuitry of the data processing system is provided. The functional circuitry is configured to operate from a voltage supply whose voltage level is variable, the functional circuitry having at least one error correction circuit configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom. An adaptive controller then generates the feedback control signal in dependence on the error rate history information such that the adaptive controller adjusts the feedback control signal over time having regard to the error rate history information in order to obtain a predetermined target non-zero error rate within the functional circuitry. Such an approach enables a significant reduction in power consumption of the data processing system to be achieved. | 01-26-2012 |
20120126879 | Apparatus and method for controlling power gating in an integrated circuit - A technique for controlling power gating in an integrated circuit is provided. The integrated circuit comprises a block of components to be power gated, and power gating circuitry for selectively isolating the block of components from the source voltage supply in order to achieve such power gating. Voltage regulator circuitry is used to provide a control voltage to the power gating circuitry when performing such power gating operations, the control voltage being settable to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller then issues a feedback control signal to the voltage regulator circuitry whose value is dependent on the received operating parameter data. The voltage regulator circuitry is then responsive to the feedback control signal to change the control voltage between the plurality of predetermined voltage levels, until the operating parameter data indicates that a desired leakage current has been obtained within the power gating circuitry. Such an approach enables a balance to be achieved between reducing leakage current and reducing wear out of the power gating circuitry. | 05-24-2012 |
20120286824 | Supplying a clock signal and a gated clock signal to synchronous elements - A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The clock gating circuitry unit receives a clock signal, a clock enable signal having either an enable value indicating the plurality of synchronous elements to are currently functional and are to be clocked, or a disable value indicating the plurality of synchronous elements are currently not required and are not to be clocked, and a power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down, or a functional mode value indicating the plurality of synchronous elements are to be powered. The clock gating unit has logic circuitry that is configured in response to the clock enable signal having the enable value and to the low power mode signal having the functional mode value to output the clock signal and in response to at least one of the clock enable signal having the disable value and the low power mode signal having the low power value to output the predetermined gated value. | 11-15-2012 |
20120286850 | Apparatus for storing a data value in a retention mode - Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate | 11-15-2012 |
20120286858 | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells - An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together. | 11-15-2012 |
20120303985 | State retention circuit adapted to allow its state integrity to be verified - A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or the scan input value changes, thus providing an external indication of the integrity of the state value held by the state retention component. | 11-29-2012 |
20120303986 | Verifying state integrity in state retention circuits - A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits. The plurality of parity information generation elements are arranged to provide one or more parity path(s), such that an output parity value generated at an output of the parity path will invert if one of said respective state values changes, providing an external indication of the integrity of the state values held by the state retention circuits. | 11-29-2012 |
20120326772 | Integrated circuit with power gating - An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry. | 12-27-2012 |
20130202008 | MONITORING CIRCUIT AND METHOD - A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature. | 08-08-2013 |
20140035661 | AN INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING LOAD ON THE OUTPUT FROM ON-CHIP VOLTAGE GENERATION CIRCUITRY - An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled. | 02-06-2014 |
20140340122 | CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON - An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage. | 11-20-2014 |
20150054563 | COMMUNICATION BETWEEN VOLTAGE DOMAINS - An integrated circuit | 02-26-2015 |