Patent application number | Description | Published |
20110037128 | METHOD AND STRUCTURE FOR IMPROVING UNIFORMITY OF PASSIVE DEVICES IN METAL GATE TECHNOLOGY - Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region. | 02-17-2011 |
20110049624 | MOSFET ON SILICON-ON-INSULATOR REDX WITH ASYMMETRIC SOURCE-DRAIN CONTACTS - A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region. | 03-03-2011 |
20110215300 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 09-08-2011 |
20110215405 | PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES - A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing. | 09-08-2011 |
20110227043 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 09-22-2011 |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 10-06-2011 |
20110248321 | Self-Aligned Contacts for Field Effect Transistor Devices - A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region. | 10-13-2011 |
20110248343 | Schottky FET With All Metal Gate - A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer. | 10-13-2011 |
20110248362 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 10-13-2011 |
20110298060 | INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface. | 12-08-2011 |
20110315961 | Ultrathin Spacer Formation for Carbon-Based FET - A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET. | 12-29-2011 |
20110316565 | SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR - A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule. | 12-29-2011 |
20120007054 | Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity. | 01-12-2012 |
20120007181 | Schottky FET Fabricated With Gate Last Process - A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region. | 01-12-2012 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 01-12-2012 |
20120037991 | Silicon on Insulator Field Effect Device - A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material. | 02-16-2012 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 02-16-2012 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 02-16-2012 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 02-23-2012 |
20120043620 | Multiple Threshold Voltages in Field Effect Transistor Devices - A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device. | 02-23-2012 |
20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-03-2012 |
20120119266 | Stressor in Planar Field Effect Transistor Device - A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region. | 05-17-2012 |
20120139062 | SELF-ALIGNED CONTACT COMBINED WITH A REPLACEMENT METAL GATE/HIGH-K GATE DIELECTRIC - A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer. | 06-07-2012 |
20120146001 | ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET - A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer. | 06-14-2012 |
20120181616 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 07-19-2012 |
20120187375 | Deposition On A Nanowire Using Atomic Layer Deposition - In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire. | 07-26-2012 |
20120193712 | FinFET STRUCTURE HAVING FULLY SILICIDED FIN - A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins. | 08-02-2012 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 11-08-2012 |
20120280322 | Self-Aligned Contacts for Field Effect Transistor Devices - A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w). | 11-08-2012 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 11-15-2012 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 11-15-2012 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 11-22-2012 |
20120292701 | Silicon on Insulator Field Effect Device - A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate, the first silicide material arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material. | 11-22-2012 |
20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 11-22-2012 |
20120299104 | SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS - A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate. | 11-29-2012 |
20120299118 | Multiple Threshold Voltages in Field Effect Transistor Devices - A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel. | 11-29-2012 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 11-29-2012 |
20120312452 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 12-13-2012 |
20120326125 | Deposition On A Nanowire Using Atomic Layer Deposition - A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape. | 12-27-2012 |
20120326236 | MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 12-27-2012 |
20120329193 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-27-2012 |
20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 07-04-2013 |
20130230978 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 09-05-2013 |
20130328016 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-12-2013 |
20140170844 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 06-19-2014 |