Patent application number | Description | Published |
20120104595 | NO FLOW UNDERFILL - A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element. | 05-03-2012 |
20120126389 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND VIAS CONNECTED TO THE CENTRAL CONTACTS - The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface. | 05-24-2012 |
20120280344 | Wafer Scale Packaging Platform For Transceivers - A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules. | 11-08-2012 |
20120314384 | LOW-STRESS TSV DESIGN USING CONDUCTIVE PARTICLES - A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via. | 12-13-2012 |
20130001757 | FLIP-CHIP QFN STRUCTURE USING ETCHED LEAD FRAME - A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess. | 01-03-2013 |
20130037925 | AREA ARRAY QFN - A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame. | 02-14-2013 |
20130049179 | LOW COST HYBRID HIGH DENSITY PACKAGE - A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly. | 02-28-2013 |
20130063918 | LOW CTE INTERPOSER - An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”). | 03-14-2013 |
20130101250 | Molded Glass Lid For Wafer Level Packaging Of Opto-Electronic Assemblies - An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer. | 04-25-2013 |
20130182996 | Releasable Fiber Connector For Opto-Electronic Assemblies - An apparatus for providing releasable attachment between a fiber connector and an opto-electronic assembly, the opto-electronic assembly utilizing an interposer substrate to support a plurality of opto-electronic components that generates optical output signals and receives optical input signals. An enclosure is used to cover the interposer substrate and includes a transparent region through which the optical output and input signals pass unimpeded. A magnetic connector component is attached to the lid and positioned to surround the transparent region, with a fiber connector for supporting one or more optical fibers magnetically attached to the connector component by virtue of a metallic component contained in the fiber connector. This arrangement provides releasable attachment of the fiber connector to the enclosure in a manner where the optical output and input signals align with the optical fibers in the connector. | 07-18-2013 |
20130183008 | Self-Aligning Connectorized Fiber Array Assembly - An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion. | 07-18-2013 |
20130188970 | Packaging Platform For Opto-Electronic Assemblies Using Silicon-Based Turning Mirrors - An apparatus for transmitting optical signals includes an interposer for supporting opto-electronic components used to create optical output signals. An enclosure is used to encapsulate the populated interposer assembly and includes a silicon sidewall and a transparent lid. The sidewall is etched to include a turning mirror feature with a reflecting surface at a predetermined angle θ, the turning mirror disposed to intercept the optical output signals and re-direct them through the enclosure's transparent lid. A coverplate is disposed over and aligned with the enclosure, where the coverplate includes a silicon sidewall member that is etched to include a turning mirror element with a reflecting surface at the same angle θ as the enclosure's turning mirror element. The optical signals re-directed by the enclosure then pass through the transparent lid of the enclosure, impinge the turning mirror element of the coverplate, and are then re-directed along the longitudinal axis. | 07-25-2013 |
20130202255 | Single Mode Fiber Array Connector For Opto-Electronic Transceivers - An apparatus for providing single mode optical signal coupling between an opto-electronic transceiver and a single mode optical fiber array takes the form of a lens array and a ferrule component. The lens array includes a plurality of separate lens element disposed to intercept a like plurality of single mode optical output signal from the opto-electronic transceiver and provide as an output a focused version thereof. The ferrule component includes a plurality of single mode fiber stubs that are passively aligned with the lens array and support the transmission of the focused, single mode optical output signals towards the associated single mode optical fiber array. | 08-08-2013 |
20130314707 | Arrangement For Placement And Alignment Of Opto-Electronic Components - An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner. | 11-28-2013 |
20140003457 | Interposer Configuration With Thermally Isolated Regions For Temperature-Sensitive Opto-Electronic Components | 01-02-2014 |
20140169734 | COUPLING LIGHT FROM A WAVEGUIDE ARRAY TO SINGLE MODE FIBER ARRAY - Techniques for coupling light from a waveguide array to a single mode fiber array are described. In an embodiment, lateral misalignment of an array of focusing lenses and an array of optical fiber ferrules held into alignment by a lens holder sub-assembly is compensated by tilting the lens holder sub-assembly with respect to the propagation axis of the light being coupled by the lens holder-subassembly. Since the amount of tilt can be adjusted according to the degree of lateral misalignment, lens holder sub-assemblies manufactured with varying degrees of misalignment may be utilized to couple light into single mode fiber-optic cable. In addition, the same technique can also be used to compensate for other defects as well, such as angular errors in manufacturing or placement of a turning mirror or prism used to direct light into the lens holder sub-assembly. | 06-19-2014 |
20140201994 | LOW-STRESS TSV DESIGN USING CONDUCTIVE PARTICLES - A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via. | 07-24-2014 |
20140217584 | FLOW UNDERFILL FOR MICROELECTRONIC PACKAGES - A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal. | 08-07-2014 |
20140248723 | WAFER SCALE PACKAGING PLATFORM FOR TRANSCEIVERS - A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules. | 09-04-2014 |
20140322864 | LOW CTE INTERPOSER - An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”). | 10-30-2014 |
20150016784 | SELF-ALIGNING CONNECTORIZED FIBER ARRAY ASSEMBLY - An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion. | 01-15-2015 |
20150023377 | INTERPOSER CONFIGURATION WITH THERMALLY ISOLATED REGIONS FOR TEMPERATURE-SENSITIVE OPTO-ELECTRONIC COMPONENTS - An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices. | 01-22-2015 |
Patent application number | Description | Published |
20100022034 | Manufacture of devices including solder bumps - Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly. | 01-28-2010 |
20110006415 | SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process. | 01-13-2011 |
20130149857 | SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process. | 06-13-2013 |
20130328186 | REDUCED STRESS TSV AND INTERPOSER STRUCTURES - A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall. | 12-12-2013 |
20140043685 | Lid Design to Seal Optical Components of a Transceiver Module - Techniques and configurations are provided for packaging optoelectronic devices. In particular, a lid component of an optoelectronic device is provided, and the lid component is configured to cover active components of the optoelectronic device. An optically transparent wall is also provided. The optically transparent wall is coated with an anti-reflective material and configured to interface with a section of the lid component. The optically transparent wall is joined with the section of the lid component such that the optically transparent wall and the lid provide a seal for the active components of the optoelectronic device. Additionally, the lid component has a top surface and a plurality of side surfaces that are coupled to the top surface. An optically transparent wall coated with an anti-reflective material adhesively joins to the top surface and one or more side surfaces. | 02-13-2014 |
20140217607 | REDUCED STRESS TSV AND INTERPOSER STRUCTURES - A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall. | 08-07-2014 |
Patent application number | Description | Published |
20100235832 | Storage Virtualization With Virtual Datastores - Computer implemented methods and systems for providing storage virtualization of physical storage include receiving a request for storage from a virtual machine during provisioning of the virtual machine. The request includes a capability and quota requirement for storage as required by the virtual machine. A virtual datastore that satisfies the capability and quota requirements of the request is identified. If not found, one or more volumes, that satisfy the storage requirements, are discovered or created. A virtual datastore is created and maps to one or more volumes which have unique volume identifiers. A unique virtual datastore identifier is generated for the virtual datastore. The virtual datastore identifier is distinct from the volume identifiers of the underlying volumes. The volumes are mapped to the virtual datastore while retaining the virtual datastore identifier for the virtual datastore. The virtual datastore identifier for the virtual datastore is not changed when modifications are made to the physical storage entities mapped to the virtual datastore. | 09-16-2010 |
20130054890 | MANAGEMENT SYSTEM AND METHODS FOR OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. To facilitate creation and management of logical storage volumes, special application programming interfaces (APIs) have been developed. The special APIs include commands to create a logical storage volume, bind, unbind, and rebind the logical storage volume, extend the size of the logical storage volume, clone the logical storage volume, and move the logical storage volume. | 02-28-2013 |
20130054910 | VIRTUAL MACHINE SNAPSHOTTING IN OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects within logical storage containers. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. A snapshot profile can be separately defined for each of these logical storage volumes, even for those that are within the same storage container. The snapshot profile for a logical storage volume defines whether or not snapshot is enabled for that logical storage volume, the frequency of the snapshot, and the number of snapshots to be retained. | 02-28-2013 |
20130054932 | OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings. | 02-28-2013 |
20130055248 | METHOD OF BALANCING WORKLOADS IN OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. When traffic through a particular protocol endpoint is busy, the logical storage volume undergoes a rebind process pursuant to which the logical storage volume is bound to a new protocol endpoint, and the binding to the old protocol endpoint is removed upon completion of all pending input-output commands issued through the old protocol endpoint. | 02-28-2013 |
20140095826 | SYSTEM AND METHOD FOR ALLOCATING DATASTORES FOR VIRTUAL MACHINES - A datastore for a virtual machine that can be executed on a host computer networked to a physical storage system is allocated by a server. The server generates a unique identifier to associate with the datastore, wherein the unique identifier mimics a form of identifier that is generated by the physical storage system to identify volumes of physical storage in the physical storage system that are accessible to the host computer. At least one volume of physical storage in the physical storage system having physical storage available to satisfy the request to allocate the datastore is identified and the server maintains a mapping of the unique identifier to the at least one volume of physical storage and provides the mapping to the host computer upon running the virtual machine, thereby enabling the host computer to store data for the datastore in the at least one volume of physical storage. | 04-03-2014 |
20140244929 | OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings. | 08-28-2014 |
20140245016 | MANAGEMENT SYSTEM AND METHODS FOR OBJECT STORAGE SYSTEM - The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. To facilitate creation and management of logical storage volumes, special application programming interfaces (APIs) have been developed. The special APIs include commands to create a logical storage volume, bind, unbind, and rebind the logical storage volume, extend the size of the logical storage volume, clone the logical storage volume, and move the logical storage volume. | 08-28-2014 |
20140325170 | Conversion of Virtual Disk Snapshots Between Redo and Copy-on-Write Technologies - A framework for converting between copy-on-write (COW) and redo-based technologies is disclosed. To take a virtual disk snapshot, disk descriptor files, which include metadata information about data stored in virtual volumes (vvols), are “swizzled” such that the descriptor file for a latest redo log, to which IOs are currently performed, points to the base vvol of a COW-based vvol hierarchy. A disk descriptor file previously associated with the base vvol may also be updated to point to the vvol newly created by the snapshot operation. To revert to an earlier disk state, a snapshot may be taken before copying contents of a snapshot vvol of the COW-based vvol hierarchy to a base vvol of the hierarchy, thereby ensuring that the reversion can be rolled back if it is unsuccessful. Reference counting is performed to ensure that vvols in the vvol hierarchy are not orphaned in delete and revert use cases. Differences between vvols in the COW-based vvol hierarchy are used to clone the hierarchy and to migrate the hierarchy to a redo-based disk hierarchy. | 10-30-2014 |