Doering
Andreas Doering, Adliswil CH
Andreas C. Doering, Adliswil CH
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20080270754 | USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION - A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well. | 10-30-2008 |
Andreas C. Doering, Rueschlikon CH
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20120303948 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 11-29-2012 |
20130019108 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 01-17-2013 |
Andreas C. Doering, Zufikon CH
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20130124786 | MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE - The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2). | 05-16-2013 |
20130198455 | CACHE MEMORY GARBAGE COLLECTOR - A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced. | 08-01-2013 |
20140293533 | Cooling Electronic Components and Supplying Power to the Electronic Components - A mechanism is provided for cooling electronic components of a printed circuit board module and for supplying power to the electronic components of the printed circuit board module. The computer module comprises a printed circuit board module, wherein the electronic components are attached to a first side of the printed circuit board module, and a cooling module being attached to a second side of the printed circuit board, being arranged in parallel to the printed circuit board and having a first layer being thermally and electrically conductive. The first layer is arranged such that heat is dissipated from the printed circuit board module and that power from a power source is supplied to the electronic components of the printed circuit board module. | 10-02-2014 |
20150089253 | Power Converter for a Computer Device and Method for Operating a Power Converter - A power converter for a computer device having a processing unit and a memory device is suggested. The power converter is connectable to the computer device by a coupling circuitry, wherein the computer device requires an actual input voltage. The power converter comprises a voltage regulator, a measuring entity, and a determining entity. The voltage regulator is configured to control an actual output voltage for the coupling circuitry based on a determined reference output voltage. The measuring entity is configured to measure an actual output current of the voltage regulator output to the coupling circuitry. The determining entity is configured to determine the determined reference output voltage such that the determined reference output voltage equals a sum of the actual input voltage of the computer device and the product of the measured actual output current and a resistance of the coupling circuitry. | 03-26-2015 |
Andreas Ch. Doering, Adliswil CH
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20080291913 | Detecting a timeout of elements in an element processing system - Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed. | 11-27-2008 |
Andreas Christian Doering, Zufikon CH
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20130007375 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |
20130007398 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |
20130021061 | TUNNEL FIELD-EFFECT TRANSISTOR - A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region. | 01-24-2013 |
Falk Doering, Amiens FR
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20130284852 | Drum Assembly And Method Of Assembling The Drum Assembly - A drum assembly includes a core having a first end and a second end opposite the first end, a first hub coupled to the core adjacent the first end of the core, a second hub coupled to the core adjacent the second end of the core, a first flange releasably coupled to the first hub, the first flange including a body having an inner surface, an outer support structure, and an aperture formed therethrough, and a second flange releasably coupled to the second hub, the second flange including a body having an inner surface, an outer support structure, and an aperture formed therethrough. | 10-31-2013 |