Patent application number | Description | Published |
20090153401 | MOTION DETECTION FOR TRACKING - An apparatus and method for tracking a target wherein a new position fix is taken when the measured movement of the target is more than a predetermined threshold amount or when the position fix has not been updated in a predetermined interval. The apparatus and method minimize energy use and network resources by performing position determination fixes only when needed. | 06-18-2009 |
20100090852 | GEOGRAPHICAL BOUNDARY BASED TRACKING - An apparatus, method and system for geographical tracking entry and/or exiting of an asset into and/or out of a defined geographical boundary and reporting the same. Entry and exit tests compare position fixes with various thresholds and parameters to determine if the asset has entered or exited the geographical boundary. Tests are sequenced such that tests having lower levels of complexity (lower order) are performed before tests having higher levels of complexity (higher order). In this way, most position fixes are processed using computations having a lower order of mathematical complexity than conventionally implemented. | 04-15-2010 |
20100098135 | METHOD AND APPARATUS FOR AVOIDING INTERFERENCE BETWEEN COEXISTING WIRELESS SYSTEMS - Apparatuses and methods for avoiding interference between wireless systems are described herein. One embodiment of the disclosure provides an apparatus for avoiding interference between at least one transmitter and at least one receiver within at least one wireless device. The apparatus comprises a first processing circuit configured to determine whether one or more bins are affected by interference from a transmitter based on predetermined information. The apparatus further comprises a second processing circuit configured to mitigate the interference from the transmitter by at least one of the transmitter and a receiver if it is determined that the one or more bins are affected | 04-22-2010 |
20100250134 | DEAD RECKONING ELEVATION COMPONENT ADJUSTMENT - The subject matter disclosed herein relates to adjusting an elevation component of a estimated location based, at least in part, on sensor-based dead reckoning. | 09-30-2010 |
20100284424 | SYSTEM AND METHOD FOR ADAPTING TRANSMIT DATA BLOCK SIZE AND RATE BASED ON QUALITY OF COMMUNICATION LINK - System and method for transmitting data to a remote communication device to achieve desirable transmit data block size and data rate based on measurements of the communication link quality to the remote device. The method entails selecting an initial transmit data rate and power based on an initial measurement of the link quality, and a default size for the transmit data block. The data block is then transmitted to the remote, and an acknowledgement (ACK) message is received from the remote. If the ACK message indicates that the data block was properly received, the size for the next data block to be transmitted is increased. Otherwise, the size for the next data block may be decreased or remain the same. Additionally, the transmit data rate may be increased if the remote properly receives a defined number of consecutive data blocks, or decreased if the remote does not receive a defined number of consecutive data blocks. | 11-11-2010 |
20110206146 | CHANNEL ESTIMATION USING REPLICAS ZERO FORCING - Channel estimation for a wireless Orthogonal Frequency Division Multiplexed (OFDM) link having pilots on at least some carriers in at least some symbols may be implemented by performing first and second channel estimation processes. The first channel estimation process uses only frequency domain interpolation of the pilots to obtain a first candidate channel estimate for the OFDM link, and the second channel estimation process uses both time domain interpolation and frequency domain interpolation of the pilots to obtain a second candidate channel estimate for the OFDM link. One of the first and second candidate channel estimates is selected for processing a communication received via the OFDM link. | 08-25-2011 |
20110261905 | COMPRESSED SENSING CHANNEL ESTIMATION IN OFDM COMMUNICATION SYSTEMS - Methods and devices for receiving Orthogonal Frequency Domain Multiplexed (OFDM) wireless signals employ compressed sensing-based estimation techniques, exploiting the common sparseness of the wireless channel, to achieve signal reception in the presence of significant Doppler spread. When implemented for an ISDB-T mobile TV standard signal, the compressed sensing channel estimation algorithm enables data reception in Doppler spread conditions beyond the capabilities of conventional channel estimation methods. | 10-27-2011 |
20110304776 | METHOD AND APPARATUS FOR ATSC SIGNAL PROCESSING - Embodiment methods and apparatus enable ATSC receiver devices to receive and process ATSC-M/H training sequences in order to improve the reception and decoding of an ATSC service. A processor within the ATSC receiver device may be configured to receive training sequences 1 and 2 of the ATSC-M/H signal. In an embodiment, the ATSC-M/H training sequence 2 may be received by correlating symbols of the two halves of the training sequence 2. If the result of correlating the symbols is greater than or equal to a threshold, the ATSC-M/H training sequence 2 may be received by the ATSC receiver and a counter for the training sequence 1 may start. The ATSC receiver may correlate two consecutive training sequences 1 to perform fine residual frequency error estimation. | 12-15-2011 |
20120069196 | METHOD AND APPARATUS FOR SAVING POWER IN ATSC-M/H MOBILE DEVICES - Methods and apparatus enable ATSC-M/H mobile devices to conserve power by entering a high power state at a slot reception start time that is after the start of an ATSC M/H slot and entering a low power state at a slot reception stop time before the end of the ATSC M/H slot. Data lost due to the device being in a low power state during the time between the start time of the ATSC M/H slot and the activation time and during the time between the deactivation time and the end of the ATSC M/H slot are recovered using error correction processing. The slot receive and slot reception stop times may be based on the received signal quality. The receiver circuitry may also be deactivated when the entire payload has been received and skip reception of remaining slots. | 03-22-2012 |
20130169433 | GEOGRAPHICAL BOUNDARY BASED TRACKING - An apparatus, method and system for geographical tracking entry and/or exiting of an asset into and/or out of a defined geographical boundary and reporting the same. Entry and exit tests compare position fixes with various thresholds and parameters to determine if the asset has entered or exited the geographical boundary. Tests are sequenced such that tests having lower levels of complexity (lower order) are performed before tests having higher levels of complexity (higher order). In this way, most position fixes are processed using computations having a lower order of mathematical complexity than conventionally implemented. | 07-04-2013 |
20140256246 | DUAL-MODE LOW-NOISE BLOCK CONTROLLER - Exemplary embodiments are related to a dual-mode controller. A device may include a controller configured to convey a signal to a low-noise block (LNB) via a transmission line and circuitry configured to sense at least one parameter of the transmission line. The device may further include logic coupled to the circuitry and configured to determine whether the transmission line is available for transmission based on the at least one sensed parameter. | 09-11-2014 |
Patent application number | Description | Published |
20090164763 | METHOD AND APPARATUS FOR A DOUBLE WIDTH LOAD USING A SINGLE WIDTH LOAD PORT - A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load. | 06-25-2009 |
20090172355 | INSTRUCTIONS WITH FLOATING POINT CONTROL OVERRIDE - Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described. | 07-02-2009 |
20090172358 | IN-LANE VECTOR SHUFFLE INSTRUCTIONS - In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand. | 07-02-2009 |
20090172363 | MIXING INSTRUCTIONS WITH DIFFERENT REGISTER SIZES - When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers. | 07-02-2009 |
20090172365 | Instructions and logic to perform mask load and store operations - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 07-02-2009 |
20090265409 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 10-22-2009 |
20110093682 | METHOD AND APPARATUS FOR PACKING DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element. | 04-21-2011 |
20110153707 | MULTIPLYING AND ADDING MATRICES - An apparatus and method are described for multiplying and adding matrices. For example, one embodiment of a method comprises decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements. | 06-23-2011 |
20110219214 | Microprocessor having novel operations - A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation. | 09-08-2011 |
20110264895 | METHOD AND APPARATUS FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 10-27-2011 |
20110307687 | IN-LANE VECTOR SHUFFLE INSTRUCTIONS - In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand. | 12-15-2011 |
20120079251 | MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS - A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction. | 03-29-2012 |
20120166509 | Performing Reciprocal Instructions With High Accuracy - In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed. | 06-28-2012 |
20120198210 | Microprocessor Having Novel Operations - A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation. | 08-02-2012 |
20120216018 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 08-23-2012 |
20120331028 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 12-27-2012 |
20130067204 | Instructions With Floating Point Control Override - Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described. | 03-14-2013 |
20130091190 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 04-11-2013 |
20130117537 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117538 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117539 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117540 | METHOD AND APPARATUS FOR UNPACKING PACKED DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117547 | Method and Apparatus for Unpacking and Moving Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130124833 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124834 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124835 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130191615 | INSTRUCTIONS AND LOGIC TO PERFORM MASK LOAD AND STORE OPERATIONS - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 07-25-2013 |
20130198254 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 08-01-2013 |
20130212360 | In-Lane Vector Shuffle Instructions - In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand. | 08-15-2013 |
20130219151 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 08-22-2013 |
20130262547 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 10-03-2013 |
20130262836 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-subtract operations on data elements in the first and second packed data. | 10-03-2013 |
20130290685 | FLOATING POINT ROUNDING PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed. | 10-31-2013 |
20140119657 | EFFICIENT IMAGE ANALYSIS APPARATUS AND TECHNIQUE - An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel. | 05-01-2014 |
20140222883 | MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION - A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed. | 08-07-2014 |
20150088946 | FLOATING POINT SCALING PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed. | 03-26-2015 |
20150088947 | MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS - A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction. | 03-26-2015 |