Patent application number | Description | Published |
20080272814 | PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL - A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment. | 11-06-2008 |
20080273528 | PHASE SELECT CIRCUIT WITH REDUCED HYSTERESIS EFFECT - A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal. | 11-06-2008 |
20080297216 | TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE - An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal. | 12-04-2008 |
20100171547 | PSEUDO BANDGAP VOLTAGE REFERENCE CIRCUIT - A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor. | 07-08-2010 |
20120133459 | PASSIVE FILTER AND AC COUPLER RECEIVER INTERFACE - An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus. | 05-31-2012 |
20130162310 | CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY - A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit. | 06-27-2013 |
20130162357 | OSCILLATOR WITH HIGHLY-ADJUSTABLE BANG-BANG CONTROL - A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal. | 06-27-2013 |
20140049292 | INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY - An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format. | 02-20-2014 |
20140176098 | FEED-FORWARD COMPENSATION FOR LOW-DROPOUT VOLTAGE REGULATOR - A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage. | 06-26-2014 |
20150041955 | Multi-Die Fine Grain Integrated Voltage Regulation - A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. | 02-12-2015 |