Patent application number | Description | Published |
20100005234 | Enabling functional dependency in a multi-function device - In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed. | 01-07-2010 |
20130346774 | PROVIDING ENERGY EFFICIENT TURBO OPERATION OF A PROCESSOR - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to prevent a first core from execution at a requested turbo mode frequency if the first core has a stall rate greater than a first stall threshold, and concurrently allow a second core to execute at a requested turbo mode frequency if the second core has a stall rate less than a second stall threshold. Other embodiments are described and claimed. | 12-26-2013 |
20140006761 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS | 01-02-2014 |
20140068284 | Configuring Power Management Functionality In A Processor - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed. | 03-06-2014 |
20140068290 | Configuring Power Management Functionality In A Processor - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed. | 03-06-2014 |
20140157021 | ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed. | 06-05-2014 |
20140189239 | PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES - A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed. | 07-03-2014 |
20140195829 | DYNAMICALLY COMPUTING AN ELECTRICAL DESIGN POINT (EDP) FOR A MULTICORE PROCESSOR - In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed. | 07-10-2014 |
20140208141 | DYNAMICALLY CONTROLLING INTERCONNECT FREQUENCY IN A PROCESSOR - In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed. | 07-24-2014 |