Patent application number | Description | Published |
20080234134 | Buffer layers for coated conductors - A composite structure is provided including a base substrate, an IBAD oriented material upon the base substrate, and a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material. Additionally, an article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and a thick film upon the cubic metal oxide material. Finally, a superconducting article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and an yttrium barium copper oxide material upon the cubic metal oxide material. | 09-25-2008 |
20090137401 | Chemical Solution Deposition Method of Fabricating Highly Aligned MgO Templates - A superconducting article includes a substrate having an untextured metal surface; an untextured barrier layer of La | 05-28-2009 |
20100009176 | High temperature superconducting thick films - An article including a substrate, a layer of an inert oxide material upon the surface of the substrate, (generally the inert oxide material layer has a smooth surface, i.e., a RMS roughness of less than about 2 nm), a layer of an amorphous oxide or oxynitride material upon the inert oxide material layer, a layer of an oriented cubic oxide material having a rock-salt-like structure upon the amorphous oxide material layer is provided together with additional layers such as at least one layer of a buffer material upon the oriented cubic oxide material layer or a HTS top-layer of YBCO directly upon the oriented cubic oxide material layer. With a HTS top-layer of YBCO upon at least one layer of a buffer material in such an article, J | 01-14-2010 |
20100022397 | METHOD FOR IMPROVING PERFORMANCE OF HIGH TEMPERATURE SUPERCONDUCTORS WITHIN A MAGNETIC FIELD - The present invention provides articles including a base substrate including a layer of an oriented cubic oxide material having a rock-salt-like structure layer thereon; and, a buffer layer upon the oriented cubic oxide material having a rock-salt-like structure layer, the buffer layer having an outwardly facing surface with a surface morphology including particulate outgrowths of from 10 nm to 500 run in size at the surface, such particulate outgrowths serving as flux pinning centers whereby the article maintains higher performance within magnetic fields than similar articles without the necessary density of such outgrowths. | 01-28-2010 |
20100093547 | Buffer layer for thin film structures - A composite structure including a base substrate and a layer of a mixture of strontium titanate and strontium ruthenate is provided. A superconducting article can include a composite structure including an outermost layer of magnesium oxide, a buffer layer of strontium titanate or a mixture of strontium titanate and strontium ruthenate and a top-layer of a superconducting material such as YBCO upon the buffer layer. | 04-15-2010 |
Patent application number | Description | Published |
20090108466 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 04-30-2009 |
20090170319 | METHOD OF FORMING AN INTERLAYER DIELECTRIC MATERIAL HAVING DIFFERENT REMOVAL RATES DURING CMP - By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements. | 07-02-2009 |
20120220119 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 08-30-2012 |